CN117353858B - Audio clock synchronization method, system, equipment and readable storage medium - Google Patents
Audio clock synchronization method, system, equipment and readable storage medium Download PDFInfo
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Abstract
The application discloses an audio clock synchronization method, an audio clock synchronization system, audio clock synchronization equipment and a readable storage medium, relates to the technical field of clock synchronization, and is applied to an audio synchronization system, wherein the audio synchronization system comprises a master device and a slave device, the slave device comprises a system clock circuit and a digital-to-analog converter clock circuit, and the method comprises the following steps: starting the master device to read a micro data frame, determining the total micro frame duration of the master device for reading the micro data frame, and determining a first working clock of the master device based on the total micro frame duration; after detecting that the master device finishes reading the micro data frame, acquiring the current system time of the slave device, and taking the current system time as a second working clock of the slave device; and adjusting the frequency offset of the system clock circuit and the digital-to-analog converter clock circuit according to the clock difference between the first working clock and the second working clock, so that the master device and the slave device are in audio clock synchronization. The method and the device realize the audio clock synchronization of the master device and the slave device.
Description
Technical Field
The present disclosure relates to the field of clock synchronization technologies, and in particular, to an audio clock synchronization method, system, device, and readable storage medium.
Background
With the popularity of host devices such as computers in teleconferencing, a great deal of applications have also emerged through related peripherals (or called slaves) connected by communication, and Audio devices connected by a USB (Universal Serial Bus ) are one type of most used in communication, where Audio data is usually transmitted by a UAC protocol (USB Audio Class, USB Audio protocol) at the host device end, and this type of protocol itself does not provide a mechanism for clock synchronization between the host device and the slave device, and if clock synchronization is not performed, sound jamming occurs during long-time recording or playback.
The existing synchronous audio clock mode is generally that a slave device establishes a buffer area, a program judges the change of the size of the buffer area, if the buffer area becomes too small and fast, the data consumption rate of the buffer area is reduced by increasing the sampling rate resampling mode or the data supplementing mode of the slave device, so that the data consumption rate of the buffer area is basically consistent with the UAC sound card speed of the master device, otherwise, the data consumption rate of the buffer area is accelerated by decreasing the sampling rate resampling mode or the data losing mode. This way of setting the buffer does not essentially achieve synchronization of the master and slave audio clocks, but adjusts the sampling rate after digital-to-analog conversion of the audio signal, which may cause problems that the frequency spectrum of the audio data is affected to some extent, the sound quality of the audio data is affected, etc.
In summary, how to achieve clock synchronization between a master device and a slave device is a technical problem to be solved in the art.
Disclosure of Invention
The main objective of the present application is to provide an audio clock synchronization method, system, device and readable storage medium, which aim to solve the technical problem of how to realize audio clock synchronization of a master device and a slave device.
In order to achieve the above object, the present application provides an audio clock synchronization method, which is applied to an audio synchronization system, wherein the audio synchronization system includes a master device and a slave device, the slave device includes a system clock circuit and a digital-to-analog converter clock circuit, and the audio clock synchronization method includes the following steps:
starting the master device to read a micro data frame, determining the total micro frame duration of the master device for reading the micro data frame, and determining a first working clock of the master device based on the total micro frame duration;
after detecting that the master device finishes reading the micro data frame, acquiring the current system time of the slave device, and taking the current system time as a second working clock of the slave device;
and adjusting the frequency offset of the system clock circuit and the digital-to-analog converter clock circuit according to the clock difference between the first working clock and the second working clock so that the master device and the slave device are in audio clock synchronization.
Optionally, the step of determining a total micro-frame duration of the micro-data frame read by the master device includes:
acquiring single micro-frame time length of the main equipment, and determining the micro-frame number of the micro-data frame read by the main equipment;
multiplying the micro frame number by the single micro frame time length to obtain the total micro frame time length of the micro data frame read by the main equipment.
Optionally, the step of determining the first working clock of the master device based on the total micro-frame duration includes:
determining the starting time of the master device for starting to read the micro data frame, determining the micro frame time based on the total micro frame time and the starting time, and taking the micro frame time as a first working clock of the master device, wherein the time between the micro frame time and the starting time is the total micro frame time.
Optionally, the step of adjusting the frequency offset of the system clock circuit and the digital-to-analog converter clock circuit according to determining the clock difference between the first working clock and the second working clock includes:
determining a clock difference between the first operating clock and the second operating clock;
and if the clock difference is greater than a preset threshold, adjusting the frequency offset of the system clock circuit and the digital-to-analog converter clock circuit, and returning to execute the step of starting the main equipment to read the micro data frame until the clock difference between the first working clock and the second working clock is less than or equal to the preset threshold.
Optionally, the step of adjusting the frequency offset of the system clock circuit and the digital-to-analog converter clock circuit includes:
if the two working clocks are larger than the first working clock, reducing the frequency offset of the system clock circuit and the frequency offset of the digital-to-analog converter clock circuit;
and if the second working clock is smaller than the first working clock, increasing the frequency offset of the system clock circuit and the frequency offset of the digital-to-analog converter clock circuit.
Optionally, the step of adjusting the frequency offset between the system clock circuit and the digital-to-analog converter clock circuit further includes:
detecting whether the system clock circuit and the digital-to-analog converter clock circuit are subjected to first frequency offset adjustment or not;
if yes, the first working clock and the second working clock are input into a preset frequency offset calculation model, a target frequency offset is obtained through output, the frequency offset of the system clock circuit is set to be the target frequency offset, and the frequency offset of the digital-to-analog converter clock circuit is set to be the target frequency offset.
Optionally, after the step of detecting whether the system clock circuit and the digital-to-analog converter clock circuit are the first frequency offset adjustment, the method further includes:
if not, acquiring a first current frequency offset of the system clock circuit and acquiring a second current frequency offset of the digital-to-analog converter clock circuit;
adjusting the first current frequency offset based on a preset algorithm to obtain a target frequency offset, wherein the preset algorithm comprises a proportional-integral-derivative algorithm;
and adjusting the first current frequency offset of the system clock circuit to the target frequency offset, and adjusting the second current frequency offset of the digital-to-analog converter clock circuit to the target frequency offset.
In addition, to achieve the above object, the present application further provides an audio clock synchronization system, where the audio clock synchronization system includes a master device and a slave device, and the slave device includes a system clock circuit and a digital-to-analog converter clock circuit, and the audio clock synchronization system further includes:
the first determining module is used for starting the master device to read the micro data frame, determining the total micro frame duration of the master device for reading the micro data frame, and determining a first working clock of the master device based on the total micro frame duration;
the second determining module is used for acquiring the current system time of the slave device after detecting that the master device finishes reading the micro data frame, and taking the current system time as a second working clock of the slave device;
and the synchronization module is used for adjusting the frequency offset of the system clock circuit and the digital-to-analog converter clock circuit according to the clock difference between the first working clock and the second working clock so as to synchronize the audio clocks of the master equipment and the slave equipment.
In addition, to achieve the above object, the present application further provides an audio clock synchronization apparatus, including: the system comprises a memory, a processor and an audio clock synchronization program stored in the memory and capable of running on the processor, wherein the audio clock synchronization program realizes the steps of the audio clock synchronization method when being executed by the processor.
In addition, in order to achieve the above object, the present application further provides a readable storage medium, on which an audio clock synchronization program is stored, which when executed by a processor, implements the steps of the audio clock synchronization method as described above.
The method comprises the steps of determining total micro-frame duration of a micro-data frame read by a main device by starting the micro-data frame read by the main device, and determining a first working clock of the main device based on the total micro-frame duration; after detecting that the master device finishes reading the micro data frame, acquiring the current system time of the slave device, and taking the current system time as a second working clock of the slave device; and adjusting the frequency offset of a system clock circuit and a digital-to-analog converter clock circuit of the slave device according to the clock difference between the first working clock and the second working clock, so that the master device and the slave device are synchronous in audio frequency clock. Thus, compared with the mode of setting the buffer area by the slave device in the prior art, the embodiment of the invention quantitatively determines the working clocks of the master device and the slave device, compares the clock differences between the working clocks to determine whether the clocks of the master device and the slave device are synchronous, and when the clocks of the slave device and the slave device are not synchronous, based on the frequency offset (ppm, parts per million), the allowable deviation value under a specific center frequency is indicated to be the deviation of a clock generated every 1million clock, if the frequency offset is increased, the clock is equivalent to more than the clock before, and the clock is equivalent to increased, otherwise, the clock is equivalent to reduced, and the frequency offset of a clock circuit of the slave device system and the clock circuit of the digital-analog converter is adjusted, so that the effect of adjusting the clocks of the slave device is achieved until the clocks of the slave device and the slave device are synchronous. Therefore, the working clocks of the master device and the slave device are determined through quantization, so that the master device and the slave device are synchronized through adjusting frequency offset, and the audio clock synchronization of the master device and the slave device is realized. Further, in the embodiment of the application, the audio clock is synchronized before the audio signal is subjected to digital-to-analog conversion, rather than changing the data through software or a signal processing mode after the audio signal is subjected to digital-to-analog conversion, so that the frequency spectrum and the tone quality of the audio data are not affected.
Drawings
The implementation, functional features and advantages of the present application will be further described with reference to the accompanying drawings in conjunction with the embodiments.
FIG. 1 is a schematic diagram of a terminal/system architecture of a hardware operating environment according to an embodiment of the present application;
FIG. 2 is a flowchart of a first embodiment of an audio clock synchronization method according to the present application;
FIG. 3 is a schematic diagram of a master-slave device micro data frame read in the audio clock synchronization method of the present application;
FIG. 4 is a schematic diagram of frequency offset adjustment of a clock circuit in the audio clock synchronization method of the present application;
fig. 5 is a schematic diagram of a system module of the audio clock synchronization system of the present application.
Detailed Description
It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an audio clock synchronization device of a hardware running environment according to an embodiment of the present application.
As shown in fig. 1, the audio clock synchronization apparatus may include: a processor 1001, such as a central processing unit (Central Processing Unit, CPU), a communication bus 1002, a user interface 1003, a network interface 1004, a memory 1005. Wherein the communication bus 1002 is used to enable connected communication between these components. The user interface 1003 may include a Display, an input unit such as a Keyboard (Keyboard), and the optional user interface 1003 may further include a standard wired interface, a wireless interface. The network interface 1004 may optionally include a standard wired interface, a WIreless interface (e.g., a WIreless-FIdelity (WI-FI) interface). The Memory 1005 may be a high-speed random access Memory (Random Access Memory, RAM) Memory or a stable nonvolatile Memory (NVM), such as a disk Memory. The memory 1005 may also optionally be a storage system separate from the processor 1001 described above.
It will be appreciated by those skilled in the art that the structure shown in fig. 1 is not limiting of the audio clock synchronization device and may include more or fewer components than shown, or may combine certain components, or a different arrangement of components.
As shown in fig. 1, an operating system, a data storage module, a network communication module, a user interface module, and an audio clock synchronization program may be included in the memory 1005 as one type of storage medium.
In the audio clock synchronization device shown in fig. 1, the network interface 1004 is mainly used for data communication with other devices; the user interface 1003 is mainly used for data interaction with a user; the processor 1001 and the memory 1005 in the audio clock synchronization device may be provided in the audio clock synchronization device, where the audio clock synchronization device invokes an audio clock synchronization program stored in the memory 1005 through the processor 1001, and executes the audio clock synchronization method provided in the embodiment of the present application.
Referring to fig. 2, fig. 2 is a flowchart of a first embodiment of an audio clock synchronization method according to the present application. It should be noted that although a logical order is depicted in the flowchart, in some cases the steps depicted or described may be performed in a different order than presented herein.
In this embodiment, the audio clock synchronization method is applied to the terminal device. It should be understood that the audio clock synchronization method of the present application may of course be applied specifically to other terminal devices in different possible embodiments, based on different design requirements of the actual application.
In this embodiment, the audio clock synchronization method is applied to an audio synchronization system, the audio synchronization system includes a master device and a slave device, the slave device includes a system clock circuit and a digital-to-analog converter clock circuit, and the audio clock synchronization method includes the following steps:
step S10, starting the master device to read a micro data frame, determining the total micro frame duration of the master device for reading the micro data frame, and determining a first working clock of the master device based on the total micro frame duration;
it will be appreciated that the master device also includes clock circuitry for providing an operating clock thereto. The host device may be a device that provides audio data, such as a computer, a cell phone, or the like. The slave device may be a device that receives audio data, such as a microphone, a stylus, a microphone, and the like.
The master device is in communication connection with the slave device, specifically can be in communication connection through USB, audio data are transmitted between the master device and the slave device through USB, and UAC protocol can be used for transmitting audio data between the master device and the slave device. When the USB transmits data, a fixed SOF (Start Of Frame) time is used, and when the UAC transmits data, a synchronous transmission mode is used, wherein the mode uses a fixed rate, that is, the UAC transmission rate and the SOF time have a fixed proportional relationship, so that the working clock Of the master device can be quantized through the SOF time, and the working clock Of the slave device is adjusted, and the clock Of the master device and the missing Of the slave device are kept consistent within a certain range.
Further, the master device may be started to read a preset number of micro data frames from a preset start time, where the preset number may be any number, such as 10 micro frames, 15 micro frames, 20 micro frames, etc., or start to read micro data frames from the preset start time for a preset duration, where the preset duration may be any duration, such as 1 second, 2 seconds, etc.
In one possible implementation manner, the step of determining the total micro-frame duration of the micro-data frame read by the master device includes:
step S101, acquiring single micro-frame time length of the main equipment, and determining the micro-frame number of the micro-data frame read by the main equipment;
step S102, multiplying the micro frame number by the single micro frame duration to obtain the total micro frame duration of the micro data frame read by the main equipment.
The single micro-frame duration is a micro-frame duration specified by the USB protocol, specifically 125 microseconds. Frames and micro-frames are the concept of a physical layer time reference, and the USB protocol specifies full-speed and low-speed devices SOF time-frame time of 1 millisecond, whereas high-speed devices, each frame is divided into 8 micro-frames, SOF time-micro-frame time of 125 microseconds. After the USB master device and the slave device controller are synchronized, the starting point of each micro-frame starts to transmit data, and in one micro-frame time, the USB trains each device to perform control transmission, interrupt transmission, batch transmission and synchronous transmission in one micro-frame transmission time.
When the micro-frame starting time comes, the controller sends an interrupt to the CPU of the main equipment system, the interrupt processing function is driven to process the micro-frame starting, various transmissions are configured into the channel of the controller, then the main equipment starts to work, each device is trained according to the configured channel, and a certain endpoint corresponding to the channel. When the transmission of a certain channel is completed, the main device interrupts the CPU, after the driving process is completed, the channel is cleared, and then the next channel is configured.
In this embodiment, preferably, taking a micro frame, that is, a micro data frame as an example, a single micro frame duration is obtained, where the single micro frame duration of the micro frame is 125 microseconds.
The preset start time may be any set start time, and it is to be noted that the master device and the slave device start to quantize the working clock from the same preset start time. For convenience of description and explanation, the preset start time is denoted as t0 in this embodiment.
In addition, the master device may also be started to read the micro data frame with the preset duration from the preset start time, the micro frame number read in the preset duration is determined, the micro frame number is multiplied by the single micro frame duration to obtain the total micro frame duration of the micro data frame read by the master device, if the master device reads the US port physical layer ((Port Physical Layer, PHY) micro frame counter register to be f0 when the preset start time is assumed, after the preset duration, the micro frame is f1, and the read micro frame number is (f 1-f 0).
The USB uses a fixed SOF time to obtain the actual clock rate of the primary device based on the micro-frame number read by the primary device. For convenience of subsequent explanation and description, the length of the micro-frame of the note is m, and the number of the micro-frames is f, so that the total micro-frame length of the master device is m×f.
In one possible implementation manner, the step of determining the first working clock of the master device based on the total micro-frame duration includes:
step S103, determining a start time when the master device starts to read the micro data frame, determining a micro frame time based on the total micro frame time and the start time, and taking the micro frame time as a first working clock of the master device, wherein a time length between the micro frame time and the start time is the total micro frame time length.
The micro-frame time is h1=t0+f×m. Therefore, the embodiment converts the reading of the micro-frame into time, the master device and the slave device transmit audio data, which is the time which cannot be perceived, the master device reads the data frame, and the slave device receives the data frame, so that the reading rate of the data frame read by the master device is synchronous with the receiving rate of the data frame received by the slave device, and the audio clock synchronization of the master device and the slave device can be realized.
Step S20, after detecting that the master device finishes reading the micro data frame, acquiring the current system time of the slave device, and taking the current system time as a second working clock of the slave device;
for a slave device, the receiving rate of the data frame can be measured by the sampling rate of a digital-to-analog converter (analog to Digital Converter, ADC), the sampling rate of the digital-to-analog converter is related to the digital-to-analog converter clock, if the slave device performs a preset number of samples in one clock period of the digital-to-analog converter, the shorter the clock period, the faster the sampling rate of the digital-to-analog converter.
The system clock circuit is used for providing a system clock, i.e. providing a clock signal for system time, i.e. increasing the time of a high-level clock signal by 1 second, the digital-to-analog converter clock is used for providing a digital-to-analog converter clock, i.e. providing a clock signal for the digital-to-analog converter, so that the digital-to-analog converter works, i.e. a high-level clock signal, the digital-to-analog converter performs data frame sampling once, and the system clock and the ADC clock are obtained by frequency multiplication or frequency division of an external crystal oscillator through a multi-stage Phase-locked loop (PLL), i.e. the system clock and the ADC clock are directly in a proportional relationship, so that the ADC clock can be effectively reflected through the system clock.
The master device starts to read the micro data frame from t0, and the master device finishes reading the micro data frame when h1 is set, and the slave device reads the system time, namely the system time at the moment is t1, and t1 is taken as a second working clock of the slave device. Therefore, the clock taking the USB micro-frame as the reference at the main equipment side and the clock speed of the system clock at the slave equipment side can be compared by comparing h1 with t1, and the system clock rate is adjusted, so that the USB micro-frame clock is connected to the system clock.
Step S30, according to determining the clock difference between the first working clock and the second working clock, adjusting the frequency offset between the system clock circuit and the digital-to-analog converter clock circuit, so that the master device and the slave device are in audio clock synchronization.
The clock difference between the first working clock and the second working clock is determined, the clock difference can be an absolute value difference, the first working clock is recorded as h1, the second working clock is recorded as t1, and the clock difference can be expressed as |h1-t1|.
Frequency error (ppm: units per million), when indicative of frequency offset, frequency deviation, indicates the allowable deviation value at a particular center frequency, where frequency is in Hz. In the embodiment, the frequency offset of the clock circuit (comprising the system clock circuit and the digital-to-analog converter clock circuit) is adjusted so as to achieve the effect of adjusting the working clock of the slave device, and the frequency offset is adjusted until the first working clock and the second working clock are synchronous.
In one possible implementation, the system clock circuit includes a multi-stage first phase-locked loop controller, the system clock circuit is configured to provide a clock signal to a system of the slave device, the system clock circuit includes a multi-stage first phase-locked loop controller, the digital-to-analog converter clock circuit includes a multi-stage second phase-locked loop controller, and the step of adjusting a frequency offset of the system clock circuit and the digital-to-analog converter clock circuit includes:
step S301, adjusting the frequency offset of the first phase-locked loop controller, and adjusting the frequency offset of the second phase-locked loop controller.
Considering that the system clock and the ADC clock are obtained by frequency multiplication or frequency division of an external crystal oscillator through a multi-stage Phase-locked loop (PLL) controller, that is, the system clock and the digital-to-analog converter clock are directly in a proportional relationship, when the frequency offset of the system clock circuit is adjusted, the digital-to-analog converter clock is also adjusted according to the same frequency offset, so that the digital-to-analog converter clock can be synchronized to the system time clock, and the system clock is synchronized to the USB micro-frame clock, thereby realizing that the digital-to-analog converter clock is synchronized to the USB micro-frame clock, so that the reading rate of the data frame of the master device is synchronized with the sampling rate of the digital-to-analog converter of the slave device, the frequency offset of the system clock circuit is adjusted, so that the USB micro-frame clock (i.e., the first working clock, the audio clock of the master device) is synchronized with the system clock circuit, and the frequency offset of the digital-to-analog converter clock of the slave device is adjusted in the same manner, thereby realizing that the digital-to-analog converter clock of the master device (the audio clock of the slave device) is synchronized, and the audio frequency offset of the slave device is synchronized, and the frequency offset of the audio clock of the slave device is not required to be increased, and the frequency spectrum quality is not affected.
According to the method, a master device is started to read a preset number of micro data frames, the total micro frame duration of the micro data frames read by the master device is determined, and a first working clock of the master device is determined based on the total micro frame duration; after detecting that the master device finishes reading the micro data frame, acquiring the current system time of the slave device, and taking the current system time as a second working clock of the slave device; and adjusting the frequency offset of a system clock circuit and a digital-to-analog converter clock circuit of the slave device according to the clock difference between the first working clock and the second working clock, so that the master device and the slave device are synchronous in audio frequency clock. Thus, compared with the mode of setting the buffer area by the slave device in the prior art, the embodiment quantitatively determines the working clocks of the master device and the slave device, compares the clock differences between the working clocks to determine whether the clocks of the master device and the slave device are synchronous, and when the clocks of the slave device and the slave device are not synchronous, based on the frequency offset (ppm, parts per million), the allowable offset value under a specific center frequency is indicated to be offset of a clock every 1million clock, if the frequency offset is increased, the clock is increased, otherwise, the clock is increased, the clock is decreased, and the frequency offset of a clock circuit of the slave device system and the clock circuit of the digital-analog converter is adjusted, so that the clock of the slave device is adjusted until the clocks of the slave device and the slave device are synchronous. Therefore, the working clocks of the master device and the slave device are determined through quantization, so that the master device and the slave device are synchronized through adjusting frequency offset, and the audio clock synchronization of the master device and the slave device is realized. Further embodiments synchronize the audio clock prior to digital-to-analog conversion of the audio signal, rather than altering the data by software or signal processing after digital-to-analog conversion, so that the frequency spectrum and sound quality of the audio data are not affected.
Further, in order to facilitate understanding of the technical concept or working principle of the present application, a specific embodiment is listed:
the audio clock synchronization flow in this embodiment is:
step 1: the USB protocol specifies full-speed and low-speed device SOF time-frame times of 1 millisecond, and high-speed device SOF time-micro frame times of 125 microseconds, with high-speed devices being exemplified below. As shown in fig. 3, the PC (Personal Computer ) end (host Device end) and the peripheral end transmit data in 125uS as a unit through USB, the specific PC end transmits data in 125uS as a unit through USB host interface (USB host interface) the USB Device interface (USB Device interface) of the peripheral end, the USB PHY physical layer micro-frame counter counts the number of micro-frames transmitted, the system time read when the peripheral end program is started is t0, the time read when the host end is started is h0, the read USB PHY physical layer micro-frame counter register is f0, after 1 second, the read system time is t1, the micro-frame is f1, and the time of the PC end based on the USB micro-frame is: h1 The time of the device side is d1=t1, and by comparing h1 with t1, the clock rate of the host side based on the USB micro-frame and the rate of the device side system time can be compared, and the system clock rate can be adjusted, so that the USB micro-frame clock rate can be synchronized to the system clock rate.
Step 2: as shown in fig. 4, in the external system, the system clock and the ADC clock are obtained by multiplying or dividing the frequency of the external crystal oscillator by the multi-stage PLL, that is, the system clock and the ADC clock are directly in a proportional relationship, when the system clock is adjusted by PPM in step 1, and the ADC clock is adjusted by the same PPM, the ADC clock rate can be synchronized to the system clock rate, and the system clock rate is synchronized to the USB micro-frame clock rate in step 1, so that the ADC clock rate is synchronized to the UAC clock rate, and the master device and the slave device are synchronized in audio clock.
It should be noted that the above specific embodiments are only for understanding the present application, and do not limit the audio clock synchronization process of the present application, and more forms of simple transformation based on the technical concept are all within the protection scope of the present application.
Further, based on the first embodiment of the present application, a second embodiment of the audio clock synchronization method of the present application is provided, and the same or similar content as that of the first embodiment may be referred to the description above, and will not be repeated. In this embodiment, the step of adjusting the frequency offset between the system clock circuit and the digital-to-analog converter clock circuit according to the clock difference between the first working clock and the second working clock includes:
step A10, determining a clock difference between the first working clock and the second working clock;
and step A20, if the clock difference is larger than a preset threshold value, adjusting the frequency offset of the system clock circuit and the digital-to-analog converter clock circuit, and returning to execute the step of starting the main equipment to read the micro data frame until the clock difference between the first working clock and the second working clock is smaller than or equal to the preset threshold value.
In this embodiment, after the frequency offset is adjusted, the first working clock of the master device and the working clock of the slave device are redetermined, so as to redetermine the clock difference between the first working clock and the working clock of the slave device, thereby adjusting the frequency offset between the system clock circuit and the digital-to-analog converter clock circuit until the clock difference between the first working clock and the second working clock is smaller than a preset threshold, and the preset threshold can be zero, so that the synchronization of the audio clocks of the master device and the slave device is ensured.
In one possible implementation, the step of adjusting the frequency offset of the system clock circuit and the digital-to-analog converter clock circuit includes:
step B10, if the two working clocks are larger than the first working clock, reducing the frequency offset of the system clock circuit and the frequency offset of the digital-to-analog converter clock circuit;
and step B20, if the second working clock is smaller than the first working clock, increasing the frequency offset of the system clock circuit and the frequency offset of the digital-to-analog converter clock circuit.
The frequency offset of the system clock circuit and the frequency offset of the digital-to-analog converter clock circuit are adjusted, specifically, the frequency offset of the phase-locked loop controller in the clock circuit can be adjusted, the phase-locked loop controller included in the slave system clock circuit is recorded as a first phase-locked loop controller, and the phase-locked loop controller included in the slave digital-to-analog converter clock circuit is recorded as a second phase-locked loop controller. The frequency offset adjustment mode of the first phase-locked loop controller is the same as the frequency offset mode and adjustment value of the second phase-locked loop controller.
The second working clock is larger than the first working clock, so that the second working clock can be determined to be more than the first working clock, and the frequency offset of the phase-locked loop controller is reduced at the moment, so that the second working clock can be reduced, and the second working clock is reduced, so that the second working clock approaches to the first working clock. Similarly, if the second working clock is smaller than the first working clock, it can be determined that the second working clock is smaller than the first working clock, and at this time, the frequency offset of the phase-locked loop controller is increased, and the second working clock can be increased, so that the second working clock is increased, and the second working clock approaches to the first working clock. Thereby, the validity of the second operating clock adjustment is ensured.
In one possible implementation manner, the step of adjusting the frequency offset between the system clock circuit and the digital-to-analog converter clock circuit further includes:
step C10, detecting whether the system clock circuit and the digital-to-analog converter clock circuit are subjected to first frequency offset adjustment;
and step C20, if yes, inputting the first working clock and the second working clock into a preset frequency offset calculation model, outputting to obtain a target frequency offset, setting the frequency offset of the system clock circuit as the target frequency offset, and setting the frequency offset of the digital-to-analog converter clock circuit as the target frequency offset.
The preset frequency offset calculation model may be ppm= -1000000 x (d 1-d 0)/(t 1-t 0), where d1=t1-h 1, d0=t0-h 0, t0 is a system time read from when the device side program is started, h0 is a system time read from the device side while the device side program is started, h1 is a first working clock, h1=t0+f is m, and t1 is a second working clock. When the frequency offset of the system clock circuit and the digital-to-analog converter clock circuit is adjusted for the first time, specifically, when the frequency offset of the first phase-locked loop controller and the second phase-locked loop controller is adjusted for the first time, the frequency offset of the first phase-locked loop controller and the second phase-locked loop controller is set as the target frequency offset.
In one possible implementation manner, after the step of detecting whether the system clock circuit and the digital-to-analog converter clock circuit are the first frequency offset adjustment, the method further includes:
step D10, if not, obtaining a first current frequency offset of the system clock circuit and obtaining a second current frequency offset of the digital-to-analog converter clock circuit;
step D20, adjusting the first current frequency offset based on a preset algorithm to obtain a target frequency offset, wherein the preset algorithm comprises a proportional-integral-derivative algorithm;
and step D30, adjusting the first current frequency offset of the system clock circuit to the target frequency offset, and adjusting the second current frequency offset of the digital-to-analog converter clock circuit to the target frequency offset.
The proportional-integral-derivative algorithm (Proportion Intergration Differentiation, PID) specifically may take a clock difference between a first working clock and a second working clock as an input, the first current frequency offset is the same as the second current frequency offset, the current frequency offset is adjusted based on a feedback mechanism of the PID algorithm to obtain a target frequency offset, and the current frequency offset (including the first current frequency offset and the second current frequency offset) of the phase-locked loop controller (including the first phase-locked loop controller and the second phase-locked loop controller) is adjusted to be the target frequency offset.
In this embodiment, the target frequency offset can be calculated based on the preset frequency offset calculation model and the preset algorithm, so that the frequency offset of the phase-locked loop controller is directly adjusted to the target frequency offset, the frequency offset adjustment times are reduced, the adjustment efficiency is improved, and the synchronization efficiency of audio clock synchronization is improved.
It should be noted that, if the device between the master device and the slave device is a low-speed device, the first working clock and the second working clock may be determined based on the data frame, and the determination manner is similar to that based on the micro data frame, which is not described in detail in this embodiment, and may be considered as a micro frame or a frame, and the frame type of the micro data frame in this embodiment is specifically limited.
In addition, the application further provides an audio clock synchronization system, referring to fig. 5, where the audio synchronization system includes a master device and a slave device, the slave device includes a system clock circuit and a digital-to-analog converter clock circuit, and the audio clock synchronization system further includes:
a first determining module 10, configured to start the master device to read a micro data frame, determine a total micro frame duration of the master device to read the micro data frame, and determine a first working clock of the master device based on the total micro frame duration;
the second determining module 20 is configured to obtain a current system time of the slave device after detecting that the master device finishes reading the micro data frame, and take the current system time as a second working clock of the slave device;
and the synchronization module 30 is configured to adjust a frequency offset between the system clock circuit and the digital-to-analog converter clock circuit according to determining a clock difference between the first working clock and the second working clock, so that the master device and the slave device are in audio clock synchronization.
In addition, the embodiment of the application also provides audio clock synchronization equipment, which comprises a memory, a processor and an audio clock synchronization program stored in the memory and executable on the processor, wherein the audio clock synchronization program realizes the steps of the audio clock synchronization method when being executed by the processor.
The specific implementation manner of the audio clock synchronization device is basically the same as the above embodiments of the audio clock synchronization method, and will not be repeated here.
In addition, in order to achieve the above object, the present application further provides a readable storage medium, on which an audio clock synchronization program is stored, which when executed by a processor, implements the steps of the audio clock synchronization method as described above.
The specific implementation manner of the readable storage medium is basically the same as the above embodiments of the audio clock synchronization method, and will not be repeated here.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or system that comprises the element.
The foregoing embodiment numbers of the present application are merely for describing, and do not represent advantages or disadvantages of the embodiments.
From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) as described above, including several instructions for causing a terminal device (which may be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to perform the method described in the embodiments of the present application.
The foregoing description is only of the preferred embodiments of the present application, and is not intended to limit the scope of the claims, and all equivalent structures or equivalent processes using the descriptions and drawings of the present application, or direct or indirect application in other related technical fields are included in the scope of the claims of the present application.
Claims (7)
1. An audio clock synchronization method, wherein the audio clock synchronization method is applied to an audio synchronization system, the audio synchronization system comprises a master device and a slave device, the slave device comprises a system clock circuit and a digital-to-analog converter clock circuit, and the audio clock synchronization method comprises the following steps:
starting the main equipment to read micro data frames, acquiring single micro frame duration of the main equipment, and determining the micro frame number of the micro data frames read by the main equipment in preset duration;
multiplying the micro frame number by the single micro frame time length to obtain the total micro frame time length of the micro data frame read by the main equipment;
determining a start time of the master device for starting to read a micro data frame, determining a micro frame time based on the total micro frame time and the start time, and taking the micro frame time as a first working clock of the master device, wherein the time between the micro frame time and the start time is the total micro frame time, and the start time is the system time read when the slave device is started;
after detecting that the master device finishes reading the micro data frame, acquiring the current system time of the slave device, and taking the current system time as a second working clock of the slave device;
according to the clock difference between the first working clock and the second working clock, adjusting the frequency offset of the system clock circuit and the digital-to-analog converter clock circuit so that the master device and the slave device are synchronous in audio frequency clock;
wherein the step of adjusting the frequency offset between the system clock circuit and the digital-to-analog converter clock circuit includes:
detecting whether the system clock circuit and the digital-to-analog converter clock circuit are subjected to first frequency offset adjustment or not;
if yes, inputting the first working clock and the second working clock into a preset frequency offset calculation model, outputting to obtain a target frequency offset, setting the frequency offset of the system clock circuit as the target frequency offset, and setting the frequency offset of the digital-to-analog converter clock circuit as the target frequency offset;
the preset frequency offset calculation model comprises the following steps: ppm= -1000000 = (d 1-d 0)/(t 1-t 0), where d1=t1-h 1, d0=t0-h 0, where t0 is the system time read from when the device side program starts, h0 is the system time read from the device side while the device side program starts, h1 is the first working clock, t1 is the second working clock, and ppm is the target frequency offset.
2. The audio clock synchronization method of claim 1, wherein the step of adjusting the frequency offset of the system clock circuit and the digital-to-analog converter clock circuit based on determining the clock difference between the first operating clock and the second operating clock comprises:
determining a clock difference between the first operating clock and the second operating clock;
and if the clock difference is greater than a preset threshold, adjusting the frequency offset of the system clock circuit and the digital-to-analog converter clock circuit, and returning to execute the step of starting the main equipment to read the micro data frame until the clock difference between the first working clock and the second working clock is less than or equal to the preset threshold.
3. The audio clock synchronization method of claim 2, wherein the step of adjusting the frequency offset of the system clock circuit and the digital-to-analog converter clock circuit further comprises:
if the two working clocks are larger than the first working clock, reducing the frequency offset of the system clock circuit and the frequency offset of the digital-to-analog converter clock circuit;
and if the second working clock is smaller than the first working clock, increasing the frequency offset of the system clock circuit and the frequency offset of the digital-to-analog converter clock circuit.
4. The audio clock synchronization method of claim 1, wherein after the step of detecting whether the system clock circuit and the digital-to-analog converter clock circuit are first frequency offset adjusted, the method further comprises:
if not, acquiring a first current frequency offset of the system clock circuit and acquiring a second current frequency offset of the digital-to-analog converter clock circuit;
adjusting the first current frequency offset based on a preset algorithm to obtain a target frequency offset, wherein the preset algorithm comprises a proportional-integral-derivative algorithm;
and adjusting the first current frequency offset of the system clock circuit to the target frequency offset, and adjusting the second current frequency offset of the digital-to-analog converter clock circuit to the target frequency offset.
5. An audio clock synchronization system, comprising a master device and a slave device, the slave device comprising a system clock circuit and a digital-to-analog converter clock circuit, the audio clock synchronization system further comprising:
the first determining module is used for starting the main equipment to read the micro data frames, acquiring single micro frame duration of the main equipment, and determining the micro frame number of the micro data frames read by the main equipment in preset duration;
multiplying the micro frame number by the single micro frame time length to obtain the total micro frame time length of the micro data frame read by the main equipment;
determining a start time of the master device for starting to read a micro data frame, determining a micro frame time based on the total micro frame time and the start time, and taking the micro frame time as a first working clock of the master device, wherein the time between the micro frame time and the start time is the total micro frame time, and the start time is the system time read when the slave device is started;
the second determining module is used for acquiring the current system time of the slave device after detecting that the master device finishes reading the micro data frame, and taking the current system time as a second working clock of the slave device;
the synchronization module is used for adjusting the frequency offset of the system clock circuit and the digital-to-analog converter clock circuit according to the clock difference between the first working clock and the second working clock so as to synchronize the audio clocks of the master device and the slave device;
the synchronization module is further configured to:
detecting whether the system clock circuit and the digital-to-analog converter clock circuit are subjected to first frequency offset adjustment or not;
if yes, inputting the first working clock and the second working clock into a preset frequency offset calculation model, outputting to obtain a target frequency offset, setting the frequency offset of the system clock circuit as the target frequency offset, and setting the frequency offset of the digital-to-analog converter clock circuit as the target frequency offset;
the preset frequency offset calculation model comprises the following steps: ppm= -1000000 = (d 1-d 0)/(t 1-t 0), where d1=t1-h 1, d0=t0-h 0, where t0 is the system time read from when the device side program starts, h0 is the system time read from the device side while the device side program starts, h1 is the first working clock, t1 is the second working clock, and ppm is the target frequency offset.
6. An audio clock synchronization device, characterized in that the audio clock synchronization device comprises: memory, a processor and an audio clock synchronization program stored on the memory and executable on the processor, which when executed by the processor, implements the steps of the audio clock synchronization method of any one of claims 1 to 4.
7. A readable storage medium, characterized in that the readable storage medium has stored thereon an audio clock synchronization program, which when executed by a processor, implements the steps of the audio clock synchronization method according to any one of claims 1 to 4.
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| CN115437988A (en) * | 2021-06-04 | 2022-12-06 | 北京师旷科技有限公司 | Synchronization method, device and application of I2S audio clock data |
| CN115664577A (en) * | 2022-10-26 | 2023-01-31 | 苏州磐联集成电路科技股份有限公司 | Audio synchronization circuit and audio synchronization method |
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| CN103165169A (en) * | 2011-12-19 | 2013-06-19 | Gn奈康有限公司 | Method and system for synchronizing isochronous usb audio data to a RF communication device clock |
| CN111510235A (en) * | 2020-03-13 | 2020-08-07 | 浙江华创视讯科技有限公司 | Audio clock synchronization method, device, system, computer device and storage medium |
| CN115437988A (en) * | 2021-06-04 | 2022-12-06 | 北京师旷科技有限公司 | Synchronization method, device and application of I2S audio clock data |
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