JP2008005193A - Serial transmission system, transmitting device, and serial transmitting method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the number of transmission lines of a serial transmission system for a multichannel audio signal from increasing, even when the number of channels of the audio signal increases so as to prevent transmission from being interrupted before or after a change point, when the transmitted audio signal varies in the sampling frequency or changes in the number of channels. <P>SOLUTION: Data include the sampling frequency and the number of channels to be transmitted as properties of audio data, and a clock to be transmitted is changed, according to the sampling frequency and the number of channels to be transmitted. Consequently, the multichannel audio signal can be transmitted without increasing the number of signal lines, and transmission having no soundless period, before or after the sampling frequency is varied is realized. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a serial transmission system, and more particularly to a serial transmission system that transmits a digital audio signal via a serial transmission path.

  In recent years, digital audio technology has made great strides, and so-called multimedia devices such as DVD (Digital Versatile Disc) Video have become popular in general households. In the application, audio signals having more channels (hereinafter referred to as “multi-channel”) than conventional two-channel stereo sound are handled. As a result, the number of audio signal transmission lines has increased, increasing the number of LSI terminals and the number of wires on the board. For example, in the case of general serial transmission, two channels of audio are transmitted using a total of three signals: a transmission clock, an LR clock that identifies left and right channels of a two-channel stereo audio signal, and data. In order to transmit a 6-channel audio signal by this method, two data signals are added and a total of five wires are required.

  In addition, with the increase in the types of media such as DVD and CD (Compact Disc) and the spread of digital broadcasting, there are also a plurality of sampling frequencies of audio signals. This means that when the sampling frequency changes, This has caused a part of sound output to be silenced after a long silence period or a change in sampling frequency.

  48 kHz used in DVD Video and 44.1 kHz used in CD are both main sampling frequencies, and many of the existing audio signals adopt these two.

  Therefore, for example, after transmitting an audio signal with a sampling frequency of 48 kHz, it is necessary to transmit an audio signal with a sampling frequency of 44.1 kHz using the same transmission path.

  In this case, it is necessary to once terminate the transmission at the sampling frequency of 48 kHz, initialize the transmitting device, the receiving device, and the transmission path to change the setting to the sampling frequency of 44.1 kHz, and then start the transmission at the sampling frequency of 44.1 kHz. is there. Therefore, since the audio signal cannot be transmitted from the end of transmission to the start of the next transmission, there is no sound. In digital broadcasting, sampling frequencies of 48 kHz and 32 kHz are mainly used. For example, when an audio signal having a sampling frequency of 48 kHz is changed to a sampling frequency of 32 kHz, sampling is performed by initializing a transmitting device, a receiving device, and a transmission path. When an audio signal with a frequency of 32 kHz is transmitted, the beginning of the audio signal with a sampling frequency of 32 kHz takes time to initialize the transmission path, and therefore may not be able to output sound in time for the sound output time.

As a conventional technique, Japanese Patent Laying-Open No. 2004-147047 (Patent Document 1) discloses a serial transmission device that transmits a multi-channel audio signal.
An audio data transmission system disclosed in Patent Document 1 receives audio data of a plurality of channels, serially outputs the received audio data for each channel, and the audio processing chip transmitted from the audio processing chip And a processor for signal processing audio data. The audio processing chip includes a synchronization signal generation unit that generates the synchronization signal having a first logic level having a predetermined length according to a channel number of audio data to be transmitted to the processor. The processor includes a channel determination unit that measures a length of the synchronization signal output from the synchronization signal generation unit held at the first logic level and determines a channel number of the audio data. It is characterized by.

FIG. 1 is a timing diagram showing operations of a transmission apparatus, a serial transmission path, and a reception apparatus in the prior art.
CLK5-100 is an operation clock signal, SYNC5-101 is a signal indicating the synchronization timing indicating the data input / output time of DATA5-102 and the selected channel, and DATA5-102 is a data line. As shown in FIG. 1, the transmission apparatus reflects the channel number in the pulse width of SYNC 5-101 from the timing (a). That is, it is indicated that SYNC 5-101 at the time of channel 1 data transmission has a pulse width of 1 clock, and that of channel 4 has a pulse width of 4 clocks. The receiving apparatus recognizes the SYNC 5-101 and identifies the channel number, and then receives the DATA 5-102 from the timing (b).

  According to this configuration, it is possible to increase the number of data channels by increasing the pulse width options of the SYNC 5-101, and there is no need to increase the number of transmission lines from three of CLK5-100, SYNC5-101, and DATA5-102. The problem of increasing the number of wirings can be solved. However, there is no means for transmitting the sampling frequency, and only fixed-frequency audio data can be transmitted between the transmitting device and the receiving device. That is, it is impossible to eliminate the disadvantage that a silent period occurs in transmission of audio signals having different sampling frequencies and the synchronization relationship between the image and the sound is shifted.

JP 2004-147047 A

  Conventionally, there has been no serial transmission in which a sampling frequency, which is an important attribute of a digital audio signal, is transmitted simultaneously with a multi-channel audio signal. As a result, a phenomenon has occurred that is not in time for a long silence period or sound output time.

  In the following, means for solving the problem will be described using the numbers used in [Best Mode for Carrying Out the Invention] in parentheses. These numbers are added to clarify the correspondence between the description of [Claims] and [Best Mode for Carrying Out the Invention]. However, these numbers should not be used to interpret the technical scope of the invention described in [Claims].

A multi-channel digital audio signal (1-203) is generated based on the sampling frequency information (1-200), and the sampling frequency information (1-200) is serially transmitted together with the digital audio signal (1-203). A transmission signal generator (13) for
The sampling frequency information (1-200) and the digital audio signal (1-203) are serially received from the transmission signal generator (13), and based on the sampling frequency information (1-200), the transmission clock A serial transmission system comprising a transmission signal receiver (21) for detecting a change.

  In the serial transmission system of the present invention, the data includes the sampling frequency and the number of transmission channels, which are attributes of the audio data, and the transmission clock is changed according to the sampling frequency and the number of transmission channels. As a result, a multi-channel audio signal is transmitted without increasing the number of signal lines, and transmission without a silent period before and after the sampling frequency is changed is realized.

As a first effect, it becomes possible to transmit a multi-channel signal without increasing the number of transmission lines. The reason is to synthesize and transmit audio signals of a plurality of channels.
As a second effect, when the sampling frequency of the audio signal is switched, it is possible to transmit without interruption without generating a silent period. The reason is that, in the present invention, information on the sampling frequency that has not been transmitted conventionally is combined with the audio signal and transmitted, and the receiving apparatus outputs the sound by correctly applying the sampling frequency of the audio signal.

A first embodiment of the present invention will be described below with reference to the accompanying drawings.
FIG. 2 shows a block diagram of the present invention.
The digital audio signal serial transmission system of the present invention includes a transmission device 10 and a reception device 20.

The transmission device 10 includes a clock generator 11, a frequency divider 12, a transmission signal generator 13, a header information generator 14, and a code buffer 15.
The clock generator 11 generates a clock signal 1-104. The frequency divider 12 divides the clock signal 1-104 according to the sampling frequency information 1-200 and generates an audio clock 1-103. The frequency divider 12 changes the frequency division ratio in synchronization with the time when the LR clock 1-100 changes from the high level (H) to the low level (L). The transmission signal generator 13 acquires the audio data 1-203 from the code buffer 15, the header 1-202 from the header information generator 14, and the audio clock 1-103 from the frequency divider 12. 100, serial clock 1-101 and data 1-102 are generated. The header information generator 14 acquires the sampling frequency information 1-200, the channel information 1-201, and the status 1-204 from the code buffer 15, and generates a header 1-202. The code buffer 15 provides sampling frequency information 1-200, channel information 1-201, audio data 1-203, and status 1-204.

The receiving device 20 includes a transmission signal receiver 21, a header decoder 22, and a frequency divider 23.
The transmission signal receiver 21 acquires the LR clock 1-100, the serial clock 1-101, and the data 1-102, and generates audio data 1-301 and a header 1-302. The header decoder 22 acquires the header 1-302, and generates header information 1-303 and sampling frequency information 1-304. The frequency divider 23 acquires the LR clock 1-100, the serial clock 1-101, and the sampling frequency information 1-304, and generates a frequency-divided clock 1-305. Note that the internal circuit 24 of the receiving apparatus 20 illustrated in FIG. 2 acquires audio data 1-301, header information 1-303, and a divided clock 1-305.

FIG. 3 shows the transmission waveform of the present invention.
The data 1-102 is transmitted in synchronization with the LR clock 1-100 and the serial clock 1-101. The LR clock 1-100 changes between a low level (L) and a high level (H) in synchronization with the synchronization code, and the serial clock 1-101 changes to a low level (L) and a high level in synchronization with each bit of the audio data 1-102. The level (H) changes.

FIG. 4 is a timing chart showing the transmission method of the present invention.
In this embodiment, transmission of 8-channel audio data is used. At time 1, the audio data of channel 1 is transmitted among a part of the header 1-202 and the audio data 1-203. Here, the header includes a synchronization code, the number of channels, and a part of the status.

  At time 2, time 3, and time 4, audio data of channel 2, channel 3, and channel 4 are transmitted among the audio data 1-203, respectively.

  At time 5, the LR clock 1-100 changes from the low level (L) to the high level (H), and part of the header 1-202 and the audio data of the channel 5 among the audio data 1-203 are transmitted. . Here, the header includes a synchronization code, sampling frequency information, and a part of the status.

  At time 6, time 7, and time 8, audio data of channel 6, channel 7, and channel 8 are transmitted among the audio data 1-203, respectively.

  The header transmitted at time 1 and time 5 is incidental information corresponding to audio data transmitted during one cycle of the LR clock 1-100.

  Next, after time 9, data to be transmitted next to audio data transmitted from time 1 to time 8 is transmitted.

  At time 9, the LR clock 1-100 changes from the high level (H) to the low level (L), and part of the header 1-202 and the audio data of channel 1 out of the audio data 1-203 are transmitted. Here, the header includes a synchronization code, the number of channels, and a part of the status. When the number of channels transmitted at time 1 and the number of channels transmitted at time 9 are different, the header decoder 1-302 changes the number of channels to the frequency divider 23 and the internal circuit 24 at time 9, and the changed channel Transmit number.

  At time 10, time 11, and time 12, audio data of channel 2, channel 3, and channel 4 are transmitted among the audio data 1-203, respectively.

  At time 13, the LR clock 1-100 changes from the low level (L) to the high level (H), and part of the header 1-202 and the audio data of the channel 5 among the audio data 1-203 are transmitted. Here, the header includes a synchronization code, sampling frequency information, and a part of the status.

  When the sampling frequency information transmitted at time 5 and the sampling frequency information transmitted at time 13 are different, the header decoder 1-302 changes the sampling frequency to the fractional period 1-11 and the internal circuit 24 at time 13, and after the change. The sampling frequency information is transmitted.

Examples of the dynamic switching method of the sampling frequency and the number of channels will be described below.
FIG. 5 is a timing chart showing the transmission method of this embodiment. Hereinafter, a description will be given with reference to FIG.

  In this embodiment, 8-channel audio data with a sampling frequency of 48 kHz is transmitted, and then 2-channel audio data with a sampling frequency of 96 kHz is transmitted.

  In the present invention, information indicating the structure of audio data is transmitted together with the audio data as a header. The header consists of a 1-bit synchronization code, a 3-bit channel count, a 2-bit sampling frequency, and a 9-bit status. Table 1 shows the header factors, the number of bits corresponding to them, and the meanings of the values for each factor. The status is an area for adding other information attached to the audio data. In this embodiment, 9 bits of zero (000000000000) are transmitted.

  The header has a total of 16 bits, and 8 bits are transmitted at time 1 and time 5 respectively. The audio data is 24 bits, and at time 1 and time 5, a total of 32 bits are transmitted. At other times, only audio data is transmitted, so 24 bits are transmitted.

  In this embodiment, since the audio data with the sampling frequencies of 48 kHz and 96 kHz is transmitted, the clock frequency of the clock input to the clock generator 11 is fixed to 49.152 MHz. Table 2 shows the frequency division ratio in the clock generator 11 according to the sampling frequency and the number of channels. This frequency division ratio is designed corresponding to the maximum 32 bits transmitted at one time.

Next, the operation will be described.
The transmission device 10 transmits 8ch audio data with a sampling frequency of 48 kHz at a timing from time 1 to time 8.

  At this time, from Table 2, the frequency dividing ratio of the clock generator 11 is selected as 4, and the frequency of the serial clock 4-101 is 1/4 of 49.152 MHz, that is, 12.288 MHz.

Here, the interval of each time is 1/8 cycle of 48 kHz, so the number of bits of serial data transferred at each time is
12288/48/8 = 32
It can be seen that 32 bits are transferred at one time.

  In this embodiment, 32 bits are transmitted at time 1 and time 5 respectively, but only audio data is transmitted at other times, so 24 bits may be transmitted. The remaining 8 bits do not transmit anything. These 8 bits are generally filled with “0”. Here, in order to be able to cope with the case where attribute information such as a sampling frequency is simultaneously transmitted together with audio data, 32 bits can be transmitted.

  At this time, if the audio data can be divided, the 24-bit audio data is divided into three to generate three 8-bit divided data, and at other times (time 2, 3, 4), the audio data (24-bit) is respectively generated. ) + Divided data (8 bits) may be transmitted. Alternatively, three pieces of 8-bit divided data are created for each 24-bit audio data, and four pieces of divided data (8 bits) (8 bits × 4 = 32 bits) are transmitted at other times. .

  At other times, the clock frequency may be changed so that only 24 bits can be transmitted. That is, the clock frequency is switched within one sample time, and is changed to a frequency at which only 24 bits can be transmitted when only audio data is transmitted, and is changed to a frequency at which 32 bits can be transmitted when additional information is also transmitted.

  Thereafter, the transmitter 10 transmits 2-channel audio data having a sampling frequency of 96 kHz after time 9.

  Since the sampling frequency of the LR clock 4-100 changes, the frequency of the LR clock 4-100 changes from 48 kHz to 96 kHz at time 9 when the LR clock 4-100 changes from high level (H) to low level (L). To do.

  Since the sampling frequency and the number of channels change, the frequency dividing ratio of the frequency divider 1-2 changes from the 4 frequency division to the 8 frequency division at the timing of time 9.

  As a result, the serial clock 4-101 changes from 12.288 MHz to 6.144 MHz at the timing of time 9.

  When calculated in the same manner as described above, it is understood that 32 bits are transferred in a half cycle of 96 kHz in the 6.144 MHz serial clock.

  Also, the header transmitted at times 9 and 10 has a channel number of “001” and a sampling frequency of “11”.

  The receiving device 20 detects the number of channels and the sampling frequency, which are factors of the header transmitted at time 1 and time 5, as “111” and “00”, respectively, recognizes that the number of channels is 8 and the sampling frequency is 48 kHz.

  Accordingly, the audio data transmitted from the transmission device 10 between time 1 and time 8 is received as an audio signal with a sampling frequency of 48 kHz and 8 channels.

  After that, it is detected from the number of channels acquired at the timing of time 9 and the sampling frequency acquired at the timing of time 10 that the transmitted audio data has changed from 8 ch at the sampling frequency 48 kHz to 2 ch at the sampling frequency 96 kHz. Audio data transmitted after the timing is received as 2ch with a sampling frequency of 96 kHz. Before and after the time 9 when the sampling frequency and the number of channels are changed, it is not necessary to stop the transmitter, the receiver, and the transmission path, and audio data can be transmitted without interruption.

  As described above, in the present invention, audio data of a plurality of channels can be transmitted without increasing the number of transmission lines.

  Further, since transmission is not interrupted before and after the sampling frequency and the number of channels are changed, it is possible to eliminate conventional drawbacks in which a silent period occurs and the synchronization relationship between an image and sound is shifted.

The second embodiment of the present invention will be described below.
In the first embodiment of the present invention, the LR clock 1-100 changes from high level (H) to low level (L) at time 1 and changes from low level (L) to high level (H) at time 5. However, the second embodiment of the present invention may be a transmission method that changes from low level (L) to high level (H) at time 1 and changes from high level (H) to low level (L) at time 5.

  The serial clock 1-101 changes from high level (H) to low level (L) at the time synchronized with each bit of audio data, but the transmission method changes from low level (L) to high level (H). But it ’s okay.

  Note that examples of utilization of the present invention include an audio recording / playback apparatus such as a DVD recorder or a television capable of inputting a digital code.

  As described above, the digital audio signal serial transmission system of the present invention includes the serial interface circuit that transmits the data signal, the first clock signal, and the second clock signal. The data signal includes a digital audio signal sampled at a predetermined sampling frequency. The first clock signal changes between a low level (L) and a high level (H) in synchronization with the output time of each bit of the data signal. The second clock signal changes between a low level (L) and a high level (H) at the sampling frequency with the first clock signal.

  The digital audio signal serial transmission system includes a first frequency divider, a change point detector, a header information generator, and a transmission signal generator. The first frequency divider generates a first clock signal by dividing a master clock signal and a master clock generation circuit that generates a master clock signal having an integer multiple of the sampling frequency. The second frequency divider divides the master clock signal to generate a second clock signal. The change point detector detects a change point of the second clock signal and generates a first timing signal. The header information generator generates header information including at least the number of channels of the digital audio signal and the sampling frequency. The transmission signal generator generates a data signal by combining the header information and the digital audio signal according to the first timing signal, and sets the division ratios of the first and second dividers, respectively. .

FIG. 1 is a timing diagram showing operations of a transmission device, a serial transmission path, and a reception device used in the prior art. FIG. 2 is a block diagram of the present invention. FIG. 3 is a transmission waveform of the present invention. FIG. 4 is a timing diagram showing the transmission method of the present invention. FIG. 5 is a timing diagram showing a transmission method used in the embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Whole transmission circuit of transmission system 11 ... Clock generator on transmission side 12 ... Frequency divider on transmission side 13 ... Circuit for generating transmission signal on transmission side (transmission signal generator)
14 ... Circuit for generating header information to be transmitted (header information generator)
15 ... Buffer for storing audio data (code buffer)
20 ... Entire reception circuit of transmission system 21 ... Circuit for receiving transmission signal on transmission side (transmission signal generator)
22 ... A circuit for decoding the received header information and transmitting it to the subsequent stage (header decoder)
23. Circuit for dividing the received clock and transmitting it to the subsequent stage (frequency divider)
24. Subsequent circuit (internal circuit) that receives audio data from the receiver of the transmission system
1-100 ... LR clock to be transmitted 1-101 ... serial clock to be transmitted 1-102 ... data to be transmitted 1-103 ... LR clock to be fed back to the frequency divider 1-200 ... sampling frequency information of data to be transmitted 1-201 ... Channel number information of data to be transmitted 1-202 ... Header of data to be transmitted 1-203 ... Audio data of data to be transmitted 1-204 ... Status information of data to be transmitted 1-301 ... Received audio data 1-302 ... Reception 1-303 ... Received channel number information, sampling frequency information, status information 1-304 ... Received sampling frequency information and status information 1 -305 ... Signal obtained by dividing the received LR clock and serial clock 3-100 ... Channel with header Structure 3-101 ... Header structure 3-300 ... Header transmitted at time 1 3-301 ... Audio data transmitted at time 1 3-302 ... Header transmitted at time 5 3-303 ... Audio data transmitted at time 5 4 -100 ... LR clock transmitted in the embodiment 4-101 ... Serial clock transmitted in the embodiment 4-102 ... Data transmitted in the embodiment 4-103 ... Channel with header in data transmitted in the embodiment Structure 4-104 ... Header structure in data transmitted in the embodiment 4-105 ... Header value in data transmitted in the embodiment 5-100 ... Operation clock signal in the conventional example 1 5-101 ... In the conventional example 1 Timing indicating data input / output time and signal indicating selected channel 5-102. Data line in 1

Claims (15)

A transmission signal generator for generating a multi-channel digital audio signal based on sampling frequency information and serially transmitting the sampling frequency information together with the digital audio signal;
A serial transmission system comprising: a transmission signal receiver that serially receives the sampling frequency information and the digital audio signal from the transmission signal generator and detects a change in a transmission clock based on the sampling frequency information. The serial transmission system according to claim 1,
The transmission signal generator further serially transmits channel number information together with the digital audio signal,
The transmission signal receiver serially receives the information on the number of channels and the digital audio signal from the transmission signal generator, and detects a change in the transmission clock based on the information on the number of channels. The serial transmission system according to claim 2,
The transmission signal generator changes the transmission clock according to the sampling frequency information and the channel number information. In the serial transmission system according to any one of claims 1 to 3,
The transmission signal generator serially transmits the digital audio signal in synchronization with an LR clock signal whose low level (L) and high level (H) change based on the sampling frequency information. The serial transmission system according to any one of claims 1 to 4,
The transmission signal generator serially transmits the digital audio signal in synchronization with a serial clock signal whose low level (L) and high level (H) change in synchronization with the output time of each bit of the digital audio signal. Transmission system. A master clock generator for generating a master clock signal having a frequency that is an integer multiple of the sampling frequency;
A code buffer providing the sampling frequency information, channel information, and audio data;
A frequency divider that divides the master clock signal based on the sampling frequency information to generate an audio clock signal;
A header information generator that obtains the sampling frequency information and the channel information to generate a header;
A data signal including a digital audio signal sampled based on a sampling frequency by acquiring the audio data, the header, and the audio clock signal, and an LR that changes between a low level (L) and a high level (H) at the sampling frequency. A transmission apparatus comprising: a clock signal; and a transmission signal generator that generates a serial clock signal whose low level (L) and high level (H) change in synchronization with the output time of each bit of the data signal. The transmission apparatus according to claim 6, wherein
The frequency divider is configured to change a frequency division ratio in synchronization with a time when the LR clock signal changes from a high level (H) to a low level (L). The transmission device according to claim 6 or 7,
The frequency divider is configured to change a frequency division ratio in synchronization with a time when the serial clock signal changes from a high level (H) to a low level (L). The transmission apparatus according to any one of claims 6 to 8,
The transmission signal generator changes a transmission clock according to the sampling frequency information and the channel information. The transmission apparatus according to any one of claims 6 to 9,
The transmission signal generator transmits the data signal in synchronization with the LR clock signal and the serial clock signal,
The LR clock signal changes between a low level (L) and a high level (H) in synchronization with a synchronization code,
The serial clock signal changes between a low level (L) and a high level (H) in synchronization with each bit of the audio data signal. (A) A data signal including a digital audio signal sampled according to a sampling frequency, and a first clock signal whose low level (L) and high level (H) change in synchronization with the output time of each bit of the data signal Transmitting a second clock signal having a low level (L) and a high level (H) that change at the sampling frequency;
(B) generating a master clock signal having a frequency that is an integral multiple of the sampling frequency;
(C) dividing the master clock signal to generate the first clock signal;
(D) dividing the master clock signal to generate the second clock signal;
(E) detecting a change point of the second clock signal to generate a timing signal;
(F) generating first header information including the number of channels of the digital audio signal and the sampling frequency;
(G) According to the timing signal, the first header information and the digital audio signal are combined to generate the data signal, and the first clock signal and the second clock signal are generated. And a step of setting a division ratio of the master clock signal at the time. The serial transmission method according to claim 11,
The step (c) includes:
(C1) A serial transmission method comprising the step of changing the division ratio in synchronization with a time at which the first clock signal changes from a high level (H) to a low level (L). The serial transmission method according to claim 11 or 12,
The step (a) includes:
(A1) transmitting the data signal in synchronization with the first clock signal and the second clock signal;
(A2) the first clock signal has a step of changing a low level (L) and a high level (H) in synchronization with a synchronization code;
(A3) The second clock signal comprises a step of changing a low level (L) and a high level (H) in synchronization with each bit of the audio data signal. The serial transmission method according to any one of claims 11 to 13,
The step (g) includes:
(G1) A serial transmission method comprising a step of changing a transmission clock according to the number of channels and the sampling frequency. The serial transmission method according to any one of claims 11 to 14,
(H) receiving the data signal, the first clock signal, and the second clock signal from the first serial interface circuit;
(I) obtaining the data signal, the first clock signal, and the second clock signal, and generating audio data and incidental information corresponding to the audio data;
(J) obtaining the supplementary information and generating second header information and sampling frequency information;
(K) acquiring the first clock signal, the second clock signal, and the sampling frequency information, and generating a divided clock. A serial transmission method.

Images