CN103235254B - A kind of detection method of programmable logic device (PLD) and detection system - Google Patents
A kind of detection method of programmable logic device (PLD) and detection system Download PDFInfo
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Abstract
The embodiment of the invention discloses a kind of detection method and detection system of programmable logic device (PLD), the method comprises: described Programmable logic design receive clock signal, generates detect pulse signal and export according to predetermined pulse cycle generating mode; Master controller receives described detection pulse signal, resolves the actual pulse cycle obtaining described detection pulse signal; Whether the difference in actual pulse cycle described in comparison and described predetermined pulse cycle is in default error range; If so, then judge that described PLD is current to be properly configured; Otherwise, then judge that described PLD is current not to be properly configured, the logical value mechanical periodicity of level in the detection pulse signal that this testing process gathers, avoid transmission link when breaking down, obtain wrong testing result because parsing obtains the fixed level signal of mistake, improve the reliability of detection method.
Description
Technical field
The present invention relates to electronic product fault detection technique field, more particularly, relate to a kind of detection method and detection system of programmable logic device (PLD).
Background technology
Programmable logic device (PLD) (programmablelogicdevice is called for short PLD) is a kind of semicustom integrated circuit being realized required function by user program.Described PLD model, inner pin are distributed and the description of annexation, i.e. configuration data, can be stored in EPROM(Erasable Programmable Read Only Memory EPROM) or PROM(programmable read only memory) etc. storage unit.When described PLD and peripheral circuit remain unchanged, the storage unit for described PLD writes different configuration datas, can realize different logic functions.Compiled configuration data is write the process of described PLD, be called that PLD configures.
In actual applications, for ensureing the integrality of configuration data, namely described configuration data download and memory period countless according to the generation of the phenomenon such as omissions, damage, master controller needs to detect the configuration result of PLD under current operating state of its periphery, to ensure the control command that described PLD accurately can perform master controller and sends.Existing detection method is as follows:
In compiling configuration data process, introduce the data that can send fixed level signal, carry out PLD configuration in the lump with former configuration data; In the user mode, described PLD performs configuration data, is fixed level signal and exports, and described master controller collection also resolves the logical value of this fixed level signal, realizes detecting; If the logical value of resolving the fixed level signal obtained is identical with the logical value of the fixed level signal compiled during compiling configuration data, represents that this PLD is current and be properly configured; Otherwise then represent that this PLD is current not to be properly configured.
In above-mentioned detection method, described PLD and master controller carry out information transmission by transmission link.But, because described transmission link is the connecting link existed physically between described PLD and master controller, as a wire, with extraneous contact, there is the failure risk of broken string, misconnection power supply or short circuit over the ground, the logical value that the fixed level signal obtained resolved by described master controller can be fixed as high or low because of the failure condition of this transmission link, cause when knowing that described transmission link breaks down, the configuring condition current to described PLD makes erroneous judgement, and the reliability of this detection method is not high.
Summary of the invention
In view of this, the invention provides a kind of detection method and detection system of programmable logic device (PLD), when can know in real time described transmission link whether fault, detect whether described PLD is current is properly configured simultaneously, improve the reliability of detection method.
A detection method for programmable logic device (PLD), comprising:
Described Programmable logic design receive clock signal, generates according to predetermined pulse cycle generating mode and detects pulse signal and export;
Master controller receives described detection pulse signal, resolves the actual pulse cycle obtaining described detection pulse signal;
Whether the difference in actual pulse cycle described in comparison and described predetermined pulse cycle is in default error range; If so, then judge that described PLD is current to be properly configured; Otherwise, then judge that described PLD is current and be not properly configured.
Wherein, described PLD receive clock signal, generates according to predetermined pulse cycle generating mode and detects pulse signal, comprising:
Described PLD receives at least two clock signals;
Described PLD according to the first predetermined pulse cycle generating mode, respectively the quantity such as corresponding each clock signal generation, the pre-detection pulse signal with the same predetermined pulse cycle;
To above-mentioned pre-detection pulse signal time-sharing multiplex, generate one and detect pulse signal.
Wherein, described PLD receive clock signal, generates according to predetermined pulse cycle generating mode and detects pulse signal, comprising:
Described PLD receives a clock signal;
Described PLD according to the second predetermined pulse cycle generating mode, to clock signal generating a pre-detection pulse signal; This pre-detection pulse signal is described detection pulse signal.
Alternatively, before described PLD receive clock signal, also comprise:
Described PLD download configuration data, described configuration data comprises and has according to clock signal and predetermined pulse cycle generating mode, generates the data of the logic function of the pulse signal that a recurrence interval presets.
A detection system for programmable logic device (PLD), is characterized in that, comprising: Programmable logic design, master controller and transmission link;
Described PLD receive clock signal, generates according to predetermined pulse cycle generating mode and detects pulse signal and export;
Described master controller receives described detection pulse signal, resolves the actual pulse cycle obtaining described detection pulse signal; Whether the difference in actual pulse cycle described in comparison and described predetermined pulse cycle is in default error range; If so, then judge that described PLD is current to be properly configured; Otherwise, then judge that described PLD is current and be not properly configured;
Described master controller is connected by transmission link with described PLD.
Wherein, described PLD comprises storing and has
According to the logic function of the pulse signal that the clock signal production burst cycle presets
The storage unit of configuration data.
Wherein, described storage unit has for storing
Receive at least two clock signals; According to same predetermined pulse cycle generating mode, respectively the quantity such as corresponding each clock signal generation, the pre-detection pulse signal with the same predetermined pulse cycle; To above-mentioned pre-detection pulse signal time-sharing multiplex, generate the logic function that is detected pulse signal
The first chip of configuration data.
Wherein, described storage unit has for storing
Receive a clock signal; According to predetermined pulse cycle generating mode, to clock signal generating the logic function of a pre-detection pulse signal
The second chip of configuration data, wherein this pre-detection pulse signal is detection pulse signal.
As can be seen from above-mentioned technical scheme, the embodiment of the present invention by described PLD receive clock signal, and sends detection pulse signal according to described clock signal according to the expection recurrence interval; Master controller receives the described detection pulse signal of this parsing, obtains its actual recurrence interval; Detect described PLD by the expection recurrence interval of this detection pulse signal of comparison and the difference in actual pulse cycle whether to be properly configured: if this difference is in error allowed band, then judge that described PLD is properly configured; Otherwise be not then properly configured, compared to prior art, the logical value mechanical periodicity of level in the detection pulse signal that the application's testing process gathers, avoid transmission link when breaking down, obtain wrong testing result because parsing obtains the fixed level signal of mistake, improve the reliability of detection method.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
The detection method process flow diagram of Fig. 1 a-1c a kind of programmable logic device (PLD) disclosed in the embodiment of the present invention;
The detection system structural representation of Fig. 2 a-2c a kind of programmable logic device (PLD) disclosed in the embodiment of the present invention.
Embodiment
For the purpose of quoting and know, the technical term hereinafter used, write a Chinese character in simplified form or abridge and be summarized as follows:
PLD:programmablelogicdevice, programmable logic device (PLD);
EPROM:ErasableProgrammableReadOnlyMemory, Erasable Programmable Read Only Memory EPROM;
PROM:ProgrammableRead-OnlyMemory, programmable read only memory.
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
As illustrated by figures 1 a-1 c, the embodiment of the invention discloses a kind of detection method of programmable logic device (PLD), described transmission link whether fault can be known in real time, detect whether described PLD is current is properly configured simultaneously, improve the reliability of detection method, comprise (see Fig. 1 a):
Step 101: described PLD receive clock signal, generates according to predetermined pulse cycle generating mode and detects pulse signal and export;
Wherein, the clock signal that described PLD receives only refers to the clock signal participated in involved by this detection method, and do not comprise described PLD and do not participate in this detection method, only participate in other logic controls and the clock signal received, in addition, it should be noted that, the clock signal participated in involved by this detection method also can participate in other logic controls simultaneously, does not limit to.
The oscillatory circuit of described PLD periphery is as the transmitting terminal of clock signal, and for described PLD provides clock source, described PLD receives described clock signal, as the input signal of this detection method.
The clock period of the clock signal that the described oscillatory circuit received according to described PLD produces and time radix corresponding to described clock signal, can calculate with this clock signal for time recurrence interval of pulse signal of sending of base, specific formula for calculation is as follows:
Clock signal clock period × clock signal time radix=pulse signal recurrence interval.
Wherein, when described oscillatory circuit is constant, the clock period of its corresponding clock signal produced is changeless given value, the recurrence interval of each clock signal corresponding described pulse signal generated respectively is the preset value that described PLD defines, and can determine the time radix that each clock signal is corresponding respectively thus.
This preset value is the predetermined pulse cycle of the detection pulse signal generated according to predetermined pulse cycle generating mode, and wherein said preset value can set arbitrarily, does not limit to.Described predetermined pulse cycle generating mode specific implementation process is as follows:
Described PLD receives the clock signal that its peripheral oscillatory circuit produces, with described clock signal for time base, according to the time radix that fixed each clock signal is corresponding respectively, generate the pulse signal with the predetermined pulse cycle corresponding with it, according to the number of described clock signal, step 101 can be refined as scheme one and scheme two respectively, to obtain described detection pulse signal according to described pulse signal.
Scheme one (see Fig. 1 b):
Step 11: described PLD receives at least two clock signals;
Described at least two clock signals are sent by the different peripheral oscillatory circuit of described PLD respectively.
Step 12: described PLD according to the first predetermined pulse cycle generating mode, respectively the quantity such as corresponding each clock signal generation, the pre-detection pulse signal with the same predetermined pulse cycle;
Described pre-detection pulse signal is the pulse signal described in above-mentioned formula;
According to described oscillatory circuit crystal oscillator frequency separately, pre-determine the time radix of the clock signal that each oscillatory circuit correspondence sends, consistent with the preset value of the recurrence interval ensureing the corresponding pre-detection pulse signal produced of each clock signal difference, namely the described predetermined pulse cycle is consistent; The inverse of the crystal oscillator frequency of described peripheral oscillatory circuit is the clock period of the clock signal that it sends;
If: predetermined pulse cycle as described in setting is as 1000us, described clock signal is respectively the first clock signal and second clock signal, if the clock period of described first clock signal is 1us, so known by aforementioned computing formula, the time radix of described first clock signal should be defined as 1000us/1us=1000; If the clock period of described second clock signal is 2us, the time radix of so described second clock signal should be defined as 1000us/2us=500; Correspondence obtains the pre-detection pulse signal that the predetermined pulse cycle is 1000us respectively thus.
Step 13: to above-mentioned pre-detection pulse signal time-sharing multiplex, generates one and detects pulse signal.
To each clock signal respectively corresponding at least two the pre-detection pulse signals described in the unified predetermined pulse cycle that have generated carry out time-sharing multiplex, obtain a new pulse signal, i.e. described detection pulse signal; Because the predetermined pulse cycle of described pre-detection pulse signal is consistent, then the predetermined pulse cycle of carrying out the detection pulse signal of time-sharing multiplex generation to it equals predetermined pulse cycle of described pre-detection pulse signal.
Scheme two (see Fig. 1 c):
Step 21: described PLD receives a clock signal;
Step 22: described PLD according to the second predetermined pulse cycle generating mode, to clock signal generating a pre-detection pulse signal; This pre-detection pulse signal is detection pulse signal.
Described pre-detection pulse signal is the pulse signal described in above-mentioned formula;
Described PLD, according to the crystal oscillator frequency of the peripheral oscillatory circuit of this clock signal of generation, pre-determines the time radix that this clock signal is corresponding, to ensure that the recurrence interval of the pre-detection pulse signal that this clock signal correspondence generates is for preset value; Namely described detection pulse signal has the predetermined pulse cycle.
Step 102: master controller receives described detection pulse signal, resolves the actual pulse cycle obtaining described detection pulse signal;
Step 103: whether the difference in actual pulse cycle described in comparison and described predetermined pulse cycle is in default error range; If so, then judge that described PLD is current to be properly configured; Otherwise, then judge that described PLD is current and be not properly configured.
The described detection pulse signal generated in step 101 has the known predetermined pulse cycle, but not to be properly configured or because of clock drift effect described PLD is current, the actual pulse cycle of described detection pulse signal then there will be mistake or deviation, and its actual value also needs described master controller to be known by parsing.
Be properly configured if described PLD is current, the actual pulse cycle of then resolving the described clock signal that the obtains corresponding pre-detection pulse signal produced respectively is consistent and equal predetermined pulse cycle of its correspondence, so in scheme one, to the detection pulse signal that described pre-detection pulse signal time-sharing multiplex produces, its actual recurrence interval just should equal its predetermined pulse cycle; Same in scheme two, the pre-detection pulse signal that single clock signal produces is described detection pulse signal, and the actual pulse cycle of this detection pulse signal also should equal its predetermined pulse cycle.
Consider that the clock signal that peripheral oscillatory circuit produces may produce certain error under clock drift effect, thus there is certain error between the predetermined pulse cycle of the pre-detection pulse signal causing each clock signal correspondence to produce and its actual recurrence interval, also just error may be there is in predetermined pulse cycle and its actual recurrence interval of the so corresponding detection pulse signal obtained, as long as but both differences are in default error range, then think that described PLD is properly configured; Otherwise, then think that described PLD is not properly configured; Described default error range is the deviation range of the recurrence interval after considering clock drift.
Secondly, whether the oscillatory circuit that the embodiment of the present invention also can be used for detecting described PLD periphery exists exception:
When the predetermined pulse cycle of described detection pulse signal and the difference in actual pulse cycle are in default error range, illustrate that the clock signal that the oscillatory circuit of described PLD periphery provides for described PLD is errorless, can ensure that described PLD realizes the logic function of expection, the oscillatory circuit of described PLD periphery is in normal operating condition.
As preferably, before described PLD receive clock signal, also comprise:
Described PLD download configuration data, described configuration data comprises and has according to clock signal and predetermined pulse cycle generating mode, generates the data of the logic function of the pulse signal that a recurrence interval presets.
Described PLD performs described configuration data, realizes above-mentioned Detection task.
The process of described PLD download configuration data performs under described PLD configuration mode, treats that described configuration data is downloaded and terminates, then identify described PLD device and developed; The described process realizing above-mentioned Detection task performs under described PLD user model.
As shown in figs. 2 a-2 c, the embodiment of the invention also discloses a kind of detection system of programmable logic device (PLD), described transmission link whether fault can be known in real time, detect whether described PLD is current is properly configured simultaneously, improve the reliability of detection method, comprise (see Fig. 2 a):
Programmable logic design 100, master controller 200 and transmission link 300;
Described PLD100 receive clock signal, generates according to predetermined pulse cycle generating mode and detects pulse signal and export;
Described master controller 200 receives described detection pulse signal, resolves the actual pulse cycle obtaining described detection pulse signal; And whether the difference in actual pulse cycle described in comparison and described predetermined pulse cycle is in default error range; If so, then judge that described PLD100 is current to be properly configured; Otherwise, then judge that described PLD100 is current and be not properly configured;
Described master controller 200 is connected by transmission link 300 with described PLD100; Described transmission link 300 is the connecting links existed physically between described PLD100 and master controller 200, as a wire.
Wherein, described PLD100 comprises storing and has
According to the logic function of the pulse signal that the clock signal production burst cycle presets
The storage unit 10 of configuration data.
Namely described storage unit 10 stores the configuration data of the pulse signal that the described PLD100 of instruction preset according to the clock signal production burst cycle.
Wherein, described storage unit 10 can have for storing
Receive at least two clock signals; According to same predetermined pulse cycle generating mode, respectively the quantity such as corresponding each clock signal generation, the pre-detection pulse signal with the same predetermined pulse cycle; To above-mentioned pre-detection pulse signal time-sharing multiplex, generate the logic function that is detected pulse signal
The first chip 11(of configuration data see Fig. 2 b).
Wherein, can also have for storing see described storage unit 10
Receive a clock signal; According to predetermined pulse cycle generating mode, to clock signal generating the logic function of a pre-detection pulse signal
The second chip 12(of configuration data see Fig. 2 c), wherein this pre-detection pulse signal is detection pulse signal.
Described storage unit 10 can be the storage chips such as EPROM or PROM, does not limit to.
In sum, the embodiment of the present invention by described PLD receive clock signal, and sends detection pulse signal according to described clock signal according to the expection recurrence interval; Master controller receives the described detection pulse signal of this parsing, obtains its actual recurrence interval; Detect described PLD by the expection recurrence interval of this detection pulse signal of comparison and the difference in actual pulse cycle whether to be properly configured: if this difference is in error allowed band, then judge that described PLD is properly configured; Otherwise be not then properly configured, compared to prior art, the logical value mechanical periodicity of level in the detection pulse signal that the application's testing process gathers, avoid transmission link when breaking down, obtain wrong testing result because parsing obtains the fixed level signal of mistake, improve the reliability of detection method.
For system embodiment, because it is substantially corresponding to embodiment of the method, so describe fairly simple, relevant part illustrates see the part of embodiment of the method.Those of ordinary skill in the art, when not paying creative work, are namely appreciated that and implement.
To the above-mentioned explanation of the disclosed embodiments, professional and technical personnel in the field are realized or uses the present invention.To be apparent for those skilled in the art to the multiple amendment of these embodiments, General Principle as defined herein when not departing from the spirit or scope of the embodiment of the present invention, can realize in other embodiments.Therefore, the embodiment of the present invention can not be restricted to these embodiments shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (6)
1. a detection method for programmable logic device (PLD), is characterized in that, comprising:
Described Programmable logic design receive clock signal, generates according to predetermined pulse cycle generating mode and detects pulse signal and export;
Master controller receives described detection pulse signal, resolves the actual pulse cycle obtaining described detection pulse signal;
Whether the difference in actual pulse cycle described in comparison and described predetermined pulse cycle is in default error range; If so, then judge that described PLD is current to be properly configured; Otherwise, then judge that described PLD is current and be not properly configured;
Described PLD receive clock signal, generates according to predetermined pulse cycle generating mode and detects pulse signal, comprising:
Described PLD receives at least two clock signals;
Described PLD according to the first predetermined pulse cycle generating mode, respectively the quantity such as corresponding each clock signal generation, the pre-detection pulse signal with the same predetermined pulse cycle;
To above-mentioned pre-detection pulse signal time-sharing multiplex, generate one and detect pulse signal;
Or described PLD receive clock signal, generates according to predetermined pulse cycle generating mode and detects pulse signal, comprising:
Described PLD receives a clock signal;
Described PLD according to the second predetermined pulse cycle generating mode, to clock signal generating a pre-detection pulse signal; This pre-detection pulse signal is described detection pulse signal;
Wherein, described default error is that the described clock signal that peripheral oscillatory circuit produces produces error under clock drift effect, there is error between the described predetermined pulse cycle of the pre-detection pulse signal causing described clock signal correspondence to produce and its actual recurrence interval, thus cause the predetermined pulse cycle of described detection pulse signal and its actual recurrence interval also just to there is error.
2. detection method according to claim 1, is characterized in that, before described PLD receive clock signal, also comprises:
Described PLD download configuration data, described configuration data comprises and has according to clock signal and predetermined pulse cycle generating mode, generates the data of the logic function of the pulse signal that a recurrence interval presets.
3. a detection system for programmable logic device (PLD), is characterized in that, comprising: Programmable logic design, master controller and transmission link;
Described PLD receive clock signal, generates according to predetermined pulse cycle generating mode and detects pulse signal and export;
Described master controller receives described detection pulse signal, resolves the actual pulse cycle obtaining described detection pulse signal; Whether the difference in actual pulse cycle described in comparison and described predetermined pulse cycle is in default error range; If so, then judge that described PLD is current to be properly configured; Otherwise, then judge that described PLD is current and be not properly configured;
Described master controller is connected by transmission link with described PLD;
Described PLD receive clock signal, generates according to predetermined pulse cycle generating mode and detects pulse signal, comprising:
Described PLD receives at least two clock signals;
Described PLD according to the first predetermined pulse cycle generating mode, respectively the quantity such as corresponding each clock signal generation, the pre-detection pulse signal with the same predetermined pulse cycle;
To above-mentioned pre-detection pulse signal time-sharing multiplex, generate one and detect pulse signal;
Or described PLD receive clock signal, generates according to predetermined pulse cycle generating mode and detects pulse signal, comprising:
Described PLD receives a clock signal;
Described PLD according to the second predetermined pulse cycle generating mode, to clock signal generating a pre-detection pulse signal; This pre-detection pulse signal is described detection pulse signal;
Wherein, described default error is that the described clock signal that peripheral oscillatory circuit produces produces error under clock drift effect, there is error between the described predetermined pulse cycle of the pre-detection pulse signal causing described clock signal correspondence to produce and its actual recurrence interval, thus cause the predetermined pulse cycle of described detection pulse signal and its actual recurrence interval also just to there is error.
4. detection system according to claim 3, is characterized in that, described PLD comprises the storage unit of the configuration data storing the logic function with the pulse signal preset according to the clock signal production burst cycle.
5. detection system according to claim 4, is characterized in that, when described PLD receive clock signal, generates and detects pulse signal, comprising according to predetermined pulse cycle generating mode:
Described PLD receives at least two clock signals;
Described PLD according to the first predetermined pulse cycle generating mode, respectively the quantity such as corresponding each clock signal generation, the pre-detection pulse signal with the same predetermined pulse cycle;
To above-mentioned pre-detection pulse signal time-sharing multiplex, when generating a detection pulse signal:
Described storage unit has reception at least two clock signals for storing; According to same predetermined pulse cycle generating mode, respectively the quantity such as corresponding each clock signal generation, the pre-detection pulse signal with the same predetermined pulse cycle; To above-mentioned pre-detection pulse signal time-sharing multiplex, generate the first chip that is detected the configuration data of the logic function of pulse signal.
6. detection system according to claim 4, is characterized in that, when described PLD receive clock signal, generates and detects pulse signal, comprising according to predetermined pulse cycle generating mode:
Described PLD receives a clock signal;
Described PLD according to the second predetermined pulse cycle generating mode, to clock signal generating a pre-detection pulse signal; When this pre-detection pulse signal is described detection pulse signal:
Described storage unit has reception clock signal for storing; According to predetermined pulse cycle generating mode, to clock signal generating the second chip of the configuration data of the logic function of a pre-detection pulse signal, wherein this pre-detection pulse signal is detection pulse signal.
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