CN213365438U - Double-circuit server mainboard and server - Google Patents

Abstract

The utility model provides a double-circuit server mainboard and server, this server mainboard include a mainboard, set up first central processing unit and the second central processing unit on the mainboard, through 2X 16 XGMI interconnection of group between first central processing unit and the second central processing unit. And a mini SAS HD connector connected with the first central processing unit is further arranged on the main board and used for connecting an SATA disk or an NVME disk. The main board is also provided with a data selector, and the data selector is also connected with the mini SAS HD connector; the data selector is used for automatically identifying the SATA disk or the NVME disk plugged in the mini SAS HD connector and selecting the SATA disk or the NVME disk to be connected with the first central processing unit. The mainboard is also provided with a BMC chip connected with the first central processing unit, and the BMC chip is also connected with the data selector. The transmission rate of GOP between the double CPUs in the double-path CPU mainboard is improved. The main board is compatible with and connected with the SATA hard disk or the NVME disk. And remotely monitoring whether the SATA hard disk or the NVME disk is plugged into the mini SAS HD connector.

Description

Double-circuit server mainboard and server

Technical Field

The utility model relates to a computer technology field especially relates to a double-circuit server mainboard and server.

Background

The dual-path CPU main board is produced mainly for meeting the professional application requirements of a server, a graphic workstation and the like, so that the workstation main board is greatly different from a common main board, and system compatibility, BIOS function extension and the like are designed for the fields of the server, the graphic workstation and the like. Dual CPU motherboards typically use a server processor that supports dual CPU. The main board is logically a single computer, and an operating system can directly call the resources of two CPUs. If the single-path CPU main board of two ordinary computers is used, more problems are faced. Such as: there is not more display cards of space installation, two ordinary ATX mainboard connection lines are complicated and have a large amount of repeated hardware, need two power supplies to supply power, the space is compact for a long time operation simultaneously and is influenced stability. The data transmission efficiency between the double CPUs of the existing double-path CPU mainboard is low, and the mainboard is provided with the slots specially used for installing the SATA hard disk and the NVME disk, which are not compatible with each other, and the slots specially used for installing the SATA hard disk and the NVME disk occupy the larger area of the mainboard.

SUMMERY OF THE UTILITY MODEL

The utility model provides a double-circuit server mainboard for improve the transmission rate of the GOP between the two CPUs in the double-circuit CPU mainboard, realize a compatible SATA hard disk of connector or NVME dish on the double-circuit CPU mainboard, it is SATA hard disk or NVME dish to peg graft on the connector to be can remote monitoring simultaneously.

In a first aspect, the present invention provides a two-way server motherboard, which comprises a motherboard, a first central processing unit and a second central processing unit, wherein the first central processing unit and the second central processing unit are interconnected via a 2-group X16 XGMI. And a mini SAS HD connector connected with the first central processing unit is further arranged on the main board and used for connecting an SATA disk or an NVME disk. The main board is also provided with a data selector connected with the first central processing unit, and the data selector is also connected with a mini SAS HD connector; the data selector is used for automatically identifying the SATA disk or the NVME disk plugged in the mini SAS HD connector and selecting the SATA disk or the NVME disk to be connected with the first central processing unit. The mainboard is also provided with a BMC chip connected with the first central processing unit, and the BMC chip is also connected with the data selector.

In the scheme, the first central processing unit and the second central processing unit are interconnected by adopting two X16 XGMI buses, so that the transmission rate of GOPs between two CPUs on the two-way CPU mainboard can reach 12.8GT/S at most, and the transmission rate of GOPs between two CPUs in the two-way CPU mainboard is improved. Through set up compatible inserting connection SATA hard disk or NVME dish mini SAS HD connector on the mainboard, and the data selector, automatic identification is inserting on mini SAS HD connector whether SATA hard disk or NVME dish, and control is inserting on mini SAS HD connector whether SATA hard disk or NVME dish is connected with first central processing unit, thereby realize compatible SATA hard disk or NVME dish of mini SAS HD connector on the double-circuit CPU mainboard, make compatible inserting connection SATA hard disk or NVME dish of mainboard, reduce the number of slot on the mainboard. And meanwhile, a BMC chip is arranged on the mainboard and is also connected with the data selector, so that the data selector can be remotely controlled, and whether the SATA hard disk or the NVME disk is plugged into the mini SAS HD connector can be remotely monitored.

In a specific embodiment, the first central processing unit is further connected with a PCIE x4 socket, a PCIE x8 STORAGE socket for plug-in connection with an SAS/RAID memory card, a PCIE x1BM socket for connection with a secure card, and a PCIE x8 OCP a type socket for connection with the OCP network card; and the one PCIE x4 socket, the one PCIE x8 STORAGE socket, the one PCIE x1BM socket, and the one PCIE x8 OCP a-type socket are all disposed on the motherboard. The second central processing unit is also connected with a PCIE x16 socket and two PCIE x8 sockets; and the one PCIE x16 socket and the two PCIE x8 sockets are all disposed on the motherboard. Through setting up the PCIE socket of different grade type on the mainboard, improve the compatibility of mainboard.

In a specific embodiment, the first central processing unit is connected with a plurality of DDR channels, and the second central processing unit is connected with a plurality of DDR channels; wherein, each DDR Channel is connected with two DIMM memory slots. The memory frequency of the mainboard can reach 2933MHz to the maximum, so that the memory frequency of the mainboard is improved.

In a specific embodiment, the motherboard is further provided with a power regulator and a CPLD chip, wherein the power regulator and the CPLD chip are respectively connected to the first central processing unit and the second central processing unit, so as to control PWR BTN and RST BTN signals of the first central processing unit and the second central processing unit through the BMC chip network.

In a specific embodiment, the CPLD chip, the first central processor and the BMC chip are connected through an LPC bus. And a TCM security chip and a TPM security chip which are respectively connected with the LPC bus are also arranged on the mainboard, so that the security performance of the mainboard is improved.

In a specific embodiment, an I350 chip is further disposed on the motherboard, and the I350 chip is connected to the first central processing unit through a PCIE x2 signal; and RJ45 network interfaces connected with the I350 chip are also arranged on the mainboard. So that the mainboard can be connected with the outside through a network.

In a specific embodiment, the main board is further provided with an RJ45 network interface connected with a COMB PHY interface of the BMC chip, so that the BMC chip can be connected with the outside conveniently.

In a specific embodiment, a VGA converter is further disposed on the motherboard, the VGA converter is connected to the BMC chip, and the VGA converter is further connected to a VGA slot, so that the motherboard transmits the image signal to an external display.

In a specific embodiment, a BMC ROM and a BIOS ROM, both of which are connected to the BMC chip, are further disposed on the motherboard, and an SD card, which is connected to the BMC chip, is further disposed on the motherboard, so as to improve the performance of the BMC chip.

In a second aspect, the present invention also provides a server, which comprises any one of the above two-way server mainboards. By adopting two X16 XGMI buses to interconnect the first central processing unit and the second central processing unit, the transmission rate of GOP between two CPUs on the two-way CPU mainboard can reach 12.8GT/S at most, and the transmission rate of GOP between two CPUs in the two-way CPU mainboard is improved. Through set up compatible inserting connection SATA hard disk or NVME dish mini SAS HD connector on the mainboard, and the data selector, automatic identification is inserting on mini SAS HD connector whether SATA hard disk or NVME dish, and control is inserting on mini SAS HD connector whether SATA hard disk or NVME dish is connected with first central processing unit, thereby realize compatible SATA hard disk or NVME dish of mini SAS HD connector on the double-circuit CPU mainboard, make compatible inserting connection SATA hard disk or NVME dish of mainboard, reduce the number of slot on the mainboard. And meanwhile, a BMC chip is arranged on the mainboard and is also connected with the data selector, so that the data selector can be remotely controlled, and whether the SATA hard disk or the NVME disk is plugged into the mini SAS HD connector can be remotely monitored.

Drawings

Fig. 1 is a block diagram schematically illustrating a structure of a two-way server motherboard according to an embodiment of the present invention;

fig. 2 is a schematic diagram illustrating a connection between two cpus on a motherboard of a two-way server according to an embodiment of the present invention;

fig. 3 is a schematic block diagram illustrating a structure of the connection of the first central processing unit, the mini SAS HD connector, the data selector, and the BMC chip on the motherboard of the two-way server according to an embodiment of the present invention;

fig. 4 is a block diagram illustrating a structure of a PCIE slot connected to two central processing units on a motherboard of a two-way server according to an embodiment of the present invention;

fig. 5 is a schematic diagram of a two-way server motherboard according to an embodiment of the present invention, where two central processing units are connected to a DDR memory;

fig. 6 is a schematic diagram illustrating the power supply and power off of the cpu controlled by the BMC chip on the motherboard of the two-way server according to the embodiment of the present invention;

fig. 7 is a schematic connection diagram of an I350 chip on a motherboard of a two-way server according to an embodiment of the present invention;

fig. 8 is a schematic diagram of a connection between a BMC chip and an RJ45 network interface on a motherboard of a two-way server according to an embodiment of the present invention.

Reference numerals:

10-mainboard 11-first central processing unit 12-second central processing unit

21-mini SAS HD connector 22-data selector 23-BMC chip

31-power supply adjuster 32-CPLD chip 33-I350 chip 34-RJ45 network interface

41-VGA converter 42-VGA slot 43-BMC ROM 44-BIOS ROM

45-SD card 51-TCM security chip 52-TPM security chip

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

For conveniently understanding the utility model provides a two-way server mainboard, first explain below the utility model provides an application scene of two-way server mainboard, this two-way server mainboard is applied to in the server to as the hardware that realizes each function of server. The two-way server motherboard will be described in detail with reference to the accompanying drawings.

Referring to fig. 1, fig. 2 and fig. 3, an embodiment of the present invention provides a two-way server motherboard including a motherboard 10, a first central processing unit 11 and a second central processing unit 12 disposed on the motherboard 10, wherein the first central processing unit 11 and the second central processing unit 12 are interconnected through 2X 16 XGMI groups. A mini SAS HD connector 21 connected to the first central processing unit 11 is also provided on the main board 10, and the mini SAS HD connector 21 is used for connecting a SATA disk or an NVME disk. The main board 10 is further provided with a data selector 22 connected with the first central processing unit 11, and the data selector 22 is further connected with a mini SAS HD connector 21; the data selector 22 is configured to automatically identify the SATA disk or the NVME disk plugged into the mini SAS HD connector 21, and select the SATA disk or the NVME disk to connect to the first central processing unit 11. The main board 10 is further provided with a BMC chip 23 connected to the first central processor 11, and the BMC chip 23 is further connected to the data selector 22.

In the above scheme, the first central processing unit 11 and the second central processing unit 12 are interconnected by using two X16 XGMI buses, so that the transmission rate of the GOP between the two CPUs on the two-way CPU board 10 can reach 12.8GT/S at most, and the transmission rate of the GOP between the two CPUs in the two-way CPU board 10 is improved. Through set up compatible mini SAS HD connector 21 of pegging graft connection SATA hard disk or NVME dish on mainboard 10, and data selector 22, automatic identification pegs graft on mini SAS HD connector 21 is SATA hard disk or NVME dish, and control pegs graft on mini SAS HD connector 21 is SATA hard disk or NVME dish and is connected with first central processing unit 11, thereby realize compatible SATA hard disk or NVME dish of mini SAS HD connector 21 on double-circuit CPU mainboard 10, make mainboard 10 compatible grafting SATA hard disk or NVME dish, reduce the number of slot on mainboard 10. Meanwhile, the BMC chip 23 is arranged on the mainboard 10, and the BMC chip 23 is also connected with the data selector 22, so that the data selector 22 can be remotely controlled, and whether the SATA hard disk or the NVME disk is plugged on the mini SAS HD connector 21 can be remotely monitored. The configuration of each hardware described above will be described in detail with reference to the drawings.

When the motherboard 10 is provided, referring to fig. 1 and 2, the motherboard 10 is a printed circuit board capable of being provided with devices such as a central processing unit. The mainboard 10 is provided with a first central processing unit 11 and a second central processing unit 12, and the first central processing unit 11 and the second central processing unit 12 are interconnected through two X16 XGMI buses, so that the transmission rate of GOPs between two CPUs on the two-way CPU mainboard 10 can reach 12.8GT/S at most, and the transmission rate of GOPs between two CPUs in the two-way CPU mainboard 10 is improved. When the first central processing unit 11 and the second central processing unit 12 are disposed on the motherboard 10, two CPU slots may be disposed on the motherboard 10, and the first central processing unit 11 and the second central processing unit 12 are respectively mounted on the two CPU slots. The two CPU slots may be sockets or slots. When the first central processing unit 11 and the second central processing unit 12 are disposed, the first central processing unit 11 may be a main central processing unit, and the second central processing unit 12 may be a sub-central processing unit. Specifically, when the models of the first central processing unit 11 and the second central processing unit 12 are selected, two pieces of the Hai-Fi 5100/5200CPU chips can be selected as the first central processing unit 11 and the second central processing unit 12.

Referring to fig. 1 and 3, a mini SAS HD connector 21 connected to the first central processing unit 11 is further provided on the main board 10, and the mini SAS HD connector 21 is used for connecting a SATA disk or an NVME disk. The main board 10 is further provided with a data selector 22 connected with the first central processing unit 11, and the data selector 22 is further connected with a mini SAS HD connector 21; the data selector 22 is configured to automatically identify the SATA disk or the NVME disk plugged into the mini SAS HD connector 21, and select the SATA disk or the NVME disk to connect to the first central processing unit 11. Through set up compatible mini SAS HD connector 21 of pegging graft connection SATA hard disk or NVME dish on mainboard 10, and data selector 22, automatic identification pegs graft on mini SAS HD connector 21 is SATA hard disk or NVME dish, and control pegs graft on mini SAS HD connector 21 is SATA hard disk or NVME dish and is connected with first central processing unit 11, thereby realize compatible SATA hard disk or NVME dish of mini SAS HD connector 21 on double-circuit CPU mainboard 10, make mainboard 10 compatible grafting SATA hard disk or NVME dish, reduce the number of slot on mainboard 10.

As shown in fig. 1 and 3, a BMC chip 23 connected to the first central processor 11 is further provided on the motherboard 10, and the BMC chip 23 is further connected to the data selector 22. Therefore, the data selector 22 can be remotely controlled, and whether the SATA hard disk or the NVME disk is plugged on the mini SAS HD connector 21 can be remotely monitored.

Referring to fig. 4, different PCIE sockets may also be disposed on the motherboard 10, so as to improve the performance of adapting the motherboard 10 to different types of PCIE expansion cards. Specifically, as shown in fig. 4, the first central processing unit 11 may be connected to a PCIE x4 socket, a PCIE x8 STORAGE socket for plugging and connecting an SAS/RAID memory card, a PCIE x1BM socket for connecting a security card, and a PCIE x8 OCP a-type socket for connecting the OCP network card; and the one PCIE x4 socket, the one PCIE x8 STORAGE socket, the one PCIE x1BM socket, and the one PCIE x8 OCP a-type socket are all disposed on the motherboard 10. The second central processor 12 is further connected to a PCIE x16 socket and two PCIE x8 sockets; and the PCIE x16 socket and the two PCIE x8 sockets are all disposed on the motherboard 10. Through setting up the PCIE socket of different grade type on mainboard 10, improve mainboard 10's compatibility. During setting, the first central processing unit 11 and the second central processing unit 12 can provide PCIE sockets with high bandwidth, connect the COMB PHYs (function configurable interfaces) of the first central processing unit 11 and the second central processing unit 12, and support PCIE, SATA hard disks, and XGBE network devices by inserting expansion cards.

Referring to fig. 1 and 4, when one PCIE x16 socket is disposed, as shown in PCIE x16Slot1 in fig. 1 and 7, the PCIE x16Slot1 is connected to P2[15:0] of the second central processor 12, and can support PCIE standard card x16/x8/x4/x2/x1, and by inserting different patch panels, 2 x8 PCIE slots or 1 x8+2 x4 PCIE slots can be implemented.

When a PCIE x4 socket is configured, as the PCIE x4 Slot2 shown in fig. 1 and fig. 7, the PCIE x4 Slot2 is linked to P0[15:12] of the first central processing unit 11, and may support a PCIE standard card x4/x2/x 1.

When two PCIE x8 sockets are provided, as shown in fig. 1 and fig. 7, PCIE x8 Slot3 and PCIE x8 Slot4, the PCIE x8 Slot3 and PCIE x8 Slot4 are respectively connected to a COMB PHY P0[15:8] and a P0[7:0] of the second central processor 12, and can support PCIE standard cards x8/x4/x2/x 1; or support 2 x4 PCIE slots by plugging in a patch panel; other adapter boards can be inserted to be switched into 4 XGBE network interfaces and 4 SATA hard disk interfaces.

When a PCIE x8 STORAGE Slot is provided, such as the PCIE x8 STORAGE Slot shown in FIG. 1 and FIG. 7, the PCIE x8 STORAGE Slot is connected to the P0[15:8] of the first central processor 11 for inserting the SAS/RAID memory card.

When a PCIE x1BM socket is provided, like the PCIE x1BM Slot shown in fig. 1 and fig. 7, the PCIE x1BM Slot is connected to the P0[0] of the first central processing unit 11, and can support a secure card, and if the secure card is not supported, the method can be used for other PCIE x1 card.

When a PCIE x8 OCP a socket is set, as a PCIE x8 OCP a Slot shown in fig. 1 and fig. 7, the PCIE x8 OCP a Slot is connected to P2[7:0] of the first central processing unit 11, and is used to support an a-type OCP card.

As shown in fig. 5, a plurality of DDR channels may be connected to the first central processor 11, and a plurality of DDR channels may be connected to the second central processor 12; wherein, each DDR Channel is connected with two DIMM memory slots. The memory frequency of the main board 10 can reach 2933MHz to improve the memory frequency of the main board 10. The number of the DDR channels connected to each central processing unit may be 2, 3, 4, 5, and the like, which improves the memory frequency of the motherboard 10. When each central processing unit is connected with 4 DDR channels, the main board 10 supports 16 DDR4 memory slots altogether, the memory frequency can reach 3200MHz at most, and supports RDIMM and LRDIMM. The connection relationship is shown in the following figure 5, each central processor mounts 8 DDR4 DIMM slots, supports UDIMM/RDIMM/LRDIMM/NVDIMM, and supports DDR 4-3200.

As shown in fig. 1, a power regulator 31 (VR in fig. 1) connected to the first central processing unit 11 and the second central processing unit 12, respectively, and a CPLD chip 32 connected to the power regulator 31 may be further disposed on the motherboard 10, so as to control the PWR BTN and RST BTN signals of the first central processing unit 11 and the second central processing unit 12 through the BMC chip 23 network. The power supply adjuster 31 for supplying power to the central processing unit and the power-on and power-off time sequence of the signal input to the central processing unit can be flexibly adjusted through the logic codes, so that the requirements of the power-on and power-off sequence of the central processing unit are met. The BMC chip 23 performs power-on/power-off control on the motherboard 10, and the Reset control circuit controls the PWR BTN signal and the RST BTN signal of the central processing unit through the BMC chip 23 as shown in fig. 6, so as to implement power-on and power-off control on the motherboard 10.

Referring to fig. 1, the CPLD chip 32 may be connected to both the first central processor 11 and the BMC chip 23 through LPC buses. And a TCM security chip 51 and a TPM security chip 52, both connected to the LPC bus, are further disposed on the motherboard 10 to improve the security of the motherboard 10.

Referring to fig. 7, an I350 chip 33 may also be disposed on the motherboard 10, and the I350 chip 33 is connected to the first central processor 11 through a PCIE x2 signal; the main board 10 is further provided with RJ45 network interfaces 34 respectively connected to the I350 chip 33. So that the main board 10 can be connected to the outside through a network. The number of the RJ45 network interfaces 34 may be 1, 2, 3, etc. As shown in fig. 1, the main board 10 is further provided with an RJ45 network interface 34 connected to the COMB PHY interface of the BMC chip 23, so that the BMC chip 23 can be connected to the outside.

As shown in fig. 1, a VGA converter 41 may be further disposed on the motherboard 10, the VGA converter 41 is connected to the BMC chip 23, and the VGA converter 41 is further connected to a VGA slot 42, so that the motherboard 10 transmits the image signal to an external display.

With reference to fig. 1, a BMC ROM43 and a BIOS ROM44, which are respectively connected to the BMC chip 23, may be further disposed on the motherboard 10, and an SD card 45 connected to the BMC chip 23 is further disposed on the motherboard 10, so as to improve the performance of the BMC chip 23.

As shown in fig. 1, the two-way server motherboard may be configured with 5 USB 3.0&2.0 interfaces and 4 USB2.0 interfaces on the motherboard 10, where each of the USB 3.0&2.0 interface and the USB2.0 interface is connected to two central processing units as shown in fig. 1. The two-way server mainboard can support 5 USB 3.0&2.0 interfaces and 4 USB2.0 interfaces. The USB2.0 signal may also be connected to the BMC chip 23 for supporting Virtual Media, so as to implement a remote video monitoring function of the BMC chip 23.

By interconnecting the first central processing unit 11 and the second central processing unit 12 by adopting two X16 XGMI buses, the transmission rate of GOP between two CPUs on the two-way CPU mainboard 10 can reach 12.8GT/S at most, and the transmission rate of GOP between two CPUs in the two-way CPU mainboard 10 is improved. Through set up compatible mini SAS HD connector 21 of pegging graft connection SATA hard disk or NVME dish on mainboard 10, and data selector 22, automatic identification pegs graft on mini SAS HD connector 21 is SATA hard disk or NVME dish, and control pegs graft on mini SAS HD connector 21 is SATA hard disk or NVME dish and is connected with first central processing unit 11, thereby realize compatible SATA hard disk or NVME dish of mini SAS HD connector 21 on double-circuit CPU mainboard 10, make mainboard 10 compatible grafting SATA hard disk or NVME dish, reduce the number of slot on mainboard 10. Meanwhile, the BMC chip 23 is arranged on the mainboard 10, and the BMC chip 23 is also connected with the data selector 22, so that the data selector 22 can be remotely controlled, and whether the SATA hard disk or the NVME disk is plugged on the mini SAS HD connector 21 can be remotely monitored.

In addition, the embodiment of the present invention further provides a server, referring to fig. 1, fig. 2 and fig. 3, the server includes any one of the above two-way server main boards. By interconnecting the first central processing unit 11 and the second central processing unit 12 by adopting two X16 XGMI buses, the transmission rate of GOP between two CPUs on the two-way CPU mainboard 10 can reach 12.8GT/S at most, and the transmission rate of GOP between two CPUs in the two-way CPU mainboard 10 is improved. Through set up compatible mini SAS HD connector 21 of pegging graft connection SATA hard disk or NVME dish on mainboard 10, and data selector 22, automatic identification pegs graft on mini SAS HD connector 21 is SATA hard disk or NVME dish, and control pegs graft on mini SAS HD connector 21 is SATA hard disk or NVME dish and is connected with first central processing unit 11, thereby realize compatible SATA hard disk or NVME dish of mini SAS HD connector 21 on double-circuit CPU mainboard 10, make mainboard 10 compatible grafting SATA hard disk or NVME dish, reduce the number of slot on mainboard 10. Meanwhile, the BMC chip 23 is arranged on the mainboard 10, and the BMC chip 23 is also connected with the data selector 22, so that the data selector 22 can be remotely controlled, and whether the SATA hard disk or the NVME disk is plugged on the mini SAS HD connector 21 can be remotely monitored.

The above description is only for the specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (10)

1. A two-way server motherboard, comprising:

a main board;

the first central processing unit and the second central processing unit are arranged on the mainboard, wherein the first central processing unit and the second central processing unit are interconnected through a 2-group X16 XGMI bus;

the mini SAS HD connector is arranged on the mainboard and connected with the first central processing unit, and is used for connecting an SATA disk or an NVME disk;

the data selector is arranged on the main board and connected with the first central processing unit, and the data selector is also connected with the mini SAS HD connector; the data selector is used for automatically identifying the SATA disk or the NVME disk inserted into the mini SAS HD connector and selecting the SATA disk or the NVME disk to be connected with the first central processing unit;

the BMC chip is arranged on the mainboard and connected with the first central processing unit, and the BMC chip is further connected with the data selector.

2. The two-way server motherboard of claim 1, wherein the first central processor is further connected with a PCIE x4 slot, a PCIE x8 STORAGE interface for plug-in connection with an SAS/RAID memory card, a PCIE x1BM interface for connection with a security card, and a PCIE x8 OCP a type interface for connection with an OCP network card; and the one PCIE x4 socket, the one PCIE x8 STORAGE socket, the one PCIE x1BM socket, and the one PCIE x8 OCP a-type socket are all disposed on the motherboard;

the second central processing unit is further connected with a PCIE x16 socket and two PCIE x8 sockets, and the PCIE x16 socket and the two PCIE x8 sockets are arranged on the mainboard.

3. The two-way server motherboard of claim 1, wherein a plurality of DDR channels are connected to the first central processor, and a plurality of DDR channels are connected to the second central processor; wherein, each DDR Channel is connected with two DIMM memory slots.

4. The two-way server motherboard of claim 1, further provided with a power regulator and a CPLD chip, wherein the power regulator and the CPLD chip are connected to the first central processing unit and the second central processing unit, respectively.

5. The two-way server motherboard of claim 4, wherein the CPLD chip, the first central processor and the BMC chip are connected via LPC bus;

and the mainboard is also provided with a TCM security chip and a TPM security chip which are respectively connected with the LPC bus.

6. The two-way server motherboard of claim 1, wherein the motherboard is further provided with an I350 chip, and the I350 chip is connected to the first central processing unit by a PCIE x2 signal;

and the main board is also provided with RJ45 network interfaces which are respectively connected with the I350 chip.

7. The two-way server motherboard of claim 6, wherein the motherboard further comprises an RJ45 network interface connected to the COMB PHY interface of the BMC chip.

8. The two-way server motherboard as recited in claim 1, further comprising a VGA converter disposed on the motherboard, wherein the VGA converter is connected to the BMC chip, and wherein the VGA converter is further connected to a VGA slot.

9. The two-way server motherboard of claim 1, further comprising a BMC ROM and a BIOS ROM respectively connected to the BMC chip; and the mainboard is also provided with an SD card connected with the BMC chip.

10. A server, comprising the two-way server motherboard according to any one of claims 1 to 9.

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