CN113434443A - System and method for supporting automatic switching of PCIE (peripheral component interface express) clock - Google Patents
System and method for supporting automatic switching of PCIE (peripheral component interface express) clock Download PDFInfo
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
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- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
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Abstract
The invention provides a system and a method for supporting automatic switching of a PCIE clock, wherein the system comprises a BMC, an in-place detection module, a clock buffer module, a hard disk backboard and a PCIE adapter card; the on-site detection module is connected with a plurality of onboard PCIE slots; the clock buffer module is connected with a plurality of clock expansion interfaces; the BMC acquires the on-position states of the onboard PCIE slot, the PCIE switching slot and the hard disk interface through the on-position detection module and the CPLD, and then starts the clocks of the PCIE slot, the PCIE switching slot and the hard disk interface of the on-position equipment through the clock buffer module and closes the clocks of the PCIE slot, the PCIE switching slot and the hard disk interface of the off-position equipment. The invention automatically closes the onboard PCIE slot without the PCIE equipment, the PCIE switching slot and the clock channel corresponding to the hard disk interface, thereby saving electric energy, avoiding electromagnetic interference and improving the stability of the server.
Description
Technical Field
The invention belongs to the technical field of PCIE clock control, and particularly relates to a system and a method for supporting automatic switching of a PCIE clock.
Background
With the rapid development of the internet, the deployment number of servers is also exponentially increased; the large number of servers provides the computing base for the network, but also consumes high amounts of power. And server energy saving management has become a focus of attention of many internet manufacturers today with increasing energy costs. A large number of interfaces are designed for the PCIE equipment in the server system, whether the PCIE equipment is deployed or not is determined according to different configurations, and each interface can design a 100M clock for the PCIE equipment and is usually in an open state; in some simple configurations, the PCIE interfaces are not equipped with devices, but the clocks are turned on, which causes a lot of power waste, and the 100M clock is a high-frequency signal, and in the case of no PCIE device, similar to a single-ended antenna, electromagnetic radiation is generated, which causes an EMI problem and affects the stability of the server operation.
Therefore, it is very necessary to provide a system and a method for supporting automatic switching of PCIE clocks to overcome the above-mentioned drawbacks in the prior art.
Disclosure of Invention
The invention provides a system and a method for supporting automatic switching of a PCIE clock, aiming at the defects that in the prior art, a server designs a clock for each PCIE device, when a PCIE interface is not provided with a device, the started clock causes power waste and brings electromagnetic radiation, and the technical problem is solved.
In a first aspect, the invention provides a system supporting automatic switching of a PCIE clock, including a BMC, an in-place detection module, a clock buffer module, a hard disk backplane, and a PCIE adapter card;
the on-site detection module is connected with a plurality of on-board PCIE slots, and the clock buffer module is connected with each on-board PCIE slot;
the clock buffer module is connected with a plurality of clock expansion interfaces;
the PCIE switching card is provided with a plurality of switching ports, each switching port is connected with a PCIE switching slot, each PCIE switching slot and the PCIE switching card are connected with the on-site detection module, and each switching port is connected with a clock expansion interface;
the hard disk backboard is provided with a CPLD, the CPLD is connected with a plurality of hard disk interfaces, each hard disk interface is connected with a clock expansion interface, and the hard disk backboard is also connected with the on-site detection module;
the BMC is connected with the in-place detection module, the clock buffer module and the CPLD;
the BMC acquires the on-position states of the onboard PCIE slot, the PCIE switching slot and the hard disk interface through the on-position detection module and the CPLD, and then starts the clocks of the PCIE slot, the PCIE switching slot and the hard disk interface of the on-position equipment through the clock buffer module and closes the clocks of the PCIE slot, the PCIE switching slot and the hard disk interface of the off-position equipment. The clock buffer module provides 100M clocks for on-site on-board PCIE slots of the equipment, and the clock buffer module provides 100M clocks for the on-site PCIE switching slots and the hard disk interface of the equipment through the clock expansion interface.
Further, the in-place detection module adopts an IO extension chip of 9554 model. The 9554 model IO expansion chip may identify an in-place state of a hard disk backplane, an in-place state of a PCIE adapter card, an in-place state of a device of an on-board PCIE slot, and an in-place state of a device of a PCIE adapter slot.
Further, the on-board PCIE slot includes a first on-board PCIE slot, a second on-board PCIE slot, a third on-board PCIE slot, and a fourth on-board PCIE slot;
the on-site detection module is provided with a first PCIE detection interface, a second PCIE detection interface, a third PCIE detection interface and a fourth PCIE detection interface;
the first PCIE detection interface is connected with a first onboard PCIE slot, the second PCIE detection interface is connected with a second onboard PCIE slot, the third PCIE detection interface is connected with a third onboard PCIE slot, and the fourth PCIE detection interface is connected with a fourth onboard PCIE slot. The on-line detection module detects whether the PCIE equipment of each onboard PCIE slot is on line through each PCIE detection interface.
Further, the adapter comprises a first adapter and a second adapter;
the PCIE switching slots comprise a first PCIE switching slot and a second PCIE switching slot;
the first switching interface is connected with the first PCIE switching slot, and the second switching interface is connected with the second PCIE switching slot;
the on-site detection module is also provided with a fifth PCIE detection interface and a sixth PCIE detection interface;
the fifth PCIE detection interface is connected with the first PCIE switching slot, and the sixth PCIE monitoring interface is connected with the second PCIE switching slot;
the on-line detection module is also provided with a PCIE switching card on-line detection interface and a hard disk backboard on-line detection interface;
the PCIE switching card in-place detection interface is connected with the PCIE switching card, and the hard disk backboard in-place detection interface is connected with the hard disk backboard. The in-place detection module can detect whether the PCIE switching card is in place or not and can detect whether a PCIE switching slot on the PCIE switching card is in place or not.
Further, the hard disk interface comprises a first hard disk interface, a second hard disk interface, a third hard disk interface and a fourth hard disk interface;
the CPLD is connected with the first hard disk interface, the second hard disk interface, the third hard disk interface and the fourth hard disk interface. The hard disk backboard is detected in place through the in-place detection module, and the equipment of the hard disk interface is detected in place through the CPLD.
Further, the clock expansion interface comprises a first clock expansion interface and a second clock expansion interface;
a first clock expansion channel and a second clock expansion channel are arranged on the first clock expansion interface; a third clock expansion channel and a fourth clock expansion channel are arranged on the second clock expansion interface;
the clock buffer module is provided with a first clock interface, a second clock interface, a third clock interface, a fourth clock interface, a fifth clock interface, a sixth clock interface, a seventh clock interface and an eighth clock interface;
the first clock interface is connected with a first onboard PCIE slot, the second clock interface is connected with a second onboard PCIE slot, the third clock interface is connected with a third onboard PCIE slot, and the fourth clock interface is connected with a fourth onboard PCIE slot;
the fifth clock interface is connected with the first clock expansion channel, and the other end of the first clock expansion channel is connected with the first switching interface and the second hard disk interface;
the sixth clock interface is connected with the second clock expansion channel, and the other end of the second clock expansion channel is connected with the second hard disk interface;
the seventh clock interface is connected with the third clock expanding channel, and the other end of the third clock expanding channel is connected with the second switching interface and the fourth hard disk interface;
and the eighth clock interface is connected with the fourth clock expansion channel, and the other end of the fourth clock expansion channel is connected with the third hard disk interface. The two clock expansion interfaces are used for expanding two PCIE switching slots on a PCIE switching card or four NVME hard disks serving as hard disk interfaces on an expanded hard disk backboard. Each clock expansion interface is designed with 2 groups of 100M clocks, and when the clock expansion interface is expanded to a PCIE switching slot on a PCIE switching card, the clock expansion interface only needs to provide one group of clocks; when the expansion is extended to a hard disk backboard to be used as an NVME hard disk of a hard disk interface, two groups of clocks of the clock expansion interface are provided.
Further, the BMC is connected with the in-place detection module through a first SMBUS, the BMC is connected with the clock buffer module through a second SMBUS, and the BMC is connected with the CPLD through a third SMBUS. The whole system BMC is used as a core controller and is respectively connected to the in-place detection module, the clock buffer module and the CPLD chip of the hard disk backboard through the SMBUS; the BMC reads the deployment condition of the PCIE standard card used for acquiring the current configuration and each PCIE slot of the current configuration and reads the deployment condition of the NVME hard disk used for acquiring the current configuration as the hard disk interface; and then, the register of the clock buffer module is read and written through the SMBUS to realize the open-close control of each clock channel.
In a second aspect, the present invention provides a method for supporting automatic switching of a PCIE clock based on the first aspect, including the following steps:
s1, the BMC acquires the equipment on-site states of each onboard PCIE slot, each PCIE switching slot and each hard disk interface through an on-site detection module and a CPLD;
and S2, the BMC starts the clocks of the PCIE slot, the PCIE switching slot and the hard disk interface of the equipment in place through the clock buffer module and closes the clocks of the PCIE slot, the PCIE switching slot and the hard disk interface of the equipment out of place.
Further, the step S1 specifically includes the following steps:
s11, the BMC acquires the on-position state of each onboard PCIE slot device, the on-position state of the PCIE adapter card and the on-position state of the hard disk backboard through an on-position detection module;
s12, the BMC sets an on-position on-board PCIE slot of the equipment to be an active on-board PCIE slot, and sets an off-position on-board PCIE slot of the equipment to be a standby on-board PCIE slot;
s13, when the PCIE switching card is in place, the BMC acquires the equipment in-place state of each PCIE switching slot through an in-place detection module, sets the PCIE switching slot with the equipment in place as an active PCIE switching slot and sets the PCIE switching slot with the equipment out of place as a standby PCIE switching slot;
s14, when the hard disk backboard is in place, the BMC acquires the in-place state of equipment of each hard disk interface through the CPLD, sets the in-place hard disk interface of the equipment as an active hard disk interface, and sets the hard disk interface of the equipment which is not in place as a standby hard disk interface.
Further, the step S2 specifically includes the following steps:
s21, the BMC starts a clock interface corresponding to each active onboard PCIE slot through a clock buffer module and closes a clock interface corresponding to each standby onboard PCIE slot;
s22, the BMC opens a clock interface corresponding to the clock expansion channel where each active PCIE switching slot is located through a clock buffer module, and closes the clock interface corresponding to the clock expansion channel where each standby PCIE switching slot is located;
and S23, the BMC opens the clock interface corresponding to the clock expansion channel where each active hard disk interface is located through the clock buffer module, and closes the clock interface corresponding to the clock expansion channel where each standby hard disk interface is located.
Further, when the first PCIE switch slot and the second hard disk interface are not in place, the BMC closes the fifth clock interface corresponding to the first clock expansion channel through the clock buffer module;
when at least one device in the first PCIE switching slot and the second hard disk interface is in place, the BMC starts a fifth clock interface corresponding to the first clock expansion channel through the clock buffer module;
when the second PCIE switching slot and the fourth hard disk interface are out of place, the BMC closes a seventh clock interface corresponding to the third clock expansion channel through the clock buffer module;
when at least one device in the second PCIE switch slot and the fourth hard disk interface is in place, the BMC starts a seventh clock interface corresponding to the third clock expansion channel through the clock buffer module.
The beneficial effect of the invention is that,
according to the system and the method for supporting automatic opening and closing of the PCIE clock, the clock channels corresponding to the onboard PCIE slot without the PCIE equipment, the PCIE switching slot and the hard disk interface can be automatically closed according to the in-place condition of the PCIE equipment, so that the power consumption is saved, the EMI problem is avoided, and the stability of the server is improved.
In addition, the invention has reliable design principle, simple structure and very wide application prospect.
Therefore, compared with the prior art, the invention has prominent substantive features and remarkable progress, and the beneficial effects of the implementation are also obvious.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a system supporting automatic switching of a PCIE clock according to the present invention;
fig. 2 is a table of the system clock mapping relationship supporting automatic switching of PCIE clocks according to the present invention;
fig. 3 is a first flowchart of a method supporting automatic switching of a PCIE clock according to the present invention;
fig. 4 is a flowchart illustrating a second method for supporting automatic switching of a PCIE clock according to the present invention;
in the figure, 1-BMC; 2-an in-place detection module; 3-a clock buffer module; 4-hard disk backplane; 5-PCIE switching card; 6-CPLD; SLOT 1-first onboard PCIE SLOT; SLOT 2-second onboard PCIE SLOT; SLOT 3-third on-board PCIE SLOT; SLOT 4-fourth onboard PCIE SLOT; SLOT 5-first PCIE translate SLOT; SLOT 6-second PCIE transfer SLOT; HDD1 — first hard disk interface; HDD 2-second hard disk interface; HDD 3-third hard disk interface; HDD 4-fourth hard disk interface; MCIO0 — first clock extension interface; MCIO1 — second clock extension interface; r1 — first interface; r2 — second interface.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
PCIe is a high-speed serial computer expansion bus, a short term for Peripheral Component Interconnect Express.
The BMC is a substrate Management Controller, which is an abbreviation of the Baseboard Management Controller.
CPLD is a Complex Programmable Logic Device for short of Complex Programmable Logic Device.
EMI is the abbreviation of Electromagnetic Interference (EMI) for Electromagnetic Interference.
SMBUS, a System Management Bus for short, has a data transmission rate of 100kbps, although the speed is slow, and has the characteristics of simple structure and low cost, so the SMBUS becomes an interface standard popular in the industry.
Example 1:
as shown in fig. 1, the present invention provides a system supporting automatic switching of a PCIE clock, including a BMC 1, an in-place detection module 2, a clock buffer module 3, a hard disk backplane 4, and a PCIE adapter card 5;
the on-site detection module 2 is connected with a plurality of on-board PCIE slots, and the clock buffer module 3 is connected with each on-board PCIE slot;
the clock buffer module 3 is connected with a plurality of clock expansion interfaces;
a plurality of switching interfaces are arranged on the PCIE switching card 5, each switching interface is connected with a PCIE switching slot, each PCIE switching slot and the PCIE switching card 5 are both connected with the on-site detection module 2, and each switching interface is connected with a clock expansion interface;
the hard disk backboard 4 is provided with a CPLD 6, the CPLD 6 is connected with a plurality of hard disk interfaces, each hard disk interface is connected with a clock expansion interface, and the hard disk backboard 4 is also connected with the on-site detection module 2;
the BMC 1 is connected with the in-place detection module 2, the clock buffer module 3 and the CPLD 6;
the BMC 1 acquires the on-site states of the onboard PCIE slot, the PCIE switch slot, and the hard disk interface through the on-site detection module 2 and the CPLD 6, and then turns on the clocks of the PCIE slot, the PCIE switch slot, and the hard disk interface where the device is on site through the clock buffer module 3, and turns off the clocks of the PCIE slot, the PCIE switch slot, and the hard disk interface where the device is not on site.
Example 2:
as shown in fig. 1, the present invention provides a system supporting automatic switching of a PCIE clock, including a BMC 1, an in-place detection module 2, a clock buffer module 3, a hard disk backplane 4, and a PCIE adapter card 5;
the on-site detection module 2 is connected with a plurality of on-board PCIE slots, and the clock buffer module 3 is connected with each on-board PCIE slot; the in-place detection module 2 adopts an IO expansion chip of 9554 model;
the clock buffer module 3 is connected with a plurality of clock expansion interfaces;
a plurality of switching interfaces are arranged on the PCIE switching card 5, each switching interface is connected with a PCIE switching slot, each PCIE switching slot and the PCIE switching card 5 are both connected with the on-site detection module 2, and each switching interface is connected with a clock expansion interface;
the hard disk backboard 4 is provided with a CPLD 6, the CPLD 6 is connected with a plurality of hard disk interfaces, each hard disk interface is connected with a clock expansion interface, and the hard disk backboard 4 is also connected with the on-site detection module 2;
the BMC 1 is connected with the in-place detection module 2, the clock buffer module 3 and the CPLD 6;
the BMC 1 acquires the equipment on-site states of an onboard PCIE slot, a PCIE switching slot and a hard disk interface through the on-site detection module 2 and the CPLD 6, and then starts the clocks of the PCIE slot, the PCIE switching slot and the hard disk interface of the equipment on-site through the clock buffer module 3 and closes the clocks of the PCIE slot, the PCIE switching slot and the hard disk interface of the equipment which are not on-site;
the on-board PCIE SLOTs include a first on-board PCIE SLOT1, a second on-board PCIE SLOT2, a third on-board PCIE SLOT3, and a fourth on-board PCIE SLOT SOLT 4;
the on-site detection module 2 is provided with a first PCIE detection interface, a second PCIE detection interface, a third PCIE detection interface and a fourth PCIE detection interface;
the first PCIE detection interface is connected with a first onboard PCIE SLOT SLOT1, the second PCIE detection interface is connected with a second onboard PCIE SLOT SLOT2, the third PCIE detection interface is connected with a third onboard PCIE SLOT SLOT3, and the fourth PCIE detection interface is connected with a fourth onboard PCIE SLOT SOLT 4;
the adapter comprises a first adapter R1 and a second adapter R2;
the PCIE switch SLOTs include a first PCIE switch SLOT5 and a second PCIE switch SLOT 6;
the first interface R1 is connected with a first PCIE transfer SLOT SLOT5, and the second interface R2 is connected with a second PCIE transfer SLOT SLOT 6;
the on-site detection module 2 is also provided with a fifth PCIE detection interface and a sixth PCIE detection interface;
the fifth PCIE detection interface is connected to the first PCIE switch SLOT5, and the sixth PCIE detection interface is connected to the second PCIE switch SLOT 6;
the on-site detection module 2 is also provided with a PCIE switching card on-site detection interface and a hard disk backboard on-site detection interface;
the PCIE switching card on-site detection interface is connected with the PCIE switching card 5, and the hard disk backboard on-site detection interface is connected with the hard disk backboard 4;
the hard disk interfaces include a first hard disk interface HDD1, a second hard disk interface HDD2, a third hard disk interface HDD3 and a fourth hard disk interface HDD 4;
the CPLD 6 is connected with the first hard disk interface HDD1, the second hard disk interface HDD2, the third hard disk interface HDD3 and the fourth hard disk interface HDD 4;
the clock extension interface comprises a first clock extension interface MCIO0 and a second clock extension interface MCIO 1;
a first clock expansion channel and a second clock expansion channel are arranged on the first clock expansion interface MCIO 0; a third clock expansion channel and a fourth clock expansion channel are arranged on the second clock expansion interface MCIO 1;
the clock buffer module 3 is provided with a first clock interface, a second clock interface, a third clock interface, a fourth clock interface, a fifth clock interface, a sixth clock interface, a seventh clock interface and an eighth clock interface;
the first clock interface is connected with a first onboard PCIE SLOT SLOT1, the second clock interface is connected with a second onboard PCIE SLOT SLOT2, the third clock interface is connected with a third onboard PCIE SLOT SLOT3, and the fourth clock interface is connected with a fourth onboard PCIE SLOT SOLT 4;
the fifth clock interface is connected with the first clock expansion channel, and the other end of the first clock expansion channel is connected with the first switching interface R1 and the second hard disk interface HDD 2;
the sixth clock interface is connected with the second clock expansion channel, and the other end of the second clock expansion channel is connected with the second hard disk interface HDD 2;
the seventh clock interface is connected with the third clock expansion channel, and the other end of the third clock expansion channel is connected with the second switching interface R2 and the fourth hard disk interface HDD 4;
the eighth clock interface is connected with a fourth clock expansion channel, and the other end of the fourth clock expansion channel is connected with a third hard disk interface HDD 3;
the BMC 1 is connected with the in-place detection module 2 through a first SMBUS, the BMC 1 is connected with the clock buffer module 3 through a second SMBUS, and the BMC 3 is connected with the CPLD 6 through a third SMBUS;
four onboard PCIE slots on board in the system are fixedly configured, and the BMC 3 can know whether the PCIE standard cards of the onboard PCIE slots are deployed or not only by reading in-place signals of the PCIE equipment through the in-place detection module 2; however, the clocks output by the two clock expansion interfaces and the PCIE device are expanded through cables, and different configuration scenarios exist, so that it is necessary to read in-place signals of the PCIE adapter card 5 and the hard disk backplane 4 through the in-place detection module 2 to determine which configuration is currently in. For example, when the BMC 3 reads the in-place information of the PCIE switch card 5, it determines that the current clock expansion interface is expanded to the PCIE standard card corresponding to the PCIE switch slot of the PCIE switch card 5, and then controls the clock of the corresponding clock channel to be turned on or off according to the in-place condition of the PCIE standard card corresponding to the PCIE switch slot of the PCIE switch card 5; the clock correspondence relationship of PCIE devices is shown in fig. 2.
Example 3:
as shown in fig. 3, the present invention provides a method for supporting automatic switching of a PCIE clock based on the foregoing embodiment 1 or embodiment 2, including the following steps:
s1, the BMC acquires the equipment on-site states of each onboard PCIE slot, each PCIE switching slot and each hard disk interface through an on-site detection module and a CPLD;
and S2, the BMC starts the clocks of the PCIE slot, the PCIE switching slot and the hard disk interface of the equipment in place through the clock buffer module and closes the clocks of the PCIE slot, the PCIE switching slot and the hard disk interface of the equipment out of place.
Example 4:
as shown in fig. 4, the present invention provides a method for supporting automatic switching of a PCIE clock, including the following steps:
s1, the BMC acquires the equipment on-site states of each onboard PCIE slot, each PCIE switching slot and each hard disk interface through an on-site detection module and a CPLD; the method comprises the following specific steps:
s11, the BMC acquires the on-position state of each onboard PCIE slot device, the on-position state of the PCIE adapter card and the on-position state of the hard disk backboard through an on-position detection module;
s12, the BMC sets an on-position on-board PCIE slot of the equipment to be an active on-board PCIE slot, and sets an off-position on-board PCIE slot of the equipment to be a standby on-board PCIE slot;
s13, when the PCIE switching card is in place, the BMC acquires the equipment in-place state of each PCIE switching slot through an in-place detection module, sets the PCIE switching slot with the equipment in place as an active PCIE switching slot and sets the PCIE switching slot with the equipment out of place as a standby PCIE switching slot;
s14, when the hard disk backboard is in place, the BMC acquires the in-place state of equipment of each hard disk interface through the CPLD, sets the in-place hard disk interface of the equipment as an active hard disk interface, and sets the out-of-place hard disk interface of the equipment as a standby hard disk interface;
s2, the BMC starts clocks of the PCIE slot, the PCIE switching slot and the hard disk interface of the equipment in place through the clock buffer module, and closes clocks of the PCIE slot, the PCIE switching slot and the hard disk interface of the equipment out of place; the method comprises the following specific steps:
s21, the BMC starts a clock interface corresponding to each active onboard PCIE slot through a clock buffer module and closes a clock interface corresponding to each standby onboard PCIE slot;
s22, the BMC opens a clock interface corresponding to the clock expansion channel where each active PCIE switching slot is located through a clock buffer module, and closes the clock interface corresponding to the clock expansion channel where each standby PCIE switching slot is located;
and S23, the BMC opens the clock interface corresponding to the clock expansion channel where each active hard disk interface is located through the clock buffer module, and closes the clock interface corresponding to the clock expansion channel where each standby hard disk interface is located.
Example 5:
as shown in fig. 4, the present invention provides a method for supporting automatic switching of a PCIE clock, including the following steps:
s1, the BMC acquires the equipment on-site states of each onboard PCIE slot, each PCIE switching slot and each hard disk interface through an on-site detection module and a CPLD; the method comprises the following specific steps:
s11, the BMC acquires the on-position state of each onboard PCIE slot device, the on-position state of the PCIE adapter card and the on-position state of the hard disk backboard through an on-position detection module;
s12, the BMC sets an on-position on-board PCIE slot of the equipment to be an active on-board PCIE slot, and sets an off-position on-board PCIE slot of the equipment to be a standby on-board PCIE slot;
s13, when the PCIE switching card is in place, the BMC acquires the equipment in-place state of each PCIE switching slot through an in-place detection module, sets the PCIE switching slot with the equipment in place as an active PCIE switching slot and sets the PCIE switching slot with the equipment out of place as a standby PCIE switching slot;
s14, when the hard disk backboard is in place, the BMC acquires the in-place state of equipment of each hard disk interface through the CPLD, sets the in-place hard disk interface of the equipment as an active hard disk interface, and sets the out-of-place hard disk interface of the equipment as a standby hard disk interface;
s2, the BMC starts clocks of the PCIE slot, the PCIE switching slot and the hard disk interface of the equipment in place through the clock buffer module, and closes clocks of the PCIE slot, the PCIE switching slot and the hard disk interface of the equipment out of place; the method comprises the following specific steps:
s21, the BMC starts a clock interface corresponding to each active onboard PCIE slot through a clock buffer module and closes a clock interface corresponding to each standby onboard PCIE slot;
s22, the BMC opens a clock interface corresponding to the clock expansion channel where each active PCIE switching slot is located through a clock buffer module, and closes the clock interface corresponding to the clock expansion channel where each standby PCIE switching slot is located;
s23, the BMC opens the clock interfaces corresponding to the clock expansion channels where the active hard disk interfaces are located through the clock buffer module, and closes the clock interfaces corresponding to the clock expansion channels where the standby hard disk interfaces are located;
when the first PCIE switching slot and the second hard disk interface are out of place, the BMC closes a fifth clock interface corresponding to the first clock expansion channel through the clock buffer module;
when at least one device in the first PCIE switching slot and the second hard disk interface is in place, the BMC starts a fifth clock interface corresponding to the first clock expansion channel through the clock buffer module;
when the second PCIE switching slot and the fourth hard disk interface are out of place, the BMC closes a seventh clock interface corresponding to the third clock expansion channel through the clock buffer module;
when at least one device in the second PCIE switch slot and the fourth hard disk interface is in place, the BMC starts a seventh clock interface corresponding to the third clock expansion channel through the clock buffer module.
With reference to fig. 1 and fig. 2, the NVME hard disk configuration of the hard disk interface is used to illustrate implementation steps of the present invention, and it is assumed that PCIE devices are in place in the first onboard PCIE SLOT1 and the third hard disk interface HDD3 of the hard disk backplane under the configuration.
The BMC reads the first onboard PCIE SLOT SLOT1 and the hard disk backboard in place from the in-place detection module through the first SMBUS, and judges that the current configuration is a clock expansion interface expansion NVME hard disk;
the BMC reads the in-place information of the hard disk equipment only provided with the third hard disk interface HDD3 from the CPLD of the hard disk backboard through the third SMBUS;
the BMC starts a clock of a first clock interface corresponding to the onboard first PCIE SLOT SLOT1 and a clock of an eighth clock interface corresponding to the third hard disk interface HDD3 through a register of the second SMBUS read-write clock buffer module, and closes channels of other clock interfaces.
Although the present invention has been described in detail by referring to the drawings in connection with the preferred embodiments, the present invention is not limited thereto. Various equivalent modifications or substitutions can be made on the embodiments of the present invention by those skilled in the art without departing from the spirit and scope of the present invention, and these modifications or substitutions are within the scope of the present invention/any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. A system supporting automatic switching of a PCIE clock is characterized by comprising a BMC (1), an in-place detection module (2), a clock buffer module (3), a hard disk backboard (4) and a PCIE adapter card (5);
the on-site detection module (2) is connected with a plurality of on-board PCIE slots, and the clock buffer module (3) is connected with each on-board PCIE slot;
the clock buffer module (3) is connected with a plurality of clock expansion interfaces;
a plurality of switching ports are arranged on the PCIE switching card (5), each switching port is connected with a PCIE switching slot, each PCIE switching slot and the PCIE switching card (5) are connected with the on-site detection module (2), and each switching port is connected with a clock expansion interface;
the CPLD (6) is arranged on the hard disk back plate (4), the CPLD (6) is connected with a plurality of hard disk interfaces, each hard disk interface is connected with one clock expansion interface, and the hard disk back plate (4) is also connected with the on-site detection module (2);
the BMC (1) is connected with the in-place detection module (2), the clock buffer module (3) and the CPLD (6);
the BMC (1) acquires the on-site states of the onboard PCIE slot, the PCIE switching slot and the hard disk interface through the on-site detection module (2) and the CPLD (6), and then starts the clocks of the PCIE slot, the PCIE switching slot and the hard disk interface of the on-site equipment through the clock buffer module (3) and closes the clocks of the PCIE slot, the PCIE switching slot and the hard disk interface of the off-site equipment.
2. The system of claim 1, wherein an on-board PCIE SLOT comprises a first on-board PCIE SLOT (SLOT1), a second on-board PCIE SLOT (SLOT2), a third on-board PCIE SLOT (SLOT3), and a fourth on-board PCIE SLOT (SOLT 4);
the in-place detection module (2) is provided with a first PCIE detection interface, a second PCIE detection interface, a third PCIE detection interface and a fourth PCIE detection interface;
the first PCIE detection interface is connected with a first onboard PCIE SLOT (SLOT1), the second PCIE detection interface is connected with a second onboard PCIE SLOT (SLOT2), the third PCIE detection interface is connected with a third onboard PCIE SLOT (SLOT3), and the fourth PCIE detection interface is connected with a fourth onboard PCIE SLOT (SOLT 4).
3. The system of claim 2, wherein the switch interface comprises a first switch interface (R1) and a second switch interface (R2);
the PCIE transit SLOTs include a first PCIE transit SLOT (SLOT5) and a second PCIE transit SLOT (SLOT 6);
the first adapter interface (R1) is connected with the first PCIE transfer SLOT (SLOT5), and the second adapter interface (R2) is connected with the second PCIE transfer SLOT (SLOT 6);
a fifth PCIE detection interface and a sixth PCIE detection interface are also arranged on the on-line detection module (2);
the fifth PCIE detection interface is connected with a first PCIE transfer SLOT (SLOT5), and the sixth PCIE detection interface is connected with a second PCIE transfer SLOT (SLOT 6);
the in-place detection module (2) is also provided with a PCIE switching card in-place detection interface and a hard disk backboard in-place detection interface;
the PCIE switching card in-place detection interface is connected with the PCIE switching card (5), and the hard disk backboard in-place detection interface is connected with the hard disk backboard (4).
4. The system supporting automatic switching of PCIE clocks of claim 3, wherein the hard disk interfaces comprise a first hard disk interface (HDD1), a second hard disk interface (HDD2), a third hard disk interface (HDD3), and a fourth hard disk interface (HDD 4);
the CPLD (6) is connected with the first hard disk interface (HDD1), the second hard disk interface (HDD2), the third hard disk interface (HDD3) and the fourth hard disk interface (HDD 4).
5. The system that supports automatic switching of PCIE clocks of claim 4, wherein the clock expansion interfaces comprise a first clock expansion interface (MCIO0) and a second clock expansion interface (MCIO 1);
a first clock expansion channel and a second clock expansion channel are arranged on the first clock expansion interface (MCIO 0); a third clock expansion channel and a fourth clock expansion channel are arranged on the second clock expansion interface (MCIO 1);
the clock buffer module (3) is provided with a first clock interface, a second clock interface, a third clock interface, a fourth clock interface, a fifth clock interface, a sixth clock interface, a seventh clock interface and an eighth clock interface;
the first clock interface is connected with a first onboard PCIE SLOT (SLOT1), the second clock interface is connected with a second onboard PCIE SLOT (SLOT2), the third clock interface is connected with a third onboard PCIE SLOT (SLOT3), and the fourth clock interface is connected with a fourth onboard PCIE SLOT (SOLT 4);
the fifth clock interface is connected with a first clock extension channel, and the other end of the first clock extension channel is connected with a first conversion interface (R1) and a second hard disk interface (HDD 2);
the sixth clock interface is connected with the second clock expansion channel, and the other end of the second clock expansion channel is connected with a second hard disk interface (HDD 2);
the seventh clock interface is connected with the third clock expansion channel, and the other end of the third clock expansion channel is connected with the second switching interface (R2) and the fourth hard disk interface (HDD 4);
the eighth clock interface is connected with a fourth clock expansion channel, and the other end of the fourth clock expansion channel is connected with a third hard disk interface (HDD 3).
6. The system supporting automatic switching of PCIE clocks according to claim 1, wherein the BMC (1) is connected to the in-place detection module (2) through a first SMBUS bus, the BMC (1) is connected to the clock buffer module (3) through a second SMBUS bus, and the BMC (3) is connected to the CPLD (6) through a third SMBUS bus.
7. A method for supporting automatic switching of PCIE clocks based on any one of the above claims 1-6 is characterized by comprising the following steps:
s1, the BMC acquires the equipment on-site states of each onboard PCIE slot, each PCIE switching slot and each hard disk interface through an on-site detection module and a CPLD;
and S2, the BMC starts the clocks of the PCIE slot, the PCIE switching slot and the hard disk interface of the equipment in place through the clock buffer module and closes the clocks of the PCIE slot, the PCIE switching slot and the hard disk interface of the equipment out of place.
8. The method for supporting automatic switching of PCIE clocks as claimed in claim 7, wherein the step S1 specifically includes the following steps:
s11, the BMC acquires the on-position state of each onboard PCIE slot device, the on-position state of the PCIE adapter card and the on-position state of the hard disk backboard through an on-position detection module;
s12, the BMC sets an on-position on-board PCIE slot of the equipment to be an active on-board PCIE slot, and sets an off-position on-board PCIE slot of the equipment to be a standby on-board PCIE slot;
s13, when the PCIE switching card is in place, the BMC acquires the equipment in-place state of each PCIE switching slot through an in-place detection module, sets the PCIE switching slot with the equipment in place as an active PCIE switching slot and sets the PCIE switching slot with the equipment out of place as a standby PCIE switching slot;
s14, when the hard disk backboard is in place, the BMC acquires the in-place state of equipment of each hard disk interface through the CPLD, sets the in-place hard disk interface of the equipment as an active hard disk interface, and sets the hard disk interface of the equipment which is not in place as a standby hard disk interface.
9. The method for supporting automatic switching of PCIE clocks as claimed in claim 8, wherein the step S2 specifically includes the following steps:
s21, the BMC starts a clock interface corresponding to each active onboard PCIE slot through a clock buffer module and closes a clock interface corresponding to each standby onboard PCIE slot;
s22, the BMC opens a clock interface corresponding to the clock expansion channel where each active PCIE switching slot is located through a clock buffer module, and closes the clock interface corresponding to the clock expansion channel where each standby PCIE switching slot is located;
and S23, the BMC opens the clock interface corresponding to the clock expansion channel where each active hard disk interface is located through the clock buffer module, and closes the clock interface corresponding to the clock expansion channel where each standby hard disk interface is located.
10. The method of claim 9, wherein when both the first PCIE switch slot and the second hard disk interface are out of place, the BMC closes a fifth clock interface corresponding to the first clock expansion channel through the clock buffer module;
when at least one device in the first PCIE switching slot and the second hard disk interface is in place, the BMC starts a fifth clock interface corresponding to the first clock expansion channel through the clock buffer module;
when the second PCIE switching slot and the fourth hard disk interface are out of place, the BMC closes a seventh clock interface corresponding to the third clock expansion channel through the clock buffer module;
when at least one device in the second PCIE switch slot and the fourth hard disk interface is in place, the BMC starts a seventh clock interface corresponding to the third clock expansion channel through the clock buffer module.
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| CN202110655042.9A CN113434443B (en) | 2021-06-11 | 2021-06-11 | System and method for supporting automatic switching of PCIE (peripheral component interface express) clock |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107688376A (en) * | 2017-09-28 | 2018-02-13 | 郑州云海信息技术有限公司 | A kind of hard disk backboard for supporting adaptive hard-disk interface |
| CN111966419A (en) * | 2020-09-24 | 2020-11-20 | 苏州浪潮智能科技有限公司 | Method and device for automatically distributing VPP (virtual private Point) addresses by signal conditioning equipment |
| CN112463667A (en) * | 2020-11-16 | 2021-03-09 | 苏州浪潮智能科技有限公司 | PCIE card insertion form hard disk expansion device and electronic equipment |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107688376A (en) * | 2017-09-28 | 2018-02-13 | 郑州云海信息技术有限公司 | A kind of hard disk backboard for supporting adaptive hard-disk interface |
| CN111966419A (en) * | 2020-09-24 | 2020-11-20 | 苏州浪潮智能科技有限公司 | Method and device for automatically distributing VPP (virtual private Point) addresses by signal conditioning equipment |
| CN112463667A (en) * | 2020-11-16 | 2021-03-09 | 苏州浪潮智能科技有限公司 | PCIE card insertion form hard disk expansion device and electronic equipment |
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