CN207764782U - The detecting system of peripheral component interconnection express standard slots - Google Patents
The detecting system of peripheral component interconnection express standard slots Download PDFInfo
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- CN207764782U CN207764782U CN201721718148.4U CN201721718148U CN207764782U CN 207764782 U CN207764782 U CN 207764782U CN 201721718148 U CN201721718148 U CN 201721718148U CN 207764782 U CN207764782 U CN 207764782U
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Abstract
The utility model discloses a kind of detecting system of peripheral component interconnection express standard slots, by in detection circuit board the selection of multi channel selecting chip the detection signal of PCI E slots is provided to JTAG chips or ADC by the first signal output pin second signal output pin, JTAG chips or ADC detect the connection status of the first input/output signal pin of the PCI E slots for providing detection signal according to the numerical value of detection signal, can thereby reach the technical effect for improving detection PCI E slot detection circuit boards detection coverage rate.
Description
Technical field
The utility model is related to a kind of detecting systems, refer in particular to a kind of detecting system suitable for PCI-E slots.
Background technology
Online in laptop, server production, boundary scan technique has been obtained due to the superiority that can not be substituted
It accepts extensively, essentially all of laptop, server life manufacturer are all attempting to use and promoting this technology.
Consider from point of view of practicability, is exactly using boundary scan technique, maximum application scenarios in mainboard line test
Testing host Dual Inline Memory Module or two-wire memory module (Dual In-line Memory Module, DIMM) slot
And peripheral interconnection standard (Peripheral ComponentInterconnect Express, PCI-E) slot.
Because two or more, and number of pins possessed by each slot all can be at least arranged in both slots on mainboard
Measure it is numerous, in addition to boundary scan technique, when can not ensure high coverage rate, low consumption simultaneously substantially, the test of low cost.
Using the dimm socket and PCI-E slots of boundary scan technique testing host, the test electricity of design specialized is needed
Road plate.The PCI-E slot test circuit plates of existing design are all limited for test coverage, the inspection especially on PCI-E slots
Signal is surveyed, since the electric connection mode type of PCI-E slots is various on different mainboards, this can cause PCI-E slots to test
The difficulty of circuit board testing coverage rate.
The input and output pin of PCI-E slots electric connection situation common on mainboard is, for example,：It is electrically connected pull-up
Resistance, the system for being electrically connected pull down resistor, being electrically connected power supply signal, being electrically connected ground signalling, be electrically connected to mainboard
Programmable array logic chip, PCI-E slots input and output pin have electric connection or hanging each other.
For input and output pin in the existing JTAG chips for being usually used in test circuit plate under boundary scan pattern, only in
In the encapsulation of JTAG chips and preset corresponding with each input and output pin of JTAG chips has pull-up resistor, and pull-up resistor
What formula can not be removed, for the detection signal testing of PCI-E slots, all by the mode that is electrically connected on different mainboards
Difference will be unable to simply be designed test circuit plate.
In summary, it is known that offer detection PCI-E slot detection circuit boards are be provided for a long time in the prior art and are set
Meter causes to detect the bad problem of coverage rate there are still missing, it is therefore necessary to propose improved technological means, be asked to solve this
Topic.
Utility model content
There is the design of offer detection PCI-E slot detection circuit boards in view of the prior art, there are still missings, and detection to be caused to be covered
The bad problem of lid rate, the utility model disclose a kind of detecting system of peripheral component interconnection express standard slots then, wherein：
The detecting system of peripheral component interconnection express standard slots disclosed by the utility model, it includes：Mainboard and at least
One test circuit plate, mainboard further include：Multiple peripheral interconnection standard (Peripheral ComponentInterconnect
Express, PCI-E) slot；Test circuit plate is inserted in one of PCI-E slots and is detected respectively, test circuit plate
It further includes：Multi channel selecting chip, joint test working group (Joint Test Action Group, JTAG) chip and simulation number
Word converter (Analogtodigital converter, ADC).
Each PCI-E slot of mainboard has multiple input output signal pin.
At least the one of the PCI-E slots that an at least signal input pin for the multi channel selecting chip of test circuit plate plugs certainly
First input/output signal pin receives detection signal.
The control signal of the multi channel selecting chip of test circuit plate receives pin and receives control signal, multi channel selecting chip according to
According to control signal control the signal input pin of multi channel selecting chip by the first signal output pin of multi channel selecting chip or
It is that second signal output pin provides detection signal.
The JTAG signal of the JTAG chips of test circuit plate receives pin and receives control signal and control signal sequence, with
JTAG chips are set as boundary scan (Boundary Scan) pattern according to control signal sequence.
First input and output pin of the JTAG chips of test circuit plate and the first signal output of multi channel selecting chip are drawn
Foot is electrically connected to receive detection signal, and the of the PCI-E slots for providing detection signal is detected by detecting the numerical value of signal
The connection status of one input/output signal pin.
The JTAG chips of test circuit plate receive what pin was electrically connected by the control signal with multi channel selecting chip
Second input and output pin of JTAG chips provides control signal to multi channel selecting chip.
The JTAG chips of test circuit plate generate IC bus according to continual control signal sequence
(Inter-Integrated Circuit, IIC) emulates signal and passes through third input and output pin and the 4th input and output
Pin provides IIC and emulates signal.
The signal of the ADC of test circuit plate receives pin and passes through the resistance R bleeder circuits constituted and multi channel selecting chip
Second signal output pin is electrically connected to receive detection signal and be converted to the detection signal of number, by the inspection for reading number
The numerical value of signal is surveyed to detect the connection status of the first input/output signal pin of the PCI-E slots for providing detection signal.
The third signal of the ADC of test circuit plate receives pin and fourth signal receive pin respectively with JTAG chips
Third input and output pin and the 4th input and output pin be electrically connected with receive IIC emulate signal.
System disclosed by the utility model is as above, and the difference between the prior art is by detection circuit board
The detection signal of PCI-E slots is passed through the first signal output pin or second signal output pin by the selection of multi channel selecting chip
It is provided to JTAG chips or ADC, JTAG chips or ADC provide detection signal according to the numerical value of detection signal to detect
The connection status of first input/output signal pin of PCI-E slots.
By above-mentioned technological means, the utility model can reach raising detection PCI-E slot detection circuit boards detection
The technical effect of coverage rate.
Description of the drawings
Fig. 1 is the system architecture schematic diagram of the detecting system of the utility model PCI-E slots.
Fig. 2 is the test circuit plate component diagram of the detecting system of the utility model PCI-E slots.
Symbol description：
10 mainboards
11 PCI-E slots
111 first input/output signal pins
12 system programmable array logic chips
13 PCH
14 CPU
20 test circuit plates
21 multi channel selecting chips
211 signal input pins
212 control signals receive pin
213 first signal output pins
214 second signal output pins
22 JTAG chips
221 JTAG signals receive pin
222 first input and output pins
223 second input and output pins
224 third input and output pins
225 the 4th input and output pins
23 ADC
231 signals receive pin
232 third signals receive pin
233 fourth signals receive pin
31 detection signals
32 control signal sequences
33 IIC emulate signal
34 control signals
R resistance
Specific implementation mode
The embodiment of the utility model is described in detail below in conjunction with accompanying drawings and embodiments, thereby to the utility model
How applied technology method solves technical problem and reaches the realization process of technical effect to fully understand and implement.
It will illustrate the operation system of the utility model embodiment with one embodiment below, and please also refer to Fig. 1
And shown in Fig. 2, Fig. 1 is the system architecture schematic diagram of the detecting system of the utility model PCI-E slots；Fig. 2 is schematically shown as this reality
With the test circuit plate component diagram of the detecting system of novel PCI-E slots.
The detecting system of peripheral component interconnection express standard slots disclosed by the utility model, it includes：Mainboard 10 and extremely
A few test circuit plate 20, mainboard 10 also include：Multiple peripheral interconnection standard (Peripheral
ComponentInterconnect Express, PCI-E) slot 11, system programmable array logic (System
Programmable Array Logic, SYSPAL) chip 12, platform path controller (Platform Controller
Hub, PCH) 13 and central processing unit (Central Processing Unit, CPU) 14；Test circuit plate 20 plugs respectively
In PCI-E slots 11, one of them is detected, and test circuit plate 20 also includes：Multi channel selecting chip 21, joint test work
Group (Joint Test Action Group, JTAG) chip 22 and analog-digital converter (Analogtodigital
Converter, ADC) 23.
Each PCI-E slot 11 of mainboard 10 has multiple input output signal pin, input/output signal pin example
In this way：Number B5 and B6 are in the JTAG pins of number A5, A6, A7, A8 and B9, PCI-E slots in PCI-E slots
Number B12, A19 in reason bus (System Management Bus, SMBUS) pin under the overall leadership, PCI-E slots, B30, A32,
In reservation (Reserved) pin of A33, A50 and B82, PCI-E slots number A1, A11, B11, B17, B31, B48 with
And the Kong Hold-those input and output pins of B81, the input/output signal pin of PCI-E slots 11 make to receive and transmit signal
With above-mentioned input/output signal pin can be the first input/output signal pin 111, the input on PCI-E slots 11
Output signal pin 111 on mainboard 10 may with pull-up resistor (Pull-up resistor) or directly with power supply signal electricity
Property connection, the input/output signal pin 111 on PCI-E slots 11 may also be with pull down resistor (Pull-down on mainboard 10
Resistor it) or is directly electrically connected with ground signalling, the input/output signal pin 111 on PCI-E slots 11 is in mainboard
It can also be electrically connected with system programmable array logic chip 12, PCH 13 or CPU 14 on 10, be only for example herein
It is bright, the application range of the present invention is not limited to this.
At least the one first of the PCI-E slots 11 that at least a signal input pin 211 plugs certainly of multi channel selecting chip 21
Input/output signal pin 111 receives detection signal 31, and above-mentioned multi channel selecting chip 21 is, for example, to use 74CBTLV3257 models
Chip do not limit to the application range of the utility model herein by way of example only with this.
The control signal of multi channel selecting chip 21 receives second input and output pin 223 of the pin 212 from JTAG chips 22
Continual reception controls signal 34, and multi channel selecting chip 21 can control multi channel selecting chip 21 according to control signal 34
The first signal output pin 213 or second signal output pin that pass through multi channel selecting chip 21 of signal input pin 211
214 provide detection signal 31.
It is constant from external control device (not being painted in schema) that the JTAG signal of JTAG chips 22 receives pin 221
Reception control signal sequence 32, above-mentioned JTAG chips 22 be, for example, Lattice or Altera complexity can programmed logic
Device (Complex Programmable Logic Device, CPLD) chip, JTAG chips 22 are to use in embodiment
The chip of LCMXO640C models, herein by way of example only it, the application range of the utility model, JTAG are not limited to this
It is boundary scan (Boundary Scan) pattern that chip 22 can set JTAG chips 22 according to control signal sequence 32,
Each input and output pin of JTAG chips 22 encapsulates when JTAG chips 22 are set in boundary scan pattern in JTAG chips 22
It is interior and corresponding with each input and output pin of JTAG chips 22 default with pull-up resistor.
First signal output pin 213 of the first input and output pin 222 and multi channel selecting chip 21 of JTAG chips 22
It is electrically connected to receive detection signal 31, the detection signal 31 of the first input and output pin 222 by reading JTAG chips 22
Numerical value is to detect the connection status of the first input/output signal pin 111 of the PCI-E slots 11 for providing detection signal 31.
JTAG chips 22 by it is continual control signal sequence 32 corresponding to boundary scan cell push value with
IC bus (Inter-Integrated Circuit, IIC) is generated to emulate signal 33 and by third input and output draw
Foot 224 and the 4th input and output pin 225 provide IIC and emulate signal 33 to ADC23, so that ADC 23 can be worked normally.
The signal of ADC 23 receives the bleeder circuit and the second of multi channel selecting chip 21 that pin 231 is made up of resistance R
Signal output pin 214 is electrically connected to receive detection signal 31 and be converted to the detection signal 31 of number, by reading number
31 numerical value of detection signal to detect the first input/output signal pin 111 of the PCI-E slots 11 for providing detection signal 31
Connection status, above-mentioned ADC 23 are, for example, the chip using MAX1039 models, and above-mentioned bleeder circuit is, for example, using 6K electricity
The resistance of resistance value and 2K resistance values, herein by way of example only it, the application range of the utility model is not limited to this, lead to
It is that the signal value of detection signal 31 is allow to be read by ADC 23 to cross using bleeder circuit, that is, detects signal 31 by dividing electricity
Road may make the signal value of detection signal 31 to meet the read range of ADC 23.
The third signal of ADC 23 receives pin 232 and fourth signal receive pin 233 respectively with JTAG chips 22
Third input and output pin 224 and the 4th input and output pin 225 are electrically connected emulates signal 33 to receive IIC, uses drive
Dynamic ADC 23.
On actually detected, the first input/output signal pin 111 of PCI-E slots 11 in mainboard 10 and pull-up resistor or
It is the case where directly electric connection with power supply signal, multi channel selecting chip 21 can control multi channel selecting core according to control signal 34
The signal input pin 211 of piece 21 by the second signal output pin 214 of multi channel selecting chip 21 provide detection signal 31 to
ADC23, when ADC23 signal receive pin 231 read detection signal 31 signal value be 0 (actual state when detection believe
Numbers 31 signal value between 0 to 100mV when, when the signal value that can be all judged as detection signal 31 is 0, that is, indicate that PCI-E is inserted
First input/output signal pin 111 of slot 11 generates breaking (open) failure, otherwise when the signal of ADC 23 receives pin
When 231 signal values for reading detection signal 31 meet desired value, that is, indicate the first input and output letter of PCI-E slots 11
Number pin 111 does not generate open circuit fault.
On actually detected, the first input/output signal pin 111 of PCI-E slots 11 in mainboard 10 and pull down resistor or
It is the case where directly electric connection with ground signalling, multi channel selecting chip 21 can control multi channel selecting core according to control signal 34
The signal input pin 211 of piece 21 by the first signal output pin 213 of multi channel selecting chip 21 provide detection signal 31 to
JTAG chips 22, when the signal value that the first input and output pin 222 of JTAG chips 22 reads detection signal 31 is 0,
Indicate that the first input/output signal pin 111 of PCI-E slots 11 does not generate open circuit fault, otherwise when JTAG chips 22
When the signal value that first input and output pin 222 reads detection signal 31 is 1, that is, indicate that the first of PCI-E slots 11 is defeated
Enter output signal pin 111 and generates open circuit fault.
On actually detected, multi channel selecting chip 21 controls each of multi channel selecting chip 21 according to control signal 34
Signal input pin 211 provides detection signal 31 to JTAG cores by the first signal output pin 213 of multi channel selecting chip 21
Piece 22, JTAG chips 22 can detect each signal 31 by boundary scan interconnecting test method to detect PCI-E slots
Whether 11 the first input/output signal pin 111 has the short trouble being connected with each other or open fault feelings each other
Condition, no matter that is, the first input/output signal pin 111 of PCI-E slots 11 is in mainboard 10 and system programmable array logic
Chip 12, PCH13 CPU14 be electrically connected, be directly electrically connected with power supply signal with pull-up resistor or with drop-down
Resistance is directly electrically connected the detection that can all carry out short trouble or open fault with ground signalling.
In summary, it is known that the difference between the utility model and the prior art is through the multichannel in detection circuit board
Gating chip selection provides the detection signal of PCI-E slots by the first signal output pin or second signal output pin
To JTAG chips or ADC, JTAG chips or ADC provide the PCI-E for detecting signal according to the numerical value of detection signal to detect
The connection status of first input/output signal pin of slot.
It can be designed to solve to provide detection PCI-E slot detection circuit boards present in the prior art by this technological means
There are still missings to cause to detect the bad problem of coverage rate, and then reaches raising detection PCI-E slot detection circuit boards detection and cover
The technical effect of lid rate.
Although the embodiment disclosed by the utility model is as above, only the content is not directly to limit this practicality
Novel scope of patent protection.Those skilled in the art in any the utility model technical field, are not departing from this reality
Under the premise of with novel disclosed spirit and scope, a little change can be made in the formal and details of implementation.This reality
With novel scope of patent protection, still should be subject to the scope of the claims as defined in the appended claims.
Claims (4)
1. a kind of detecting system of peripheral component interconnection express standard slots, which is characterized in that it includes：
Mainboard, the mainboard also include：
Multiple PCI-E slots, each PCI-E slot have multiple input output signal pin；
And
An at least test circuit plate, the test circuit plate are inserted in one of described PCI-E slots and are detected respectively, institute
Stating test circuit plate also includes：
Multi channel selecting chip, at least signal input pin of the multi channel selecting chip is from the PCI-E slots plugged
At least one first input/output signal pin receives detection signal；The control signal of the multi channel selecting chip receives pin and receives
Signal is controlled, the signal input that the multi channel selecting chip controls the multi channel selecting chip according to the control signal is drawn
Foot provides the detection signal by the first signal output pin or second signal output pin of the multi channel selecting chip；
JTAG chips, the JTAG signal of the JTAG chips receive pin and receive the control signal and control signal sequence,
To set the JTAG chips as boundary scan pattern according to the control signal sequence；First input of the JTAG chips is defeated
First signal output pin for going out pin and the multi channel selecting chip is electrically connected to receive the detection signal, is passed through
The numerical value of the detection signal is to detect first input/output signal for the PCI-E slots for providing the detection signal
The connection status of pin；The JTAG chips are electrically connected by receiving pin with the control signal of the multi channel selecting chip
Second input and output pin of the JTAG chips connect provides the control signal to the multi channel selecting chip；The JTAG
Chip according to the continual control signal sequence generates IIC emulation signals and by third input and output pin and the
Four input and output pins provide the IIC and emulate signal；And
The signal of ADC, the ADC receive pin and pass through described in the resistance R bleeder circuits constituted and the multi channel selecting chip
Second signal output pin is electrically connected to receive the detection signal and be converted to the detection signal of number, passes through reading
The numerical value of the detection signal of number is defeated with first input for detecting the PCI-E slots for providing the detection signal
Go out the connection status of signal pins；The third signal of the ADC receives pin and a fourth signal receive pin respectively with institute
The third input and output pin and the 4th input and output pin for stating JTAG chips are electrically connected to receive the IIC
Emulate signal.
2. the detecting system of peripheral component interconnection express standard slots as described in claim 1, which is characterized in that the PCI-E is inserted
The first input/output signal pin of slot transmits the control from the signal input pin of the multi channel selecting chip
Signal sequence.
3. the detecting system of peripheral component interconnection express standard slots as described in claim 1, which is characterized in that the mainboard also wraps
Chip containing SYSPAL, PCH and CPU, pull-up resistor, pull down resistor, power supply signal and ground signalling, the PCI-E slots
The input/output signal pin and pull-up resistor or power supply signal be electrically connected, the input of the PCI-E slots
Output signal pin is electrically connected with pull down resistor ground signalling or the input/output signal of the PCI-E slots
Pin is electrically connected with the system programmable array logic chip, PCH or CPU.
4. the detecting system of peripheral component interconnection express standard slots as described in claim 1, which is characterized in that the JTAG chips
Each input and output pin when the JTAG chips are set in boundary scan pattern in the JTAG chip packages give tacit consent to tool
There is pull-up resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721718148.4U CN207764782U (en) | 2017-12-09 | 2017-12-09 | The detecting system of peripheral component interconnection express standard slots |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721718148.4U CN207764782U (en) | 2017-12-09 | 2017-12-09 | The detecting system of peripheral component interconnection express standard slots |
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| CN207764782U true CN207764782U (en) | 2018-08-24 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109901958A (en) * | 2017-12-09 | 2019-06-18 | 英业达科技有限公司 | The detection system and its method of peripheral component interconnection express standard slots |
| CN111693754A (en) * | 2019-12-31 | 2020-09-22 | 重庆芯讯通无线科技有限公司 | Communication module PIN voltage detection device, equipment and method |
| CN111736094A (en) * | 2020-07-23 | 2020-10-02 | 深圳市微特自动化设备有限公司 | PCI-E test card |
-
2017
- 2017-12-09 CN CN201721718148.4U patent/CN207764782U/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109901958A (en) * | 2017-12-09 | 2019-06-18 | 英业达科技有限公司 | The detection system and its method of peripheral component interconnection express standard slots |
| CN109901958B (en) * | 2017-12-09 | 2024-02-20 | 英业达科技有限公司 | System and method for detecting standard slot of shortcut peripheral interconnection |
| CN111693754A (en) * | 2019-12-31 | 2020-09-22 | 重庆芯讯通无线科技有限公司 | Communication module PIN voltage detection device, equipment and method |
| CN111693754B (en) * | 2019-12-31 | 2023-11-17 | 重庆芯讯通无线科技有限公司 | Device, equipment and method for detecting PIN voltage of communication module |
| CN111736094A (en) * | 2020-07-23 | 2020-10-02 | 深圳市微特自动化设备有限公司 | PCI-E test card |
| CN111736094B (en) * | 2020-07-23 | 2021-05-25 | 深圳市微特精密科技股份有限公司 | PCI-E test card |
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