CN113806148B - Quick peripheral component interconnect socket detection system - Google Patents
Quick peripheral component interconnect socket detection system Download PDFInfo
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- CN113806148B CN113806148B CN202010549763.7A CN202010549763A CN113806148B CN 113806148 B CN113806148 B CN 113806148B CN 202010549763 A CN202010549763 A CN 202010549763A CN 113806148 B CN113806148 B CN 113806148B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test input/output devices or peripheral units
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
A PCI express slot detection system, a PCI express control chip transmits detection signals from a PCI express interface to detect the PCI express slot and generate first detection result information, the PCI express slot transmits the first detection result information to a detection program, a detection logic control chip transmits detection signals from the PCI express interface to detect and control according to the detection signals and perform detection logic setting to detect the PCI express slot and generate second detection result information, and the PCI express slot transmits the second detection result information to the detection program, thereby achieving the technical efficacy of respectively detecting the pins of the PCI express slot.
Description
Technical Field
The present invention relates to a testing system, and more particularly, to a testing system for providing a PCI express slot for testing each pin.
Background
The current PCI express slot detection is usually implemented by using a standard PCI express network card, and the standard PCI express network card detection can only detect basic power supply characteristics and connection states of the standard PCI express slot, so that each corner of the standard PCI express slot cannot be separately detected in detail, and the function of assisting in pin detection is not provided, and the existing detection coverage rate of the standard PCI express slot is low.
In view of the foregoing, it is known that there is a long-felt need in the art for providing an improved technique for detecting the positions of the pins of the standard PCI express slot.
Disclosure of Invention
In view of the problem that the conventional standard PCI express slot detection cannot provide the detection of each pin, the present invention discloses a PCI express slot detection system, wherein:
the PCI express slot detection system according to the first embodiment of the present invention comprises: motherboard and detection circuit board, detection circuit board still contains: the PCI express control chip and the detection logic control chip.
The motherboard is provided with a central processing unit, a memory and a peripheral component interconnect express (Peripheral Component Interconnect Express, PCIe) slot, wherein a detection program is stored in the memory, the central processing unit loads and executes the detection program from the memory to generate a detection signal, and the detection program transmits the detection signal, the first detection result information and the second detection result information through the PCI slot.
The detection circuit board is inserted into the PCI express slot through the PCI express interface, the PCI express control chip of the detection circuit board and the PCI express interface are directly and electrically connected with the switch, the detection signal is transmitted from the PCI express interface to detect the PCI express slot and generate the first detection result information, and the first detection result information is transmitted to the detection program through the PCI express slot; and the detection logic control chip of the detection circuit board is directly electrically connected with the quick peripheral component interconnection interface through the switch, the detection logic control chip is directly electrically connected with the quick peripheral component interconnection control chip through the switch, detection signals are transmitted from the quick peripheral component interconnection interface to carry out detection control according to the detection signals and carry out detection logic setting to detect the quick peripheral component interconnection slot and generate second detection result information, and the second detection result information is transmitted to the detection program through the quick peripheral component interconnection slot.
The PCI express slot detection system according to the second embodiment of the present invention comprises: motherboard, detection circuit board and detection device, detection circuit board still contains: the system comprises a PCI express control chip, a detection logic control chip, a first UART-to-RS-232 interface chip, a second UART-to-RS-232 interface chip, a PCI express packet switch (PCIe switch) connector and a detection logic connection connector.
The main board is provided with a quick peripheral component interconnection slot, the detection circuit board is inserted into the quick peripheral component interconnection slot through a quick peripheral component interconnection interface, a quick peripheral component interconnection control chip of the detection circuit board and the quick peripheral component interconnection interface are directly and electrically connected with each other through a switch, and detection signals are received to detect the quick peripheral component interconnection slot and generate first detection result information; the detection logic control chip of the detection circuit board is directly electrically connected with the quick peripheral component interconnection interface through the switch, the detection logic control chip is directly electrically connected with the quick peripheral component interconnection control chip through the switch, and detection signals are received to carry out detection control according to the detection signals and detection logic setting to detect the quick peripheral component interconnection slot and generate second detection result information; the fast peripheral component interconnect packet switching connector and the fast peripheral component interconnect control chip of the detection circuit board are directly electrically connected with the first UART-to-RS-232 interface chip, the fast peripheral component interconnect packet switching connector transmits detection signals to the fast peripheral component interconnect control chip, and the fast peripheral component interconnect packet switching connector transmits first detection result information; and the detection logic connection connector of the detection circuit board is electrically connected with the detection logic control chip through the second UART-RS-232 interface chip, the detection logic connection connector transmits detection signals to the detection logic control chip, and the detection logic connection connector transmits second detection result information.
The detection device is used for executing a detection program to generate detection signals, the detection device is electrically connected with the PCI express packet switching connector and the detection logic connection connector respectively, the detection program transmits the detection signals through the PCI express packet switching connector and the detection logic connection connector respectively, the detection program transmits first detection result information through the PCI express packet switching connector, and the detection program transmits second detection result information through the detection logic connection connector.
The difference between the system disclosed in the present invention and the prior art is that the PCI express control chip transmits the inspection signal from the PCI express interface to inspect the PCI express slot and generate the first inspection result information, the PCI express slot transmits the first inspection result information to the inspection program, the inspection logic control chip transmits the inspection signal from the PCI express interface to inspect and control according to the inspection signal and perform the inspection logic setting to inspect the PCI express slot and generate the second inspection result information, and the PCI express slot transmits the second inspection result information to the inspection program.
By the technical means, the invention can achieve the technical effect of respectively detecting the pins of the PCI express slot.
Drawings
FIG. 1 is a system block diagram of a PCI express slot detection system according to a first embodiment of the present invention.
FIG. 2 is a system block diagram of a PCI express slot detection system according to a second embodiment of the present invention.
FIG. 3 is a schematic diagram illustrating power pin detection for PCI express slot detection according to the present invention.
FIG. 4A is a schematic diagram of a PCI express slot test system management bus Master mode test according to the present invention.
FIG. 4B is a schematic diagram illustrating a SMBUS Slave mode detection scheme for PCI express slot detection according to the present invention.
FIG. 5 is a diagram illustrating a wake-up detection scheme for PCI express slot detection according to the present invention.
FIG. 6 is a schematic diagram of an IO inspection model for PCI express socket inspection according to the present invention.
Symbol description
10 motherboard
11 CPU
12 memory
13 PCI express slot
20 detection Circuit Board
21 PCI express control chip
22 detection logic control chip
221 first detection logic control chip
222 second detection logic control chip
23 PCI express interface
24 switch
25 read-only memory
EJTAG interface
JLINK interface 27
28 quartz oscillator
29 clock generator
31 first UART-RS-232 interface chip
32 second UART-RS-232 interface chip
33 PCI express packet switch connector
Detecting a logical connection connector 34
Detailed Description
The following detailed description of embodiments of the present invention will be given with reference to the accompanying drawings and examples, so that the implementation process of how the present invention can be applied to solve the technical problems and achieve the technical effects can be fully understood and implemented.
In the following, a first embodiment of the pci express slot inspection system according to the present invention will be described, and referring to fig. 1, fig. 1 is a system block diagram of the pci express slot inspection system according to the first embodiment of the present invention.
The PCI express slot detection system according to the first embodiment of the present invention comprises: motherboard 10 and detection circuit board 20, detection circuit board 20 still includes: the PCI express control chip 21 and the detection logic control chip 22.
The motherboard 10 has a central processing unit 11, a memory 12, and a peripheral component interconnect express (Peripheral Component Interconnect Express, PCIe) slot 13, a test program is stored in the memory 12, and the central processing unit 11 loads and executes the test program from the memory 12 to generate a test signal.
The detection circuit board 20 is inserted into the PCI express slot 13 through the PCI express interface 23, the PCI express control chip 21 and the PCI express interface 23 of the detection circuit board 20 are directly electrically connected with the switch 24, the detection logic control chip 22 and the PCI express interface 23 of the detection circuit board 20 are directly electrically connected with the switch 24, and the detection logic control chip 22 and the PCI express control chip 21 are directly electrically connected with the switch 24.
In addition, the detection circuit board 20 further includes: read-Only Memory (ROM) 25, EJTAG interface 26, JLINK interface 27, and quartz oscillator (crystal) 28.
The read-only memory 25 is electrically connected to the PCI express control chip 22, the EJTAG interface 26 is electrically connected to the PCI express control chip 22, the JLINK interface 27 is electrically connected to the detection logic control chip 24, the quartz oscillator 28 is electrically connected to the PCI express control chip 22 by a Clock generator (Clock) 29, and the quartz oscillator 28 is electrically connected to the detection logic control chip 24.
The inspection program can transmit inspection signals to the PCI express control chip 21 through the PCI express slot 13, the PCI express control chip 21 inspects the PCI express slot 13 according to the inspection signals and generates first inspection result information, and the PCI express control chip 21 transmits the first inspection result information to the inspection program through the PCI express slot 13.
The inspection program can transmit the inspection signal to the inspection logic control chip 22 through the PCI express slot 13, the inspection logic control chip 22 performs inspection control according to the inspection signal and performs inspection logic setting to inspect the PCI express slot 13 and generate second inspection result information, and the inspection logic control chip 22 transmits the second inspection result information to the inspection program through the PCI express slot 13.
Notably, the PCI express slot 13 detection includes power pin detection, PCIe transmission speed detection, PCIe transmission bandwidth detection, PCIe transmission speed switch detection, system management bus (System Management Bus, SMBus) detection, WAKE (WAKE) detection, JTAG detection, PWRBRK detection, and CLKREQ detection.
Next, the following description describes a pci express socket inspection system according to a second embodiment of the present invention, and referring to fig. 2, fig. 2 is a system block diagram of a pci express socket inspection system according to a second embodiment of the present invention.
The PCI express slot detection system according to the second embodiment of the present invention comprises: motherboard 10, detection circuit board 20 and detection device 40, detection circuit board 20 still contains: the PCI express control chip 21, the detection logic control chip 22, the first UART-RS-232 interface chip 31, the second UART-RS-232 interface chip 32, the PCI express packet switch connector 33 and the detection logic connection connector 34.
The detection circuit board 20 is inserted into the PCI slot 13 through the PCI express 23, the PCI express 21 and the PCI express 23 of the detection circuit board 20 are directly electrically connected with the switch 24, the detection logic 22 and the PCI express 21 are directly electrically connected with the switch 24, the PCI express switch connector 33 and the PCI express 21 of the detection circuit board 20 are directly electrically connected with the first UART-232 interface chip 31, and the detection logic 34 and the detection logic 22 of the detection circuit board 20 are electrically connected with the second UART-232 interface chip 32.
In addition, the detection circuit board 20 further includes: read only memory 25, EJTAG interface 26, JLINK interface 27, quartz oscillator 28.
The read-only memory 25 is electrically connected to the PCI express control chip 22, the EJTAG interface 26 is electrically connected to the PCI express control chip 22, the JLINK interface 27 is electrically connected to the detection logic control chip 24, the quartz oscillator 28 is electrically connected to the PCI express control chip 22 by a Clock generator (Clock) 29, and the quartz oscillator 28 is electrically connected to the detection logic control chip 24.
The detecting device 30 executes a detecting program to generate a detecting signal, the detecting device 30 is electrically connected with the PCI express packet switching connector 33 and the detecting logic connector 34 respectively, the detecting program transmits the detecting signal to the PCI express control chip 21 through the PCI express packet switching connector 33 in a UART transmission mode, the PCI express control chip 21 detects the PCI express slot 13 according to the detecting signal and generates a first detecting result information, and the PCI express control chip 21 transmits the first detecting result information through the PCI express packet switching connector 33.
The detection program transmits a detection signal to the detection logic control chip 22 through the detection logic connection connector 34 in a UART transmission mode, the detection logic control chip 22 performs detection control according to the detection signal and performs detection logic setting to detect the PCI express slot 13 and generate second detection result information, and the detection logic control chip 22 transmits the second detection result information to the detection program through the detection logic connection connector 34.
Notably, the PCI express slot 13 detection includes power pin detection, PCIe transmission speed detection, PCIe transmission bandwidth detection, PCIe transmission speed switch detection, system management bus (System Management Bus, SMBus) detection, WAKE (WAKE) detection, JTAG detection, PWRBRK detection, and CLKREQ detection.
Referring to fig. 3, fig. 3 is a schematic diagram illustrating power pin detection for PCI express slot detection according to the present invention.
When the detection signal received by the detection logic control chip 22 is power pin detection, the detection logic control chip 22 will measure the voltages of the power pins of the PCI express slot 13 to generate second detection result information, the detection program will determine whether the voltages measured by the power pins in the second detection result information conform to the voltage range specified by PCIe, and the detection program will detect whether the power pins of the PCI express slot 13 are powered normally.
When the detection signal received by the detection logic control chip 22 is power pin detection, the detection logic control chip 22 will measure the voltages of the power pins of the PCI express slot 13 to generate second detection result information, the detection program will determine whether the voltages measured by the power pins in the second detection result information conform to the voltage range specified by PCIe, and the detection program will detect whether the power pins of the PCI express slot 13 are powered normally.
The PCI express control chip 21 detects and stores the PCIe transmission speed and the PCIe transmission bandwidth in the register when the detection circuit board 20 is plugged into the PCI express slot 13 through the PCI express interface 21, the detection logic control chip 22 obtains the PCIe transmission speed and the PCIe transmission bandwidth from the register to generate a second detection result, the PCI express control chip 21 controls switching of the PCIe transmission speed according to the detection signal, and generates the connection state of PCIe after the switching of the PCIe transmission speed as a first detection result, and a detection program can detect whether the PCIe transmission speed, the PCIe transmission bandwidth and the PCIe transmission speed switching of the PCI express slot 13 are consistent with the specification of PCIe.
Referring to fig. 4A and fig. 4B, fig. 4A is a schematic diagram illustrating a system management bus Master mode detection of the pci express slot detection according to the present invention; FIG. 4B is a schematic diagram illustrating a SMBUS Slave mode detection scheme for PCI express slot detection according to the present invention.
In the Master mode detection of the system management bus, the detection logic control chip 22 is set to an I2C Master detection state according to the detection signal, the detection logic control chip 22 obtains the address of the I2C device on the motherboard 10, the detection logic control chip 22 reads or writes the I2C address space, and the detection program determines the availability of the SMBus according to the success or failure of the I2C address space.
In the Slave mode detection of the system management bus, the first embodiment is applicable only to the case where the detection program accesses the baseboard management controller (Baseboard Management Controller, BMC) of the motherboard or the SMBus controller on the ICH, and the SMBus controller accesses the EEPROM simulated by the detection logic control chip 22 to verify the availability of the SMBus bus by reading and writing the EEPROM.
Referring to fig. 5, fig. 5 is a schematic diagram illustrating wake-up detection of the pci express slot detection according to the present invention.
The wake-up detection includes an IO mode and a Function mode, and the Function mode is adapted in a scene that the motherboard 10 reads the wake-up state through the BMC, or that the motherboard 10 has more than one PCIe slot, and wake-up among the PCIe slots are connected together, the first detection logic control chip 221 sends out a wake-up signal, the BMC of the motherboard 10 reads the wake-up state, or the second detection logic control chip 222 sends out a wake-up signal, and the BMC of the motherboard 10 reads the wake-up state, or the first detection logic control chip 221 reads the wake-up state for detection.
Referring to fig. 6, fig. 6 is a schematic diagram of an IO test model for testing a pci express slot according to the present invention.
The signals JTAG including TMS, TDI, TDO and TCK, JTAG, PWRBRRK and CLKREQ all adopt IO detection model, and the IO detection model is shown in FIG. 6, namely, any detected pin is referred to, when the IO of the detection logic control chip 22 is connected to the pin, the detection logic control chip 22 can control two resistors connected to the pin to be respectively set as pull-up resistor and pull-down resistor. The detection logic control chip 22 can determine that the detected pin is in the H/L/NC state by controlling the pull-up state, the pull-down state, and the no pull-up state while reading the state signal of IO.
In summary, the difference between the present invention and the prior art is that the PCI express control chip transmits the inspection signal from the PCI express interface to inspect the PCI express slot and generate the first inspection result information, the PCI express slot transmits the first inspection result information to the inspection program, the inspection logic control chip transmits the inspection signal from the PCI express interface to inspect and control according to the inspection signal and perform the inspection logic setting to inspect the PCI express slot and generate the second inspection result information, and the PCI express slot transmits the second inspection result information to the inspection program.
The technical means can solve the problem that the prior art can not provide detection of each pin position for the detection of the standard PCI express slot, thereby achieving the technical effect of the respective detection of the PCI express slot pins.
Although the embodiments of the present invention are described above, the disclosure is not intended to limit the scope of the present invention. Workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention. The scope of the invention is to be defined only by the appended claims.
Claims (10)
1. A PCI express slot inspection system, comprising:
a motherboard having a central processing unit (cpu), a memory, and a peripheral component interconnect express (PCIe) slot, wherein a test program is stored in the memory, the cpu loads and executes the test program from the memory to generate a test signal, and the test program transmits the test signal, first test result information, and second test result information through the PCIe slot;
the detection circuit board is inserted into the quick peripheral component interconnection slot through the quick peripheral component interconnection interface, and the detection circuit board further comprises:
the PCI express control chip and the PCI express interface are directly and electrically connected with each other through a switch, the detection signals are transmitted from the PCI express interface to detect the PCI express slot and generate the first detection result information, and the first detection result information is transmitted to the detection program through the PCI express slot; a kind of electronic device with high-pressure air-conditioning system
The detection logic control chip and the rapid peripheral component interconnection interface are directly electrically connected with the switch, the detection logic control chip and the rapid peripheral component interconnection control chip are directly electrically connected with the switch, the detection signals are transmitted from the rapid peripheral component interconnection interface to carry out detection control according to the detection signals, detection logic setting is carried out to detect the rapid peripheral component interconnection slot and generate second detection result information, and the second detection result information is transmitted to the detection program through the rapid peripheral component interconnection slot.
2. The PCI express slot detection system of claim 1, wherein detecting the PCI express slot comprises power pin detection, PCIe transmission speed detection, PCIe transmission bandwidth detection, PCIe transmission speed switch detection, system management bus detection, wake detection, JTAG detection, PWRRK detection, and CLKREQ detection.
3. The PCI express slot detection system of claim 1 wherein the PCI express control chip detects and stores PCIe transmission speed and PCIe transmission bandwidth in a register when the detection circuit board is plugged into the PCI express slot through the PCI express interface, and the detection logic control chip obtains PCIe transmission speed and PCIe transmission bandwidth from the register to generate the second detection result.
4. The PCI express slot test system of claim 1, wherein the PCI express control chip controls switching of PCIe transmission speed according to the test signal and generates a PCIe connection state after switching of PCIe transmission speed as the first test result.
5. The PCI express slot test system of claim 1 wherein the test logic control chip electrically connects the I/O pins of the test logic control chip with the pin configuration of the PCI express slot to be tested according to the test signal, wherein the test logic control chip configures the two resistors connected to the I/O pins of the test logic control chip as a pull-up resistor and a pull-down resistor, and wherein the test logic control chip controls the I/O pins of the test logic control chip as a pull-up state, a pull-down state, and a no pull-up pull-down state to test the pins of the PCI express slot to be tested.
6. An external connection standard socket inspection system, comprising:
a motherboard, said motherboard having a peripheral component interconnect express (PCIe) slot;
the detection circuit board is inserted into the quick peripheral component interconnection slot through the quick peripheral component interconnection interface, and the detection circuit board further comprises:
the PCI express control chip and the PCI express interface are directly and electrically connected with each other through a switch, and receive detection signals to detect the PCI express slot and generate first detection result information;
the detection logic control chip and the rapid peripheral component interconnection interface are directly and electrically connected with each other through a switch, the detection logic control chip and the rapid peripheral component interconnection control chip are directly and electrically connected with each other through the switch, the detection signals are received to carry out detection control according to the detection signals, and detection logic setting is carried out to detect the rapid peripheral component interconnection slot and generate second detection result information;
the PCI express packet switch connector and the PCI express control chip are directly and electrically connected with each other through a first UART-RS-232 interface chip, the PCI express packet switch connector transmits the detection signal to the PCI express control chip, and the PCI express packet switch connector transmits the first detection result information; a kind of electronic device with high-pressure air-conditioning system
The detection logic connection connector is electrically connected with the detection logic control chip through a second UART-RS-232 interface chip, the detection logic connection connector transmits the detection signal to the detection logic control chip, and the detection logic connection connector transmits the second detection result information; a kind of electronic device with high-pressure air-conditioning system
The detection device is used for executing a detection program to generate the detection signal, the detection device is respectively electrically connected with the PCI express packet switching connector and the detection logic connection connector, the detection program respectively transmits the detection signal through the PCI express packet switching connector and the detection logic connection connector, the detection program transmits the first detection result information through the PCI express packet switching connector, and the detection program transmits the second detection result information through the detection logic connection connector.
7. The PCI express slot detection system of claim 6 wherein detecting the PCI express slot comprises power pin detection, PCIe transmission speed detection, PCIe transmission bandwidth detection, PCIe transmission speed switch detection, system management bus detection, wake detection, JTAG detection, PWRRK detection, and CLKREQ detection.
8. The PCI express slot detection system of claim 6 wherein the PCI express control chip detects and stores PCIe transmission speed and PCIe transmission bandwidth in a register when the detection circuit board is plugged into the PCI express slot through the PCI express interface, and the detection logic control chip obtains PCIe transmission speed and PCIe transmission bandwidth from the register to generate the second detection result.
9. The PCI express slot test system of claim 6, wherein the PCI express control chip controls switching of PCIe transmission speed according to the test signal and generates a PCIe connection state after switching of PCIe transmission speed as the first test result.
10. The PCI express slot test system of claim 6 wherein the test logic control chip electrically connects the I/O pins of the test logic control chip with the pin configuration of the PCI express slot to be tested according to the test signal, wherein the test logic control chip configures two resistors connected to the I/O pins of the test logic control chip as a pull-up resistor and a pull-down resistor, and wherein the test logic control chip controls the I/O pins of the test logic control chip to be in a pull-up state, a pull-down state, and a no pull-up pull-down state to test the pins of the PCI express slot to be tested.
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| TW201928386A (en) * | 2017-12-15 | 2019-07-16 | 英業達股份有限公司 | Peripheral component interconnect express slot detection system and method thereof |
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| US7447825B2 (en) * | 2006-03-10 | 2008-11-04 | Inventec Corporation | PCI-E automatic allocation system |
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| CN106940669A (en) * | 2017-03-13 | 2017-07-11 | 郑州云海信息技术有限公司 | A kind of PCIe slot position automatic testing method in place |
| TW201928386A (en) * | 2017-12-15 | 2019-07-16 | 英業達股份有限公司 | Peripheral component interconnect express slot detection system and method thereof |
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