CN114609510A

CN114609510A - Test control circuit and test control method for processor

Info

Publication number: CN114609510A
Application number: CN202210279334.1A
Authority: CN
Inventors: 不公告发明人
Original assignee: Shanghai Biren Intelligent Technology Co Ltd
Current assignee: Shanghai Biren Intelligent Technology Co Ltd
Priority date: 2022-03-21
Filing date: 2022-03-21
Publication date: 2022-06-10

Abstract

The present disclosure provides a test control circuit and a test control method for a processor. The treater includes a plurality of test access ports of parallel connection between signal input part and signal output part, and signal input part and test signal end are directly connected with receiving test signal and whether control a plurality of test access ports open input test signal, and test control circuit includes: the logic selection circuit is connected with the signal input end, the signal output end and the test signal end; the port selection circuit is connected with the logic selection circuit, the logic selection circuit outputs a first selection signal to the port selection circuit based on a test signal received from the test signal end, the port selection circuit responds to the first selection signal to select a port and output a second selection signal, and the signal input end and the signal output end control one or more of the plurality of test access ports to start inputting the test signal and start outputting the test data based on the second selection signal.

Description

Test control circuit and test control method for processor

Technical Field

Embodiments of the present disclosure relate to the field of processor technologies, and in particular, to a test control circuit and a test control method for a processor.

Background

Test Access Port (TAP) developed based on Joint Test Action Group (JTAG) is mainly used for detecting (Test) and debugging (Debug) functions inside a processor, and is ubiquitous in chips at the present stage, and is essential particularly in large-scale System on Chip (SoC). Typically, there are multiple JTAG TAPs in a chip to complete the test process for different functional modules. In addition, in the manufacturing process of the chip, different functional modules are usually manufactured by multiple manufacturers and constitute the final chip. Thus, the manufacturer configures the corresponding JTAG TAP for the functional module being produced. This makes the link mode layout and test process design for the plurality of JTAG TAPs included in the chip particularly important.

Disclosure of Invention

The embodiment of the disclosure provides a test control circuit and a test control method for a processor, which are used for providing reasonable layout for a connection mode of a plurality of Test Access Ports (TAPs) in the processor, improving the automation level of chip testing and reducing the use difficulty of test cases.

According to an aspect of the present disclosure, there is provided a test control circuit for a processor, the processor including a plurality of test access ports configured to be connected in parallel between a signal input terminal and a signal output terminal, wherein the signal input terminal is directly connected with a test signal terminal to receive a test signal from the test signal terminal and control whether the plurality of test access ports turn on an input test signal, the signal output terminal controls whether the plurality of test access ports turn on outputting test data, the test control circuit including: a logic selection circuit configured to be connected to the signal input terminal, the signal output terminal, and the test signal terminal; and a port selection circuit configured to be connected with the logic selection circuit, wherein the logic selection circuit outputs a first selection signal to the port selection circuit based on a test signal received from the test signal terminal, the port selection circuit performs port selection in response to the first selection signal and outputs a second selection signal, and the signal input terminal and the signal output terminal control one or more of the plurality of test access ports to turn on input test signals and turn on output test data based on the second selection signal.

According to some embodiments of the present disclosure, the plurality of test access ports are ports that comply with the joint test action organization specification, and the test signals include a test clock signal, a test mode select signal, a test data input signal, and a test reset signal.

According to some embodiments of the present disclosure, the logic selection circuit includes a state machine configured to receive a test mode selection signal, a test clock signal, and a test reset signal, and a monitoring circuit configured to receive a test data input signal, a test clock signal, and a test reset signal, wherein the logic selection circuit outputs the first selection signal to the port selection circuit based on the test signal received from the test signal terminal includes: the state machine determines that the plurality of test access ports are in an idle state based on the test mode selection signal and outputs an idle signal to the monitoring circuit; the monitoring circuit receives a test data input signal in response to the idle signal to determine whether the test data input signal satisfies a preset verify signal, and outputs a first select signal to the port select circuit in a case where it is determined that the verify signal is satisfied.

According to some embodiments of the present disclosure, the monitoring circuit includes a first register circuit, a controller, and a second register circuit, the first register circuit configured to receive an idle signal, a test data input signal, a test clock signal, and a test reset signal, the controller configured to be connected with the first register circuit and the second register circuit and to store a verification signal, the second register circuit connected with the port selection circuit, wherein the monitoring circuit receives the test data input signal in response to the idle signal to determine whether the test data input signal satisfies a preset verification signal, and in a case where it is determined that the verification signal is satisfied, the monitoring circuit outputs the first selection signal to the port selection circuit including: the first register circuit receives a test data input signal in response to the idle signal; the controller determines whether a test data input signal received by the first register circuit meets a verification signal, and outputs a start signal to the second register circuit under the condition that the verification signal is determined to be met; and the second register circuit outputs the first selection signal to the port selection circuit in response to the turn-on signal.

According to some embodiments of the present disclosure, the first register circuit is a shift register composed of a plurality of registers.

According to some embodiments of the disclosure, the port selection circuit is further configured to be connected with a signal input terminal and a signal output terminal, wherein the port selection circuit performs port selection in response to the first selection signal and outputs the second selection signal comprises: the port selection circuit responds to the first selection signal to turn on an input test mode selection signal; the port selection circuit performs port selection based on the test mode selection signal and generates a second selection signal.

According to some embodiments of the present disclosure, the plurality of test access ports are further configured to connect to an interface under test in the processor to test the interface under test connected thereto based on a test signal received from the signal input and to output test data.

According to some embodiments of the present disclosure, the interface under test includes a peripheral component interconnect express interface, a memory interface.

According to another aspect of the present disclosure, there is provided a test control method for a processor, the test control method being applied to a test control circuit, wherein the processor includes a plurality of test access ports configured to be connected in parallel between a signal input terminal and a signal output terminal, wherein the signal input terminal is directly connected to the test signal terminal to receive a test signal from the test signal terminal and control whether the plurality of test access ports turn on an input test signal, and the signal output terminal controls whether the plurality of test access ports turn on outputting test data, the test control circuit including: a logic selection circuit configured to be connected to the signal input terminal, the signal output terminal, and the test signal terminal; and a port selection circuit configured to be connected with the logic selection circuit. The test control method comprises the following steps: outputting, with a logic selection circuit, a first selection signal to a port selection circuit based on a test signal received from a test signal terminal; and performing port selection and outputting a second selection signal by using the port selection circuit in response to the first selection signal, wherein the signal input end and the signal output end control one or more of the plurality of test access ports to start inputting the test signal and start outputting the test data based on the second selection signal.

According to some embodiments of the present disclosure, the logic selection circuit includes a state machine configured to receive a test mode selection signal, a test clock signal, and a test reset signal, and a monitoring circuit configured to receive a test data input signal, a test clock signal, and a test reset signal, wherein outputting the first selection signal to the port selection circuit based on the test signal received from the test signal terminal includes: determining that the plurality of test access ports are in an idle state based on the test mode selection signal by using a state machine, and outputting an idle signal to the monitoring circuit; the monitoring circuit is utilized to receive a test data input signal in response to the idle signal to determine whether the test data input signal satisfies a preset verification signal, and in the event that the verification signal is determined to be satisfied, to output a first selection signal to the port selection circuit.

According to some embodiments of the present disclosure, the monitoring circuit includes a first register circuit configured to receive an idle signal, a test data input signal, a test clock signal, and a test reset signal, a controller configured to be connected with the first register circuit and the second register circuit and to store a verification signal, and a second register circuit connected with the port selection circuit, wherein receiving the test data input signal in response to the idle signal to determine whether the test data input signal satisfies a preset verification signal, and in a case where it is determined that the verification signal is satisfied, outputting the first selection signal to the port selection circuit includes: receiving a test data input signal with a first register circuit in response to an idle signal; determining whether a test data input signal received by the first register circuit satisfies a verification signal by using a controller, and outputting a start signal to the second register circuit under the condition that the verification signal is determined to be satisfied; and outputting, with the second register circuit, the first selection signal to the port selection circuit in response to the enable signal.

According to some embodiments of the disclosure, the port selection circuit is further configured to be connected with a signal input terminal and a signal output terminal, wherein the port selecting and outputting the second selection signal in response to the first selection signal comprises: turning on an input test mode select signal in response to a first select signal with a port select circuit; port selection is performed with a port selection circuit based on the test mode selection signal and a second selection signal is generated.

According to some embodiments of the present disclosure, the plurality of test access ports are further configured to connect to a tested interface in the processor, the test control method further comprising: and testing the tested interface connected with the signal input end by using a plurality of test access ports based on the test signal received from the signal input end and outputting test data.

With the test control circuit and the test control method for a processor provided by the embodiments of the present disclosure, a test topology can be realized in which a plurality of test access ports TAP are configured to be connected in parallel between a signal input terminal and a signal output terminal, and the signal input terminal is directly connected with a test signal terminal to directly receive a test signal from the test signal terminal. Further, selection between the plurality of TAPs is made by a logic selection circuit and a port selection circuit provided for the plurality of TAPs in the processor, so that the selected TAP can perform a test process and output test data based on a received test signal. Through the test control circuit and the test control method, manual TAP selection can be avoided from being involved in a software debugging process, the automation level of chip testing is improved, and the signal input end is directly connected with the test signal end, so that the use difficulty of a test case is reduced.

Drawings

In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1A shows a connection topology for multiple TAPs in the related art;

FIG. 1B illustrates another connection topology for multiple TAPs in the related art;

FIG. 2 illustrates a connection topology for multiple TAPs according to some embodiments of the present disclosure;

FIG. 3 illustrates another connection topology for multiple TAPs according to some embodiments of the present disclosure;

FIG. 4 illustrates a circuit schematic of a logic selection circuit and a port selection circuit according to some embodiments of the present disclosure;

FIG. 5 illustrates a detailed circuit diagram of a logic selection circuit and a port selection circuit according to some embodiments of the present disclosure;

FIG. 6 shows a flow chart of a test control method for a processor according to an embodiment of the disclosure.

Detailed Description

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. It is to be understood that the described embodiments are merely exemplary of some, and not all, of the present disclosure. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without any inventive step, are intended to be within the scope of the present disclosure.

Furthermore, as used in this disclosure and in the claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are inclusive in the plural, unless the context clearly dictates otherwise. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Likewise, the word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

JTAG based test access ports TAP are ubiquitous in chips, especially essential in socs. Typically, there are multiple JTAG TAPs in a chip to complete the test process for different functional modules. The Test function of JTAG is used to Test (Test) the electrical characteristics of the chip and to Debug (Debug) the chip's peripherals. JTAG defines test Access port TAP (test Access port) in the chip to realize the test process, and specifically detects and debugs the internal node of the chip by a special JTAG test tool. There is a standard IEEE1149.1 for JTAG, where the registers are divided into a Data Register (DR) and an Instruction Register (IR), which can be used to control the Data Register DR, e.g. to select a target scan chain. In particular, the TAP may be implemented as a general-purpose port, and the data register and the instruction register provided by the chip may be accessed through the TAP. For example, the TAP may include devices such as state machines and registers.

The standard IEEE1149.1 (which may also be denoted as JTAG specification) specifies some standard Test signals for the Test access port TAP, e.g., Test Mode Select (TMS), for controlling state transitions of the Test access port TAP state machine; test Clock signal (TCK); test Data Input signal (TDI); a Test Reset Signal (TRST) for resetting the Test access port TAP. Furthermore, the standard IEEE1149.1 specifies a Test Data Output signal (TDO), i.e. an Output Test signal. The IEEE1149.1 standard also specifies other signals, which are not further listed here.

In the test process, the test access port TAP determines whether to turn on based on the received test mode select signal TMS, i.e., a gating process for the test access port TAP is implemented by the TMS. The registers in the gated TAP will be able to receive test signals (which may also be referred to as test data, e.g. may be test cases, etc.) from the test data input signal terminal TDI and output test results via the test data output signal terminal TDO. For convenience of description, herein, a data input signal terminal and a signal input through the test data input signal terminal are both denoted as TDI, and a test data output signal terminal and a signal output through the test data output signal terminal are both denoted as TDO.

As described above, in the manufacturing process of chips, different functional modules are generally manufactured by a plurality of manufacturers and constitute a final chip. That is, there may be multiple vendors for the chip, and the vendors are configured with respective JTAG TAPs for the functional modules produced and are provided with a large number of test cases for the functional modules. This makes the link mode layout and test process design for the plurality of JTAG TAPs included in the chip particularly important.

As an example, fig. 1A shows a connection topology for a plurality of TAP in the related art. In fig. 1A, N TAP are connected in series, each TAP is directly connected to a test clock signal TCK, a test mode select signal TMS, and a test reset signal TRST, and a test data input signal terminal TDI and a test data output signal terminal TDO are respectively connected to the head and tail ends of the N TAP.

For a TAP gated based on TMS, for example TAP 2, will receive test signals from TDI to conduct the test procedure for the chip and output the test results via TDO. After the test procedure is completed, the gated TAP 2 will enter an idle state until gated again based on TMS. It can be seen that the topology shown in fig. 1A is not favorable for efficient chip testing, and as the number of test access ports TAPs increases, the length of a test chain increases, which results in a longer detection or debugging time, thereby reducing the testing speed, which is especially unfavorable for testing large-scale chips such as SoC.

In the related art, there is also a topology designed in a Daisy-chain (Daisy chain) form as shown in fig. 1B, in which a plurality of test access ports TAPs are connected together in parallel. As shown IN fig. 1B, the TAP1 through TAP 5 are connected IN parallel between a signal input terminal IN for controlling whether the plurality of TAPs are turned on to input a test signal and a signal output terminal OUT for controlling whether the plurality of TAPs are turned on to output test data (e.g., test results). IN the example of fig. 1B, the signal input IN and signal output OUT may control which TAP, e.g., gated TAP1, is gated for the test process based on the signals output by the MST TAPs. According to some embodiments of the present disclosure, the signal input terminal IN and the signal output terminal OUT may implement a data selector (MUX) to implement the above-described gating process. IN fig. 1B, only the gated TAP can receive input data and output test results via IN and OUT.

For the multiple TAPs connected in parallel in fig. 1B, in order to gate the required TAP based on the TMS, that is, to enable the TAP currently required to be tested, a Master TAP (MST TAP) for gating the TAP is provided in the topology of fig. 1B. The MST TAP is connected between test signal terminals (signals shown IN fig. 1B include TMS, TRST, TDI and TCK) and IN. In an implementation, the MST TAP first receives a test signal, then determines the TAP that needs to be gated based on the test signal, and generates an output signal. Specifically, the MST TAP will output a strobe signal TAP _ SEL via its output port MST _ TDO and transmit to IN and OUT to enable a corresponding TAP (e.g., TAP 2) to transition to an on state and receive and output data via IN and OUT, while other ungated TAPs will remain IN an idle state, with no data being received and output by TAPs IN the idle state.

Referring to fig. 1B, since the test signal needs to first enter the MST TAP before entering each TAP to generate the gate signal TAP _ SEL, the test clock signal increases the clock period due to the MST TAP, which is disadvantageous for the test. As described above, the vendor provided test cases for functional modules generally does not take into account the clock delay caused by MST TAP, and if the chip tester wishes to perform testing by using the provided test cases, and further needs additional workload to modify the test cases, the test mode (Pattern) and program control become more complicated.

To solve the above technical problems in the related art, some embodiments of the present disclosure provide a test control circuit for a processor having a plurality of test access ports TAP for performing a test. The test control circuit is used for providing reasonable layout for a topological structure of a plurality of Test Access Ports (TAP) in the processor, improving the automation level of chip test and reducing the use difficulty of test cases. It is understood that references herein to a processor generally refer to various types of integrated circuit structures, such as, without limitation, microprocessors, Central Processing Units (CPUs), Graphics Processing Units (GPUs), General-purpose Graphics Processing units (GPGPUs), System on chips (socs), and the like. Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs.

With the test control circuit provided by some embodiments of the present disclosure, a test topology can be realized in which a plurality of test access ports TAP are configured to be connected in parallel between a signal input terminal and a signal output terminal, and the signal input terminal is directly connected with a test signal terminal to directly receive a test signal from the test signal terminal. Further, selection between the plurality of TAPs is made by a logic selection circuit and a port selection circuit provided for the plurality of TAPs in the processor, so that the selected TAP can perform a test process and output test data based on a received test signal. Through the test control circuit, manual TAP (test access point) selection in a software debugging process can be avoided, the automation level of chip testing is improved, and the signal input end is directly connected with the test signal end, so that the use difficulty of a test case is reduced.

The manner of connection between the test control circuit and the TAP topology and the specific circuit configuration according to some embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

Fig. 2 illustrates a connection topology for a plurality of TAPs according to some embodiments of the present disclosure, and as shown IN fig. 2, the plurality of test access ports TAPs are configured to be connected IN parallel between a signal input terminal IN and a signal output terminal OUT, and the signal input terminal IN is directly connected with a test signal terminal JTAG to directly receive a test signal from the test signal terminal JTAG, wherein the test signal may be TMS, TDI, CLK, TRST, etc. as described above. The signal input terminal IN is for controlling whether the plurality of TAP ports turn on input test signals based on the received selection signal, the signal output terminal OUT is for controlling whether the plurality of TAP ports turn on output test data based on the received selection signal, only the gated TAP can receive and output data via IN and OUT, and the other non-gated TAPs will be IN an idle state. IN some embodiments according to the present disclosure, a logic selection circuit and a port selection circuit are provided, wherein the logic selection circuit outputs a first selection signal to the port selection circuit based on a test signal received from a test signal terminal, and the port selection circuit performs port selection IN response to the first selection signal and outputs a second selection signal, so that the signal input terminal IN and the signal output terminal OUT can control one or more of the plurality of test access ports to turn on an input test signal and turn on outputting test data based on the second selection signal.

Compared with the topology connection mode shown IN fig. 1B, the topology structure according to the embodiment of the present disclosure does not need to arrange an additional gating circuit (MST TAP) between IN and JTAG _, so that the test signal can be directly input to the TAP for testing through IN, and the clock delay generated IN the implementation mode shown IN fig. 1B is avoided, thereby improving the test efficiency, and the test case does not need to be adjusted according to the structure of the MST TAP, which reduces the difficulty IN using the test case.

Next, as shown in fig. 2, in order to implement the gating of the plurality of TAPs, i.e., to generate the gating signal TAP _ SEL, a test control circuit is provided according to some embodiments of the present disclosure. Specifically, the test control circuit is shown to include a logic selection circuit and a port selection circuit according to the functional distinction. It is understood that the logic selection circuit and the port selection circuit in the test control circuit according to the embodiment of the present disclosure implement the function of gating the TAP as a whole.

Referring next to fig. 2, the logic selection circuit is configured to be connected to the signal input terminal IN, the signal output terminal OUT, and the test signal terminal JTAG _. The port selection circuit is configured to be connected to the logic selection circuit. According to some embodiments of the present disclosure, the logic selection circuit outputs a first selection signal to the port selection circuit based on the test signal received from the test signal terminal JTAG _, the port selection circuit performs port selection IN response to the first selection signal and outputs a second selection signal, wherein the signal input terminal IN and the signal output terminal OUT control one or more of the plurality of test access ports to enable input of the test signal and enable output of the test data based on the second selection signal.

According to some embodiments of the present disclosure, the plurality of TAP is further configured to be connected to an interface under test in the processor to test the interface under test connected thereto based on a test signal received from the signal input terminal and output test data. As an example, the interface under test may include, for example, peripheral component interconnect express (PCIe), memory interface (DDR), i.e., detecting and debugging functions of PCIe, DDR, or other nodes inside the processor via the TAP.

By utilizing the signal processing process between the logic selection circuit and the port selection circuit, the corresponding TAP can be automatically gated to perform a corresponding test process according to the input test signal, so that manual TAP selection in a software debugging process can be avoided, and the automation level of chip testing is improved. In addition, in the implementation modes of the logic selection circuit and the port selection circuit, the function of gating the TAP can be realized only by relying on the test signal conforming to the JTAG standard, no additional signal needs to be designed, and the circuit has a simple structure and is convenient to implement.

As an implementation, the port selection circuit may be implemented as a TAP. IN particular, fig. 3 shows another connection topology for multiple TAPs, IN the implementation of fig. 3 the port selection circuit is connected between IN and OUT IN the form of TAPs and IN parallel with other TAPs. IN fig. 3, a Test signal of the Test signal terminal JTAG _isfirst transmitted to the logic selection circuit, so that the logic selection circuit outputs a first selection signal, which may be, for example, TAP _ SEL shown IN fig. 3, to the port selection circuit based on the Test signal, i.e., IN this process, the logic selection circuit first generates the first selection signal based on the Test signal to enable the port selection circuit implemented as a TAP, thereby enabling the port selection TAP to receive the Test signal via the IN, and enables a detection Data Register (TDR) IN the port selection TAP for Data processing to perform port selection and output a second selection signal. It is understood that, in other implementations, the port selection circuit may also be implemented in other circuit structures, which is not limited herein.

The specific implementation processes of the logic selection circuit, the first selection signal, the port selection circuit, and the second selection signal will be described in detail with reference to the circuit diagrams in fig. 4 and 5.

Specifically, fig. 4 shows a circuit schematic diagram of a logic selection circuit and a port selection circuit according to some embodiments of the present disclosure, and fig. 5 shows a detailed circuit diagram of a logic selection circuit and a port selection circuit according to some embodiments of the present disclosure.

As shown in fig. 4, the LOGIC selection circuit (TAP _ SELECT _ LOGIC) may include a State Machine (FSM) configured to receive the test mode SELECT signal TMS, the test clock signal TCK, and the test reset signal TRST, and a monitoring circuit (MONITOR) configured to receive the test data input signal TDI, the test clock signal TCK, and the test reset signal TRST.

According to some embodiments of the present disclosure, the logic selection circuit outputting the first selection signal to the port selection circuit based on the test signal received from the test signal terminal includes: the state machine FSM determines that the plurality of test access ports TAP are in an idle state based on the test mode select signal TMS and outputs an idle signal to the monitoring circuit MONITOR. As an example, the FSM can first determine whether, for example, TAP1 to TAP 5 in fig. 3 is in an IDLE state based on the TMS signal, and if it is determined to be in the IDLE state, output an IDLE signal IDLE to the monitoring circuit MONITOR.

According to some embodiments of the present disclosure, the monitoring circuit MONITOR receives the test data input signal TDI in response to the IDLE signal IDLE to determine whether the test data input signal TDI satisfies a preset verification signal, and in case it is determined that the verification signal is satisfied, the monitoring circuit MONITOR outputs a first selection signal to the port selection circuit. IN the example of fig. 3, this first selection signal may gate the port select TAP, i.e., cause the state machine of the port select TAP to implement a jump to begin receiving test signals from the IN, and based on the received test signals, determine the TAP to be selected for testing, and output a second selection signal.

According to some embodiments of the present disclosure, the monitoring circuit may specifically include a first register circuit, a controller, and a second register circuit. According to some embodiments of the present disclosure, the first register circuit is configured to receive an idle signal, a test data input signal, a test clock signal, and a test reset signal; the controller is configured to be connected with the first register circuit and the second register circuit and store the verification signal; the second register circuit is connected to the port selection circuit. The first register circuit may be a shift register composed of a plurality of registers, and configured to receive TDI. For example, the shift register may be set according to a predefined number of bits of the verification signal.

According to some embodiments of the present disclosure, the monitoring circuit receives a test data input signal in response to the idle signal to determine whether the test data input signal satisfies a preset verify signal, and in a case where it is determined that the verify signal is satisfied, the monitoring circuit outputs a first select signal to the port select circuit including: the first register circuit receives a test data input signal in response to the idle signal; the controller determines whether the test data input signal received by the first register circuit meets a verification signal, and outputs a start signal to the second register circuit under the condition that the verification signal is determined to be met; and the second register circuit outputs the first selection signal to the port selection circuit in response to the turn-on signal.

According to some embodiments of the disclosure, the port selection circuit is further configured to be connected with a signal input and a signal output, wherein the port selection circuit to make the port selection in response to the first selection signal and output the second selection signal comprises: the port selection circuit responds to the first selection signal to turn on an input test mode selection signal; the port selection circuit performs port selection based on the test mode selection signal and generates a second selection signal.

Fig. 5 shows a specific circuit configuration of the state machine FSM, the monitoring circuit MONITOR, and a connection manner with the port selection TAP. The overall implementation of the test monitoring circuit as some embodiments of the present disclosure will be described below in conjunction with fig. 5.

As shown in fig. 5, the logic selection circuit includes a state machine FSM and a monitoring circuit, wherein the monitoring circuit may include a first register circuit, a controller, and a second register circuit. First, the state machine FSM receives a test signal from the test signal terminal JTAG _. According to some embodiments of the present disclosure, the test signals include a test mode select signal TMS, a test clock signal TCK, and a test reset signal TRST that satisfy the JTAG specification. The state machine FSM may determine whether the TAP is in an IDLE state based on TMS, for example, and if it is determined to be in the IDLE state, output an IDLE signal IDLE to a first register circuit in the monitoring circuit.

As shown in fig. 5, the first register circuit is configured to receive the IDLE signal IDLE output by the state machine FSM, and in addition to receive the test data input signal TDI, the test clock signal TCK and the test reset signal TRST. Where the FSM determines that the connected TAP is in an IDLE state based on TMS, an IDLE signal IDLE will be output to the first register circuitry, which receives TDI in response to the IDLE signal IDLE. As shown in fig. 5, the first register circuit is composed of a group of shift registers and logic gate units. First, after the and gate in the first register circuit receives the IDLE signal IDLE, the shift register may be caused to receive the TDI signal. Then, the controller judges whether the TDI signal received by the shift register is consistent with a prestored verification signal. As an example, the validation signal may be a set of data for comparison with the received TDI signal, in which case the controller outputs an on signal to a register in the second register circuit.

As shown in fig. 5, the enable signal is transmitted to the reset terminal of the register in the second register circuit so that the register outputs the first selection signal in response to the enable signal. In particular, in case the port selection circuit is implemented as the port selection TAP shown in fig. 3, the first selection signal may be understood as the gate signal TAP _ SEL for the port selection TAP. That is, the gate signal TAP _ SEL output by the second register circuit in response to the on signal is used to gate the port selection TAP so that the port selection TAP can be in an on state, and to determine the TAP to be tested based on the received TMS. Specifically, the port selection TAP may configure the detection data register TDR based on the received TMS and generate an updated strobe signal UPDATE _ TAP _ SEL.

As shown IN fig. 5, a gate signal UPDATE _ TAP _ SEL generated by the port selection TAP may be output to IN and OUT via the second register circuit, thereby causing the TAP to be tested to transition from an idle state to an on state, and receiving test data via IN and outputting a test result via OUT.

By utilizing the test control circuit for the processor provided by some embodiments of the disclosure, manual TAP selection can be avoided in a software debugging process, the automation level of chip testing is improved, and the signal input end is directly connected with the test signal end, so that the use difficulty of a test case is reduced.

According to another aspect of the present disclosure, there is also provided a test control method for a processor. Specifically, the processor may include a plurality of test access ports TAP configured to be connected in parallel between a signal input terminal and a signal output terminal, wherein the signal input terminal is directly connected to the test signal terminal to receive the test signal from the test signal terminal and control whether the plurality of test access ports turn on input test signals based on the selection signal output by the port selection circuit, and the signal output terminal also controls whether the plurality of test access ports turn on output test data based on the selection signal output by the port selection circuit. According to some embodiments of the present disclosure, the plurality of test access ports TAPs are ports (which may also be denoted as JTAG TAPs) that conform to the joint test action group JTAG specification. According to the JTAG standard, the test signals may include, for example, a test clock signal TCK, a test mode select signal TMS, a test data input signal TDI, and a test reset signal TRST, etc.

The test control method according to some embodiments of the present disclosure is applicable to a test control circuit including a logic selection circuit and a port selection circuit. Wherein the logic selection circuit is configured to be connected to the signal input terminal, the signal output terminal, and the test signal terminal, and the port selection circuit is configured to be connected to the logic selection circuit. The circuit structure and implementation of the test control circuit may be combined with the description above with respect to fig. 2-5, and will not be repeated here.

To more clearly illustrate the test control method according to an embodiment of the present disclosure, fig. 6 is provided for illustrating a flowchart of the test control method according to an embodiment of the present disclosure. An implementation process of the test control method according to the embodiment of the present disclosure will be described below with reference to fig. 6.

As shown in fig. 6, in step S601, the first selection signal is output to the port selection circuit by the logic selection circuit based on the test signal received from the test signal terminal. Next, in step S602, a port selection circuit is utilized to perform port selection in response to the first selection signal and output a second selection signal, wherein the signal input terminal and the signal output terminal control one or more of the plurality of test access ports to turn on input test signals and turn on output test data based on the second selection signal.

According to some embodiments of the disclosure, the monitoring circuit includes a first register circuit configured to receive an idle signal, a test data input signal, a test clock signal, and a test reset signal, a controller configured to be connected to the first register circuit and the second register circuit and to store a verification signal, and a second register circuit connected to the port selection circuit, wherein receiving the test data input signal in response to the idle signal to determine whether the test data input signal satisfies a preset verification signal, and in the case where it is determined that the verification signal is satisfied, outputting a first selection signal to the port selection circuit includes: receiving a test data input signal with a first register circuit in response to an idle signal; determining whether a test data input signal received by the first register circuit satisfies a verification signal by using a controller, and outputting a start signal to the second register circuit under the condition that the verification signal is determined to be satisfied; and outputting, with the second register circuit, the first selection signal to the port selection circuit in response to the enable signal.

According to some embodiments of the present disclosure, the port selection circuit is further configured to be connected with a signal input terminal and a signal output terminal, wherein the port selecting and outputting the second selection signal in response to the first selection signal comprises: turning on an input test mode select signal in response to a first select signal with a port select circuit; and performing port selection based on the test mode selection signal and generating a second selection signal with the port selection circuit.

According to some embodiments of the present disclosure, the plurality of test access ports are further configured to connect to a tested interface in the processor, and the test control method further comprises: and testing the tested interface connected with the signal input end by using a plurality of test access ports based on the test signal received from the signal input end and outputting test data. According to some embodiments of the present disclosure, the interface under test includes a peripheral component interconnect express interface, a memory interface.

Those skilled in the art will appreciate that the disclosure of the present disclosure is susceptible to numerous variations and modifications. For example, the various devices or components described above may be implemented in hardware, or may be implemented in software, firmware, or a combination of some or all of the three.

Flow charts are used in this disclosure to illustrate steps of methods according to embodiments of the disclosure. It should be understood that the preceding or subsequent steps need not be performed in the exact order shown. Rather, various steps may be processed in reverse order or simultaneously. Also, other operations may be added to the processes.

It will be understood by those skilled in the art that all or part of the steps of the above methods may be implemented by instructing the relevant hardware through a computer program, and the program may be stored in a computer readable storage medium, such as a read-only memory, a magnetic or optical disk, and the like. Alternatively, all or part of the steps of the above embodiments may be implemented using one or more integrated circuits. Accordingly, each module/unit in the above embodiments may be implemented in the form of hardware, and may also be implemented in the form of a software functional module. The present disclosure is not limited to any specific form of combination of hardware and software.

The foregoing is illustrative of the present disclosure and is not to be construed as limiting thereof. Although a few exemplary embodiments of this disclosure have been described, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of this disclosure. Accordingly, all such modifications are intended to be included within the scope of this disclosure as defined in the claims. It is to be understood that the foregoing is illustrative of the present disclosure and is not to be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.

Claims

1. A test control circuit for a processor, the processor comprising a plurality of test access ports configured to be connected in parallel between a signal input and a signal output, wherein the signal input is directly connected to a test signal terminal to receive a test signal from the test signal terminal and control whether the plurality of test access ports are enabled to input the test signal, and the signal output controls whether the plurality of test access ports are enabled to output test data, the test control circuit comprising:

a logic selection circuit configured to be connected to the signal input terminal, the signal output terminal, and the test signal terminal; and

a port selection circuit configured to be connected to the logic selection circuit, wherein,

the logic selection circuit outputs a first selection signal to the port selection circuit based on the test signal received from the test signal terminal, the port selection circuit performs port selection in response to the first selection signal and outputs a second selection signal, wherein the signal input terminal and the signal output terminal control one or more of the plurality of test access ports to turn on input test signals and turn on output test data based on the second selection signal.

2. The test control circuit of claim 1, wherein the plurality of test access ports are ports that comply with a joint test action organization specification, and the test signals comprise a test clock signal, a test mode select signal, a test data input signal, and a test reset signal.

3. The test control circuit of claim 2, wherein the logic selection circuit comprises a state machine configured to receive the test mode selection signal, the test clock signal, and the test reset signal, and a monitoring circuit configured to receive the test data input signal, the test clock signal, and the test reset signal, wherein the logic selection circuit outputs a first selection signal to the port selection circuit based on the test signal received from the test signal terminal comprises:

the state machine determines that the plurality of test access ports are in an idle state based on the test mode selection signal and outputs an idle signal to the monitoring circuit;

the monitor circuit receives the test data input signal in response to the idle signal to determine whether the test data input signal satisfies a preset verify signal, and outputs the first select signal to the port select circuit in a case where it is determined that the verify signal is satisfied.

4. The test control circuit of claim 3, wherein the monitoring circuit comprises a first register circuit configured to receive the idle signal, the test data input signal, the test clock signal, and the test reset signal, a controller configured to be connected to the first register circuit and the second register circuit and to store the verification signal, and a second register circuit connected to the port selection circuit, wherein,

the monitor circuit receiving the test data input signal in response to the idle signal to determine whether the test data input signal satisfies a preset verify signal, the monitor circuit outputting the first select signal to the port select circuit including, in the event that the verify signal is determined to be satisfied:

the first register circuit receives the test data input signal in response to the idle signal;

the controller determines whether the test data input signal received by the first register circuit satisfies the verification signal, and outputs a turn-on signal to the second register circuit if it is determined that the verification signal is satisfied; and

the second register circuit outputs the first selection signal to the port selection circuit in response to the enable signal.

5. The test control circuit according to claim 4, wherein the first register circuit is a shift register composed of a plurality of registers.

6. The test control circuit of claim 2, wherein the port selection circuit is further configured to connect with the signal input and the signal output, wherein,

the port selection circuit making a port selection in response to the first selection signal and outputting a second selection signal includes:

the port selection circuit turns on the input of the test mode selection signal in response to the first selection signal;

the port selection circuit performs port selection based on the test mode selection signal and generates the second selection signal.

7. The test control circuit of claim 1, wherein the plurality of test access ports are further configured to connect to an interface under test in the processor to test the interface under test connected thereto based on the test signal received from the signal input and output test data.

8. The test control circuit of claim 7, wherein the interface under test comprises a peripheral component interconnect express interface, a memory interface.

9. A test control method for a processor, the test control method being applicable to a test control circuit, the processor comprising a plurality of test access ports configured to be connected in parallel between a signal input terminal and a signal output terminal, wherein the signal input terminal is directly connected to a test signal terminal to receive a test signal from the test signal terminal and control whether the plurality of test access ports are turned on to input the test signal, the signal output terminal controls whether the plurality of test access ports are turned on to output test data,

the test control circuit includes: a logic selection circuit configured to be connected to the signal input terminal, the signal output terminal, and the test signal terminal; and a port selection circuit configured to be connected to the logic selection circuit, wherein the test control method includes:

outputting, with the logic selection circuit, a first selection signal to the port selection circuit based on the test signal received from the test signal terminal;

and performing port selection by the port selection circuit in response to the first selection signal and outputting a second selection signal, wherein the signal input terminal and the signal output terminal control one or more of the plurality of test access ports to turn on input test signals and turn on output test data based on the second selection signal.

10. The method of claim 9, wherein the plurality of test access ports are ports compliant with the joint test action organization specification, and the test signals comprise a test clock signal, a test mode select signal, a test data input signal, and a test reset signal.

11. The test control method of claim 10, wherein the logic selection circuit comprises a state machine configured to receive the test mode selection signal, the test clock signal, and the test reset signal, and a monitoring circuit configured to receive the test data input signal, the test clock signal, and the test reset signal, wherein the outputting the first selection signal to the port selection circuit based on the test signal received from the test signal terminal comprises:

determining, by the state machine, that the plurality of tap ports are in an idle state based on the test mode select signal and outputting an idle signal to the monitor circuit;

receiving, with the monitor circuit, the test data input signal in response to the idle signal to determine whether the test data input signal satisfies a preset verify signal, and in the event that it is determined that the verify signal is satisfied, outputting the first select signal to the port select circuit.

12. The test control method of claim 11, wherein the monitoring circuit comprises a first register circuit, a controller, and a second register circuit, the first register circuit configured to receive the idle signal, the test data input signal, the test clock signal, and the test reset signal, the controller configured to be connected to the first register circuit and the second register circuit and to store the verification signal, the second register circuit connected to the port selection circuit, wherein,

said receiving said test data input signal in response to said idle signal to determine whether said test data input signal satisfies a preset verify signal, in the event that it is determined that said verify signal is satisfied, outputting said first select signal to said port select circuit comprising:

receiving, with the first register circuit, the test data input signal in response to the idle signal;

determining, with the controller, whether the test data input signal received by the first register circuit satisfies the verification signal, and in the event that it is determined that the verification signal is satisfied, outputting a turn-on signal to the second register circuit; and

outputting, with the second register circuit, the first selection signal to the port selection circuit in response to the turn-on signal.

13. The test control method according to claim 12, wherein the first register circuit is a shift register composed of a plurality of registers.

14. The test control method of claim 10, wherein the port selection circuit is further configured to be connected to the signal input and the signal output, wherein,

the performing port selection in response to the first selection signal and outputting a second selection signal comprises:

turning on the input of the test mode select signal with the port select circuit in response to the first select signal;

port selection is performed with the port selection circuitry based on the test mode selection signal and the second selection signal is generated.

15. The test control method of claim 9, wherein the plurality of test access ports are further configured to connect to an interface under test in the processor, the test control method further comprising:

and testing the tested interface connected with the plurality of test access ports on the basis of the test signals received from the signal input end and outputting test data.

16. The test control method of claim 15, wherein the interface under test comprises a peripheral component interconnect express interface, a memory interface.