JP3966453B2 - Semiconductor integrated circuit - Google Patents

Description

Technical field
The present invention relates to a test technique in a semiconductor integrated circuit (IC), and more particularly, to a data processing apparatus constituted by a plurality of functional modules, a microprocessor, and a system LSI (Large Scale Integration) such as a single-chip microcomputer. The present invention relates to a technique that is effective when applied to a test method.
Background art
Semiconductor integrated circuits have gradually increased in logical scale that can be mounted on one semiconductor chip due to the development of microfabrication technology. Therefore, there is also provided a semiconductor integrated circuit (hereinafter also referred to as a system LSI) in which system functions such as a microprocessor and a single chip microcomputer that have been conventionally realized by a plurality of chips are mounted on one semiconductor chip. It ’s coming.
When a circuit having various functions such as a central processing unit (CPU), a read only memory (ROM), and a random access memory (RAM) is mounted on one semiconductor chip, the way of coupling to each other is determined. It is efficient to design each function separately. Then, a circuit block designed to have such a predetermined function (referred to as a functional module in this specification) is registered in a database or the like, and is registered when a similar semiconductor integrated circuit is developed later. A semiconductor integrated circuit satisfying a desired specification can be obtained by selecting and combining modules having a desired function from a plurality of modules. Therefore, the use of the database as described above is extremely effective for shortening the development period.
In the development of a logic integrated circuit such as a data processor or a single chip microcomputer, a logic test is performed at the final stage of development in order to verify (failure detection) whether the internal logic circuit operates as expected. For testing a small-scale logic integrated circuit, a method of inputting a test pattern and comparing an output signal with an expected value can be applied. However, in a large-scale logic integrated circuit, the test pattern becomes enormous and the failure detection rate decreases. For this reason, some logic integrated circuits such as system LSIs are provided with a shift scan test function.
The shift scan type test circuit connects a plurality of flip-flops constituting a logic circuit in a serial form so that a shift register can be configured. At the time of testing, test data is scanned into the shift register from the input pin, and the data is directly inserted into the logic circuit to operate, and the data held in the flip-flop at a certain point is used by the shift register. This technology enables efficient testing by scanning out the output pin.
Problems to be solved by the invention
As a method for testing a logic integrated circuit composed of a plurality of functional modules, a method of inspecting by inputting an input / output terminal of each module to an external terminal and inputting a test pattern for each module can be considered. Although this method has an advantage that a test pattern created once can be used, there is a problem in that the number of terminals is greatly increased, and consequently the chip size is increased.
It is also conceivable to shorten the development period by providing a test circuit of a shift scan method for each functional module and reusing the test pattern once created when developing another semiconductor integrated circuit. However, in the technology for developing a semiconductor integrated circuit by combining a plurality of functional modules, the test interface circuit is different for each semiconductor integrated circuit, that is, an interface circuit having a different specification for each semiconductor integrated circuit is designed. Campus had to be recreated for each semiconductor integrated circuit. Therefore, there has been a problem that the development period is not sufficiently shortened.
An object of the present invention is to provide a technique capable of shortening the development period when a semiconductor integrated circuit is configured using a plurality of functional modules.
Another object of the present invention is to provide a technique capable of testing each module without increasing the number of external terminals.
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
Disclosure of the invention
Outlines of representative ones of the inventions disclosed in the present application will be described as follows.
That is, when a semiconductor integrated circuit such as a system LSI is configured using a plurality of functional modules, a shift scan path is incorporated in each functional module. Each functional module is provided with a test input / output terminal connected to the shift scan path separately from the input / output terminal during normal operation. Further, the semiconductor integrated circuit includes a bus interface circuit for connecting input / output terminals of a plurality of functional modules during normal operation to the bus, a bus-side input / output terminal of the bus interface circuit, and a test input for each functional module. An external interface switching circuit for switching the output terminal to connect to the external terminal and an interface control circuit for performing switching control of the external interface circuit are provided, and these are formed on one semiconductor chip.
As the interface control circuit, a JTAG interface control circuit defined by the IEEE 1149.1 standard is used, and a switching command for switching the external interface switching circuit is provided as one of the commands to the control circuit. It is done. The interface control circuit generates a control signal for controlling the interface switching circuit when this switching command is input.
The bus interface circuit converts the level of input / output signals, sets the timing, and controls the communication protocol according to the specifications of the semiconductor integrated circuit. In conventional semiconductor integrated circuits, test interface circuits with different specifications are designed for each semiconductor integrated circuit. However, according to the above means, test interface circuits with different specifications are designed for each semiconductor integrated circuit. There is no need to do it. Further, with respect to the scan path, it is only necessary to provide a path for connecting the input / output terminals during the test operation of each functional module to the external interface switching circuit. Therefore, there is no need to recreate a scan path or a test pattern for each semiconductor integrated circuit as in a semiconductor integrated circuit incorporating a conventional shift scan method. Therefore, the development period of the semiconductor integrated circuit can be greatly shortened.
Further, since the external interface switching circuit connects the test input / output terminals of the module to the external terminals during the test operation, each module can be tested without increasing the number of external terminals. Furthermore, if a JTAG interface control circuit defined by the IEEE 1149.1 standard is used as the interface control circuit, versatility can be enhanced, and the test of the semiconductor integrated circuit can be easily made.
In the present invention, a JTAG interface according to the IEEE 1149.1 standard is disclosed as an example, but a dedicated interface control circuit having a similar function may be used. Further, a test command that can be processed by the central processing unit without providing these interface control circuits may be provided, and the same test function may be realized by the command or in combination with a control register or the like.
BEST MODE FOR CARRYING OUT THE INVENTION
Preferred embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram of an embodiment of a system LSI as an example of a semiconductor integrated circuit to which the present invention is applied. On a single semiconductor chip 100 such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique. Composed.
FIG. 1 shows a schematic configuration when the present invention is applied to a microprocessor or a single chip microcomputer as an example of a system LSI.
Reference numerals 110 to 140 in FIG. 1 denote functional modules that are formed on the semiconductor chip 100 and constitute a system having a desired function, and 150 denotes between these modules and an external device provided outside the semiconductor chip 100. A bus interface circuit 160 for inputting / outputting signals is a plurality of external terminals for inputting / outputting signals. An external bus is connected to the external terminal 160.
Functional modules that make up a microprocessor or single-chip microcomputer include a central processing unit (CPU core) that decodes program instructions and executes the corresponding processes and operations, as well as reads that store programs and fixed data Dedicated memory ROM, memory RAM that can be read and written as needed to provide the work area of the CPU and the primary storage area of data, a bus controller that manages bus usage rights, serial communication interface, timer circuit, DMA (direct There are peripheral circuit modules (IP) such as a (memory access) controller, a digital / analog conversion circuit, and an analog / digital conversion circuit. In FIG. 1, 110 is a CPU core, and IPs 120 to 140 are the peripheral circuit modules.
In the system LSI of this embodiment, the original signal path 170 for the bus interface circuit 150 and the functional modules 110 to 140 are provided between the functional modules 110 to 140 and the bus interface circuit 150 and the external terminal 160. An external interface switching circuit 180 that switches between a direct connection path 171 for enabling direct input / output of a signal to 140 and a scan path 172, 173, 174, 175 for shift scanning provided for each of the functional modules; An interface control circuit 190 for forming a switching control signal for the external interface switching circuit 180 is provided. Each of the scan paths 172 to 175 includes a test data input wiring (scan-in path) for inputting test data and a test data output wiring (scan-out path) for outputting test data.
The interface control circuit 190 is coupled to a plurality of external terminals 195 for the test mode control signals TCK, TRST, TMS, the test data input signal TDI, and the test data output signal TDO, as illustrated in FIG. As the control circuit 190, a JTAG (Joint Test Action Group) interface control circuit defined in the IEEE 1149.1 standard is used, and switching for switching the external interface switching circuit 180 as one of commands to the control circuit. A command is provided. When this switching command is input from the external terminal 195, the interface control circuit 190 is configured to generate and control an interface switching control signal INC for the external interface switching circuit 180.
In FIG. 1, in addition to the module, a logic circuit (so-called user logic circuit) having a logic function requested by a user may be mounted as a module. Further, the number of scan paths provided in each of the modules 110 to 140 is not limited to one, and the number of scan paths may be provided for each module as necessary. When a plurality of scan paths are provided, the external interface switching circuit 180 performs interface switching for each scan path. If there are more external terminals 160 than the number of scan paths, these scan paths can be tested simultaneously.
FIG. 2 schematically shows each of the functional modules 110 to 140 constituting the system LSI shown in FIG. 1 while paying attention to the logical configuration thereof.
As shown in FIG. 2, each of the functional modules 110 to 140 includes a latch circuit or a flip-flop, and an output at a certain point in time is not determined only by the input signal at that time, depending on the input signal and the immediately preceding internal state. The sequential circuit 210 is determined, and a combinational circuit 220 such as a decoder or an arithmetic unit whose output at a certain time is determined only by the input signal at that time. In FIG. 2, reference numerals FF <b> 1 to FFn are attached to flip-flops that constitute the logic of the sequential circuit 210 and can constitute a shift register for a scan path.
FIG. 2 shows a state in which the flip-flops FF1 to FFn constitute a scan path shift register. 231 is a scan-in path for test data to the shift register, 232 is a scan-out path for data from the shift register, and 240 is an original input / output signal of the modules 110 to 140. The input / output signal 240 may be input to or output from the combinational circuit 220, but is generally input to the sequential circuit 210 that operates in synchronization with the clock signal, and the output signal is once latched in the flip-flop. In many cases, it is output at a predetermined timing. The scan-in path 231 and the scan-out path 232 are considered to constitute any of the scan paths 171 to 175 in FIG.
FIG. 3 shows a specific example of the flip-flops FF1 to FFn. As shown in the figure, each flip-flop has a double latch configuration of a master latch MLT and a slave latch SLT.
Among them, the master latch MLT has two data input terminals 301 and 303, an input terminal 302 of a clock CK1 that provides data latch timing to the data input terminal 301, and an input of a clock CK2 that provides data latch timing to the data input terminal 303. And a terminal 304. The master latch MLT is inputted to the data terminal 303 and NAND gates G1 and G2 which receive the data signal D inputted to the data terminal 301 and its inverted signal and the clock signal CK1 inputted to the clock terminal 302. NAND gates G5 and G6 that receive the data signal SIN and its inverted signal and the clock signal CK2 that is input to the clock terminal 304, and the output signals of these NAND gates G1, G2, G5, and G6 are input and the output terminals are mutually connected. It consists of NAND gates G3 and G4 cross-coupled to one of the input terminals of the other gate.
The data input terminal 301 of the master latch MLT receives the signal D from the preceding logic gate constituting the internal logic circuit, and the data input terminal 303 receives the signal SIN from the preceding flip-flop constituting the scan path. Is done.
On the other hand, the slave latch SLT includes two data input terminals connected to the output nodes N1 and N2 of the master latch MLT, a clock terminal 306 that provides data latch timing of the data input terminal, and one data output terminal 305. Prepare. The slave latch SLT receives NAND gates G7 and G8 that receive the output signal of the master latch MLT and the clock signal CK3 input to the clock terminal 306, and outputs the output signals of these NAND gates G7 and G8. The terminal is composed of NAND gates G9 and G10 which are cross-coupled to one of the input terminals of the other gate.
The output terminal 305 of the slave latch SLT is commonly connected to the input terminal of the subsequent logic gate constituting the internal logic circuit and the data input terminal of the subsequent flip-flop constituting the scan path. Even if connected in this way, by giving either of the clocks CK1 or CK2 to the master latch MLT at an appropriate timing, the signal from the preceding flip-flop on the scan path is taken into the master latch MLT during normal operation. Can be avoided.
In the flip-flop shown in FIG. 3, the output terminal Q for signals during normal operation and the output terminal SOUT for signals during a scan test are shared, but separate output terminals should be provided. It goes without saying.
FIG. 4A shows the clock signals CK1 to CK3 and the data signal SIN when the test data is scan-inputted to the flip-flops FFi (i = 1 to n) constituting the internal scan path and supplied to the internal logic circuit. In FIG. 4B, the clock signal CK1 to CK3 and the data signal D when the output (data D) of the logic gate in the internal logic circuit is fetched into the flip-flop FFi and the fetched data are scanned and output are shown in FIG. FIG. 4C shows the timing of the clock signals GK1 to CK3 and the data signal D when the output of the preceding logic gate is taken into the flip-flop FFi and output to the next logic gate in normal operation. It is shown.
When the test data is scan-inputted from the scan path to the flip-flop, as shown in FIG. 4A, first, the data SIN of the scan-in data input terminal 303 is taken into the master latch MLT with the clock CK2, and then the clock CK3. The data held in the master latch MLT is transferred to the slave latch SLT. By repeating this, the test data is successively shifted by the flip-flops FF1 to FFn on the scan path.
When the scan input of the test data is completed, the data is input to the original logic circuit, and the output changes. As shown in FIG. 4B, the output D is taken into the master latch MLT from the data input terminal 301 at the clock CK1, and then the data held in the master latch MLT is transferred to the slave latch SLT at the clock CK3. Thereby, the output of the logic gate in the internal logic circuit can be taken into the flip-flop from the data input terminal 301.
Next, the clocks CK2 and CK3 are alternately supplied to the flip-flops FF1 to FFn, thereby shifting the data taken in the flip-flops FF1 to FFn along the scan path. As a result, the operation result of the internal logic circuit based on the scan-in data can be output to the external terminal via the scan path.
On the other hand, during normal operation, logical operation can be performed by repeatedly taking in data at the data input terminal D at the timing shown in FIG. 4C and transferring data from the master latch MLT to the slave latch SLT.
FIG. 5 is a specific example of the external interface switching circuit 180 shown in FIG.
The external interface switching circuit 180 of this embodiment is composed of a plurality of selectors. FIG. 5 shows four selectors 411 to 414 corresponding to the two external terminals 161 and 162, but the number of selectors is not limited to four. Since the external terminals 161 and 162 shown in FIG. 5 are terminals that share the input and output terminals, two selectors are provided for each external terminal. Then, one selector is provided for each.
In the test, the selector 411 responds to the switching control signal INC,
(1) a test result output signal (scanout signal) from a scanout path (test signal output wiring) 402 coupled to the module 110 (CPU core);
(2) a test result output signal (scanout signal) from a scanout path (test signal output wiring) 408 coupled to each module 120 (130, 140), or
(3) An output signal from the signal wiring 403 coupled to the module 110 and an output signal that does not pass through the bus interface circuit 150 among the signal wiring 404 coupled to the module 110,
Optionally, it is provided for coupling to the external terminal 161.
On the other hand, the selector 411 is provided to output a normal output signal from the normal signal wiring 170 coupled to the bus interface circuit 150 to the external terminal 161 during normal operation.
The selector 412 receives a test input signal input from the external terminal 161 at the time of testing.
(4) As a scan-in signal, a scan-in path (test signal input wiring) 401 coupled to the module 110 (CPU core),
(5) As a scan-in signal, a scan-in path (test signal input wiring) 407 coupled to the module 120 (130, 140),
(6) Provided as a test signal to selectively supply the signal wiring 403 coupled to the module 110 and the signal wiring 404 coupled to the module 110.
On the other hand, the selector 412 is provided for inputting a normal input signal input from the external terminal 161 to the normal signal wiring 170 coupled to the bus interface circuit 150 during normal operation.
Therefore, the selectors 411 and 412 may be connected to scan-in paths and scan-out paths of a plurality of functional modules, as shown in FIG. It may be connected.
The selectors 413 and 414 are provided for the external terminal 162 and are coupled to the functional modules 130 or 140 other than the functional modules 110 and 120.
Although not shown in FIG. 5 to avoid complexity, the following is done.
That is, the selector 413 is
(7) a test result output signal (scanout signal) from a scanout path (test signal output wiring) coupled to the module 130 or 140;
(8) The output signal selected from the signal wiring (normal signal wiring corresponding to 403, 406, etc.) coupled to the module 110, 120, 130, or 140, and the module 110, 120, 130, or 140 Output signal that does not pass through the bus interface circuit 150 among signal wirings (signal wirings corresponding to 404, 405, etc.)
Optionally, it is provided for outputting to the external terminal 162.
On the other hand, the selector 413 is provided to couple a normal output signal from the normal signal wiring 170 coupled to the bus interface circuit 150 to the external terminal 162 during normal operation. That is, in this case, the selector 413 assigns a signal output function to the external terminal 162 so as to satisfy the function in the normal operation mode of the semiconductor integrated circuit of the embodiment. Therefore, the connection destination of the external terminal 162 is an arbitrary functional module selected from the modules 110, 120, 130, and 140.
The selector 414 receives a test input signal input from the external terminal 162 during testing.
(9) As a scan-in signal, to a scan-in path (test signal input wiring) coupled to the module 130 or 140, or
(10) As a test input signal, a normal input signal input from the external terminal 162 is connected to a signal wiring (signal wiring corresponding to 403, 406, etc.) coupled to the module 110, 120, 130, or 140, and , To signal wiring (signal wiring corresponding to 404, 405, etc.) coupled to the module 110, 120, 130 or 140,
Optionally provided for feeding.
On the other hand, the selector 414 is provided to supply a normal signal input from the external terminal 162 to the normal signal line 170 coupled to the bus interface circuit 150 during normal operation. That is, in this case, the selector 414 assigns a signal input function to the external terminal 162 so as to satisfy the function in the normal operation mode of the semiconductor integrated circuit of the embodiment. Therefore, the connection destination of the external terminal 162 is an arbitrary functional module selected from the modules 110, 120, 130, and 140.
In FIG. 5, 421 is an output buffer circuit for supplying the output signal of the selector 411 to the external terminal 161, 422 is an input buffer circuit for supplying the signal input from the external terminal 161 to the selector 412, and 423 is the output of the selector 413. An output buffer circuit 424 for supplying a signal to the external terminal 162 and an input buffer circuit 424 for supplying a signal input from the external terminal 162 to the selector 414.
The selectors 411 to 414 have their switching operations controlled by a plurality of switching control signals INC from the JTAG interface control circuit 190. By the switching operation by the selectors 411 to 414, five input / output modes as shown in FIGS. 6A to 6E can be achieved. Each mode will be described below.
(A) A normal operation mode in which the input / output terminals of the module 110 (CPU core) and the peripheral module 120 are connected to the external terminals 161 and 162 via the bus interface circuit 150. This mode is achieved by the normal operation of the selectors 411-414.
(B) A single CPU test mode in which the input / output terminals of the module 110 (CPU core) are directly connected to the external terminals 161 and 162 to perform input / output to test the function of the module. This mode is achieved by the operations (3), (6), (8) and (10) of the selectors 411 to 414.
(C) A single peripheral module test mode in which the input / output terminals of the peripheral module 120 (130, 140) are directly connected to the external terminal 161 (162) to perform input / output to test the function of the module. This mode is achieved by the operations (8) and (10) of the selectors 413 and 414.
(D) CPU shift scan test mode in which scan paths 401 and 402 of the module 110 (CPU core) are directly connected to the external terminal 161 to perform scan-in and scan-out of test signals. This mode is achieved by the operations (1) and (5) of the selectors 411 and 412.
(E) Peripheral module shift scan test mode in which the scan paths 407 and 408 of the peripheral module 120 (130 and 140) are directly connected to the external terminals 161 and 162 to perform scan-in and scan-out of test signals. This mode is achieved by the operations (2), (5), (7) and (9) of the selectors 411 to 414.
FIG. 7 shows a specific example of the JTAG interface control circuit 190 shown in FIG.
The JTAG interface control circuit 190 is a control circuit that achieves an interface for an internal shift scan test and a boundary scan test circuit defined in the IEEE1149.1 standard. The control circuit 190 is a command / data input / output circuit 510 serving as a TAP (Test Access Port) for taking in test data and commands input serially from the outside and serially outputting test result data from a module in the chip. A TAP controller 520 that controls the input / output circuit 510, and a test control unit 530 that decodes an instruction (command) fetched by the command / data input / output circuit 510 and performs test control corresponding to the instruction. The
The TAP controller 520 is connected to three dedicated external terminals 501 to 503, and inputs a test mode select signal TMS, a test clock TCK, and an asynchronous reset signal TRST for designating a test mode from these terminals 501 to 503, respectively. It is configured to be possible. The TAP controller 520 forms a control signal 5201 for controlling the registers 511 to 515 and the multiplexer 516 in the command / data input / output circuit 510 based on the signal levels of these signals TMS, TCK and TRST. Although not particularly limited, the TAP controller 520 is configured to switch the test mode every time one pulse of the test mode select signal TMS is input.
The command / data input / output circuit 510 includes a bypass register 511 used when shifting test data from the input port terminal 504 to the output port terminal 505, a shift register 512 for performing serial / parallel conversion of input / output data, Instruction register (SDIR) 513 for storing commands for controlling the test method, device ID register (IDCODE) 514 for setting a chip-specific manufacturing identification number, and data used for transmitting a specific signal to each module A register (SDDR) 515, a multiplexer 516 (MUX) for switching a path between the bypass register 511 and the shift register 512, and the like.
Further, the command / data input / output circuit 510 is provided with an input terminal 504 for command or data TDI and an output terminal 505 for test result data TDO, and the input test data TDI is received via the shift register 512. It is supplied to the registers 513 to 515. Further, the registers 513 to 515 in the command / data input / output circuit 510 are configured to be able to store values from each module in the chip via the signal line 540.
In the JTAG standard, some essential instructions are prepared as instructions set in the instruction register 513, but some other optional instructions can be provided. In this embodiment, a switching command for switching control of the external interface switching circuit 180 is provided as one of the option instructions. When this switching command is input from the data input terminal 504 to the command / data input / output circuit 510, it is stored in the instruction register 513, and the command decoder 531 decodes this command. The test mode determination circuit 532 determines the type of test mode and which module test is executed from the decoding result of the command data 531, and outputs, for example, the switching control signal ING of the external interface switching circuit 180.
In addition to the command decoder 531 and the test mode determination circuit 532, the test control unit 530 includes a boundary scan control circuit 533 that controls a boundary scan campus for testing the exchange of signals with other semiconductor integrated circuits, and a shift scan. Test circuit for generating test clock signals and control signals such as scan clock signals CK2 and CK3 of the flip-flops (FIG. 3) constituting the scan path and clock signal CK1 for taking in monitor signals at the time of testing 534 is provided.
Although not described in the embodiment of FIG. 1, when the semiconductor integrated circuit has a function of performing a boundary scan test using the control function of the boundary scan control circuit 533, for example, the boundary is switched in the external interface switching circuit 180. A shift register constituting the scan path is provided.
FIG. 8 shows a modification of the above-described embodiment, in which a JTAG interface control circuit 190 is integrally provided in a module 110 (CPU core). By configuring in this way, once such a module with a built-in interface control circuit is designed, it is registered in a database, etc., and this module is used when developing other system LSIs to control the interface. The time and effort for designing the circuit can be saved. The module in which the interface control circuit is provided integrally is not limited to the CPU core, and may be any peripheral module. In particular, a module that is frequently used when developing a system LSI is most desirable.
FIG. 9 shows another embodiment of a system LSI to which the present invention is applied. In this embodiment, in addition to the scan paths (401, 402) inside the module, signals around the module, that is, signals (403, 404) input / output to / from the module via external terminals and signals (803) between the modules are displayed. A flip-flop 801 for latching is provided, and these are connected in series to provide a scan path (802) for scanning in a test signal or scanning out a monitor signal. The signal path can be switched.
Note that the scan path control of the signals around the module can be performed by using the function of the boundary scan control circuit 533 shown in FIG. The scan path inside the module cannot monitor the output signal of the logic gate subsequent to the flip-flop constituting the scan path, but a scan path capable of monitoring the signals around the module is provided as shown in FIG. Thus, a more reliable test can be performed. When this embodiment is applied in combination with the embodiment of FIG. 1, the flip-flop that latches the signals on the signal paths 403 and 404 in FIG. A campus may be provided.
The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, in the above embodiment, the scan-in data at the time of the shift scan test is input from the external terminal 160 to each scan path via the external interface switching circuit 180. However, a test signal such as a random pattern generation circuit is provided inside the chip. It is also possible to provide a circuit for generating the signal and to input a test signal to each scan path therefrom.
As an interface control circuit, it is also possible to control an external interface switching circuit using a dedicated interface control circuit instead of the JTAG interface according to the IEEE 1149.1 standard. Further, instead of having an interface control circuit, a test command that can be executed by the central processing unit is incorporated in advance, and the central processing unit or the test control circuit is executed by executing the command or in combination with a control register or the like. However, it is also possible to control the external interface switching circuit.
Industrial applicability
In the above description, the invention made mainly by the present inventor has been explained by taking the microprocessor or single chip microcomputer as the background as an example. However, the present invention is not limited to this and is widely applied to LSIs incorporating a plurality of modules. Can be used.
The invention's effect
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
That is, according to the present invention, the development period when a system LSI is configured using a plurality of functional modules can be shortened. In addition, since the external interface switching circuit connects the test input / output terminals of the module to the external terminals during the test operation, each module can be tested without increasing the number of external terminals.
[Brief description of the drawings]
FIG. 1 is a block diagram of an embodiment of a preferred semiconductor integrated circuit to which the present invention is applied.
FIG. 2 is a conceptual diagram showing a schematic configuration of functional modules constituting the semiconductor integrated circuit.
FIG. 3 is a logical configuration diagram illustrating a specific example of a flip-flop capable of configuring a shift scan type test shift register.
FIG. 4 is a timing chart showing the operation timing of the shift scan flip-flop.
FIG. 5 is a schematic configuration diagram showing the relationship between the configuration of the external interface switching circuit and the functional modules.
FIG. 6 is an explanatory diagram showing a signal path switching state in a semiconductor integrated circuit to which the present invention is applied.
FIG. 7 is a block diagram illustrating a configuration example of the JTAG interface control circuit.
FIG. 8 is a block diagram showing another embodiment of the present invention.
FIG. 9 is an explanatory diagram showing an example of a method for observing signals between functional modules in a semiconductor integrated circuit to which the present invention is applied.

Claims (4)

A test terminal to which commands are supplied serially;
A test control circuit coupled to the test terminal for supplying a control signal in response to the command;
A functional module having a test data input terminal, a test data output terminal, and a plurality of signal terminals;
A bus interface circuit having an input coupled to the plurality of signal terminals;
A first selector having an output coupled to the test data input terminal and an output coupled to the bus interface circuit; an input coupled to the test data output terminal; and an input coupled to the bus interface circuit. A switching circuit including a second selector,
An external terminal coupled to the input of the first selector and the output of the second selector,
The first selector is responsive to the control signal to connect the external terminal to an output coupled to the test data input terminal;
Said second selector, a semiconductor integrated circuit connected in response to the control signal, the input that will be coupled to the test data output terminal to the external terminals. A test terminal to which commands are supplied serially;
A test control circuit coupled to the test terminal for supplying a control signal in response to the command;
A first functional module having a first test data input terminal, a first test data output terminal, and a plurality of first signal terminals;
A second functional module having a second test data input terminal, a second test data output terminal, and a plurality of second signal terminals;
A bus interface circuit having a first input coupled to the plurality of first signal terminals and a second input coupled to the plurality of second signal terminals;
A first selector having a first output coupled to the first test data input terminal and a second output coupled to a first input of the bus interface circuit; and a first selector coupled to the first test data output terminal. A second selector having one input and a second input coupled to the first output of the bus interface circuit; a third output coupled to the second test data input terminal; and a second input of the bus interface circuit. A fourth selector having a fourth output coupled, a third input coupled to the second test data output terminal, and a fourth input coupled to the second output of the bus interface circuit; A switching circuit including:
A first external terminal coupled to the input of the first selector and the output of the second selector;
A second external terminal coupled to the input of the third selector and the output of the fourth selector,
In response to the control signal, the first selector connects the first external terminal to the first output,
In response to the control signal, the second selector connects the first input to the first external terminal,
In response to the control signal, the third selector connects the second external terminal to the third output,
The fourth selector connects the third input to the second external terminal in response to the control signal.
Semiconductor integrated circuit. A first functional module having a first test data input terminal, a first test data output terminal, and a plurality of first signal terminals;
A second functional module having a second test data input terminal, a second test data output terminal, and a plurality of second signal terminals;
A bus interface circuit having a first input coupled to the plurality of first signal terminals and a second input coupled to the plurality of second signal terminals;
An external terminal,
A first mode for coupling the first test data input terminal and the first test data output terminal to the external terminal; and a second mode for coupling the second test data input terminal and the second test data output terminal to the external terminal. A mode, a third mode for coupling the plurality of first signal terminals to the external terminal, a fourth mode for coupling the plurality of second signal terminals to the external terminal, and an output of the bus interface circuit for the external A switching circuit having a fifth mode coupled to the terminal;
A semiconductor integrated circuit. A test terminal to which commands are supplied serially;
A test control circuit coupled to the test terminal and providing a control signal in response to the command;
The switching circuit is controlled in the first to fifth modes according to the control signal .
The semiconductor integrated circuit according to claim 3 .

Images