JP2658894B2 - Scan path circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scan path circuit for facilitating test.

[0002]

2. Description of the Related Art A flip-flop in an integrated circuit is connected like a shift register to form a scan path, a test signal is input from an external terminal, and a combinational logic (Combinat) is formed.
ionalLogic) A method of reading out the operation result of the circuit to facilitate the test is called a scan path method.

FIGS. 3 to 5 are block diagrams each showing an example of a conventional scan path circuit.

In FIGS. 3 to 5, reference numerals 1a to 1c denote a plurality of shift registers # 1 to # 1 constituting a scan path circuit.
#N, 2 is a scan mode switching control terminal for controlling switching between the normal mode and the scan mode, 3 is a clock input terminal for shifting data of the shift register, 4 is a scan input terminal, 5 is a scan output terminal. is there. Note that the shift registers # 1 to #n are also called scan registers.

The scan path circuit shown in FIG. 4 is provided with a plurality of scan input terminals 4a to 4c and a plurality of scan output terminals 5a to 5c corresponding to a plurality of shift registers # 1 to #n. 3 is different from that of FIG.

FIG. 5 shows a configuration of a scan path circuit proposed in Japanese Patent Application Laid-Open No. Hei 1-217278, in which a demultiplexer 8 for distributing data input from a scan input terminal 4 to each shift register, A multiplexer 9 for selecting one of the outputs of the shift register and outputting it to the scan output terminal 5;
And a plurality of shift registers # 1 to # 3 based on the signal input to
A decoder 7 for generating a signal for setting only one of #n to the shift mode is added.

Next, the operation of these three conventional scan path circuits will be described.

In FIG. 3, during normal operation, the scan mode switching control terminal 2 is made inactive, and the shift registers 1a to 1c are used as only registers separated from the scan path. At this time, the clock input terminal 3, the scan input terminal 4, and the scan output terminal 5 are not used.

However, when the system clock and the scan clock are shared, the clock input terminal 3 is used even during normal operation.

At the time of a scan path test, the scan mode switching control terminal 2 is activated, serial data is input from the scan input terminal 4 to the shift register, and data is written to the shift register.
The data held in the shift register is output from the scan output terminal 5 as serial data by the shift operation.

As described above, since data can be arbitrarily written to and read from the shift registers # 1 to #n in the scan path circuit, the test is facilitated. That is, at the time of the scan path test, input data can be supplied to the combinational logic circuit (not shown) and the output of the combinational logic circuit can be read out via the shift register # 1 in FIG. Are controllable, and each output of the combinational logic circuit is observable, thereby facilitating the test of the integrated circuit.

In the scan path circuit of FIG. 4, basically the same operation as that of the scan path circuit of FIG. 3 is performed, but in FIG. 4, a chain of scan path circuits (also referred to as a "scan chain"). 3 in that a plurality of scan input terminals 4a to 4c and a plurality of scan output terminals 5a to 5c are provided corresponding to a plurality of chains.

In the scan path circuit shown in FIG. 4, when data is set in, for example, the shift register # 1 and the data of the other shift registers # 2 to #n are held as they are during the test, only the scan mode switching control terminal 2a is connected. Clock input terminal 3 with clock and data as active
When it is desired to input data from the scan input terminal 4a and read only the data of the shift register # 1, only the scan mode switching control terminal 2a is activated and a clock is supplied to the clock input terminal 3 to thereby provide a scan output terminal. The data of the shift register # 1 is output from 5a.

Next, in the scan path circuit of FIG. 5, the number of input / output terminals and the number of test terminals such as scan mode switching control terminals provided in the scan path circuit of FIG. 4 are reduced. The purpose is to reduce the number of input terminals and output terminals one by one, and the signals are distributed to a plurality of shift registers by the demultiplexer 8 and the multiplexer 9.

In the scan path circuit of FIG. 5, since the coded shift mode switching input signal is decoded and used by the decoder 7, the number of terminals is reduced, and data is written and read one by one, and the multiplexer and the multiplexer are used. Since the data is distributed to a plurality of shift registers by the demultiplexer, data can be written and read for each shift register.

[0016]

In the above-described conventional scan path circuit, the configuration as shown in FIG. 3 has a problem that the number of test patterns increases because all shift registers are serially connected. Even when reading data from only one shift register, shift clocks must be input from the clock input terminal 3 by the number of stages of all shift registers, and the number of test patterns increases, resulting in poor efficiency.

The scan path circuit of FIG. 4 has a configuration in which a plurality of chains are arranged in parallel, and can write and read data individually for each shift register as compared with the configuration of FIG. Therefore, it is possible to create an efficient test pattern, and there is an advantage that the number of serial test patterns is reduced. However, there is a very important problem that the number of test terminals increases.

The scan path circuit shown in FIG.
Although the configuration is similar to that described above, since there is only one data input / output terminal, many serial test patterns are required, and additional circuits such as decoders, demultiplexers, and multiplexers are required. There are problems such as an increase in circuit scale and an increase in hardware overhead.

Therefore, an object of the present invention is to solve the above-mentioned problems, reduce the number of scan path test patterns, and
An object of the present invention is to provide a scan path circuit in which the number of test input / output terminals is minimized.

[0020]

In order to achieve the above-mentioned object, the present invention provides a method in which a signal is inputted from one scan input terminal.
Scan input data is transferred to multiple scan paths.
Scan output from scan output terminal via shift register
In a scan path circuit for outputting data,
The multiple shift registers that make up the
Scan data output from the stage shift register is
A plurality of shift registers arranged in parallel after the preceding shift register
Are input in parallel to the shift register of
Shift operation of multiple shift registers
A plurality of shift registers that output in parallel and are arranged in parallel in the last stage
Multiple scan output terminals each connected to the output of the
A scan path circuit configured to output scan output data in parallel from the slaves .

In the scan path circuit according to the present invention, a plurality of shift registers arranged in parallel at the subsequent stage are provided.
But each to test for circuit group of the same functions, is characterized in that it is configured.

In a preferred embodiment of the scan path circuit of the present invention, one scan input terminal, a plurality of scan output terminals, a plurality of shift registers forming the scan path circuit, and the shift registers are shifted. It includes a clock input terminal for a scan mode switching control terminal, and in the scan mode, the one scan data input from the scan input terminal, after passing through the at least one shift register, arranged in parallel with each other The process branches to a plurality of shift registers arranged in parallel until reaching the plurality of shift registers of the final stage, and the plurality of scan output terminals are respectively connected to outputs of the plurality of shift registers of the last stage. And a plurality of shift registers arranged in parallel with each other It is configured to perform a test of the physical circuit unit.

[0023]

According to the present invention, the scan input terminal of the scan path circuit is serially input to the shift register as one terminal, and is connected to shift registers arranged in parallel at the subsequent stage of the cyst register. By having a configuration that includes a plurality, the number of test patterns is reduced and the number of test terminals is significantly reduced.
Further, a parallel test of a group of circuits to be tested can be performed.

[0024]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a configuration of an embodiment of a scan path circuit according to the present invention. In FIG. 1, terminals and circuit elements having the same functions as those in FIGS. 3 to 5 are given the same reference numerals.

As shown in FIG. 1, in this embodiment,
The scan path is composed of a plurality of shift registers # 1 to #n, and the scan input SIN is the scan input terminal 4
, And a plurality of scan outputs Sout2 to Soutn are output from scan output terminals 5b to 5c corresponding to the shift registers # 2 to #n, respectively.

The output of the shift register # 1 is commonly input to a plurality of shift registers # 2 to #n.

The shift operation in the shift registers # 1 to #n is executed by the clock signal (CLOCK) input from the clock input terminal 3 when the scan mode switching control terminal 2 is activated.

In this embodiment, with such a configuration,
When there are a plurality of circuit groups having the same function to be tested in the integrated circuit (referred to as "same function group" and preferably composed of combinational logic circuit units), a shift register # is used for each test of the same function group. Two
The same function group can be tested in parallel using the shift register #n.

FIG. 2 shows the same function group B in the integrated circuit.
In the case where a plurality of # 1 to B # n-1 exist, a configuration example of a scan chain for performing a scan path test according to the present embodiment is shown. In the figure, the same function groups B # 1 to B # n
-1 is an independent circuit group having the same function, and data is set and read via shift registers # 2 to #n, respectively. The circuit group A is a circuit group (preferably a combinational logic circuit unit) having a different function from the circuit groups B # 1 to B # n-1, and is connected via a shift register # 1 connected to the scan input SIN. Data setting and reading are performed.

In this embodiment, the number of test patterns required for the scan path is (number of patterns to shift register # 1) + (number of patterns to shift register # 2).

On the other hand, the number of test patterns in the case of the conventional example of FIG. 3 is (the number of patterns of the shift register # 1).
+ (The number of patterns to the shift register # 2) +... + (The number of patterns to the shift register #n)
Compared with the conventional example of FIG. 3, the number of test patterns is greatly reduced.

For example, if shift registers # 1 to #n have 10
(N = 10), and one shift register is 100
In the case of the configuration of a chain of flip-flops, the conventional example of FIG. 3 requires a basic test pattern of 10 × 100, but in the present embodiment, it is greatly reduced to 2 × 100, and the test time is greatly reduced. It greatly contributes to shortening.

In comparison with the conventional example of FIG. 4 in which all scan paths are configured in parallel, in this embodiment, the number of scan input terminals and the number of scan mode switching control terminals are both reduced to one. This has the effect that the number of input terminals (input terminals) can be minimized. Further, in comparison with the conventional example of FIG. 5, the present embodiment does not require circuits such as a demultiplexer and a multiplexer.

Although the present invention has been described with reference to the above embodiments, the present invention is not limited to the above embodiments but includes various embodiments according to the principle of the present invention. For example, a mode in which a plurality of shift registers are further serially connected after the shift register # 1, and output is connected to a plurality of scan output terminals, respectively, to branch to a plurality of shift registers arranged in parallel at the last stage, Alternatively, a branch from the output of one shift register to a plurality of shift registers arranged in parallel may be provided in multiple stages on the way from the shift register # 1 to the shift register arranged in parallel in the last stage. The present invention includes such a configuration.

[0036]

As described above, according to the present invention, the scan input terminal of the scan path circuit is a single terminal and is serially input to the shift register, and the output of the shift register branches at the subsequent stage and is parallel to each other. , The number of test patterns and the number of test terminals can be effectively reduced.

Further, according to the present invention, in the integrated circuit, the same function group to be tested can be simultaneously tested in parallel by using a plurality of shift registers arranged in parallel with each other, This achieves a significant reduction in the number of test patterns and a reduction in test time.

Further, according to the present invention, the number of test terminals can be reduced without increasing the circuit scale, and a parallel test of a functional block to be tested inside an integrated circuit can be performed.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of a scan path circuit according to the present invention.

FIG. 2 is a diagram showing a configuration of a scan chain in the scan path circuit according to the present invention.

FIG. 3 is a diagram illustrating an example of a conventional scan path circuit.

FIG. 4 is a diagram showing another example of a conventional scan path circuit.

FIG. 5 is a diagram showing still another example of the conventional scan path circuit.

[Explanation of symbols]

 1a to 1c Shift register constituting scan circuit 2, 2a to 2c Scan mode switching control terminal 3 Clock input terminal 4, 4a to 4c Scan input terminal 5, 5a to 5c Scan output terminal 6 Shift mode switching input terminal 7 Decoder 8 Multiplexer 9 Multiplexer

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-3-152487 (JP, A) JP-A-63-243890 (JP, A) JP-A-1-307853 (JP, A) JP-A 57-152 15296 (JP, A) JP-A-62-196729 (JP, A) JP-A-62-49272 (JP, A) JP-A-4-221178 (JP, A) JP-A-4-220576 (JP, A) JP-A-4-263200 (JP, A)

Claims (3)

(57) [Claims] A scan input from one scan input terminal.
Scan input data can be divided into multiple shift paths
Scan output data from the scan output terminal
In a scan path circuit that outputs data, a plurality of shift registers constituting the scan path are provided.
Scan data output from the previous shift register.
Data is arranged in parallel after the preceding shift register.
Input to the plurality of shift registers in parallel,
Simultaneous shift operation of multiple shift registers arranged in parallel
And output in parallel, output to multiple shift registers arranged in parallel at the last stage.
Scan from multiple connected scan output terminals.
A scan path circuit configured to output scan output data in parallel . 2. A plurality of shift registers arranged in parallel in the subsequent stage.
Register, respectively to test for circuit group of the same function, the scan path circuit according to claim 1, characterized in that it is configured. 3. A scan input terminal, a plurality of scan output terminals, a plurality of shift registers forming a scan path circuit, a clock input terminal for performing a shift operation of the shift registers, and a scan mode switching control terminal. When provided with, in the scan mode, the one scan data input from the scan input terminal, after passing through the at least one shift register, through to a plurality of shift registers of the last stage which is arranged in parallel with each other In the parallel distribution
A plurality of shift registers arranged in parallel, and the plurality of scan output terminals are respectively connected to the outputs of the plurality of shift registers in the final stage, and the plurality of shift registers arranged in parallel with each other have combination logic of the same function. scan path circuit, characterized in that it is configured to perform test of the circuit unit.