JP2003076576A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To overcome problems wherein terminals for test are increased or generating method of data for test becomes complicated and control speed in the case of the test is lowered by increase of transfer quantity of test data when a plurality of semiconductor cores 4, 5 individually having test circuits are integrated into one semiconductor device. SOLUTION: An instruction code is transferred to the semiconductor core 4 specified by referring to an additional bit that specifies the semiconductor core added to the instruction code as it is and the instruction code is transferred to the semiconductor core 5 which is not specified by replacing the instruction code with the one which does not effect an operation of the semiconductor core 5 in a data converting part 28. Thus, only the specified semiconductor core 4 can be controlled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a plurality of semiconductor devices each provided with a test circuit are integrated into one system LSI.

[0002]

2. Description of the Related Art In recent years, the number of semiconductor cores such as processors having on-chip test circuits for software debugging and on-board mounting tests has been increasing, and these test circuits have a state transition type such as JTAG method. Controlled by the test terminal. Further, a semiconductor device called a system LSI in which a plurality of semiconductor cores each having these test circuits are integrated into one chip has been developed. At that time, the terminals for controlling the respective test circuits are connected by a serial chain and only one set of test terminals is provided as a terminal of the system LSI, or a plurality of test terminals corresponding to the number of semiconductor cores are provided, or the test terminals are provided. Had added terminals for semiconductor core selection in one set. Usually, a semiconductor device and a test device for the semiconductor device are manufactured first with a single semiconductor core, and then a semiconductor device and a test device for the semiconductor device that integrate a plurality of semiconductor cores are manufactured.

FIG. 9, FIG. 10 and FIG. 11 are configuration diagrams showing the configuration of a conventional semiconductor device and connection with an external test device.
9 shows a configuration of a semiconductor device connected by a serial chain, FIG. 10 shows a configuration of a semiconductor device having a plurality of sets of test terminals, and FIG. 11 shows a configuration of a semiconductor device to which terminals for selection are added.

In FIG. 9, 1 is an external test device, 2 is a test input terminal, 3 is a test output terminal, 4 and 5 are semiconductor cores each having a test circuit, and 6 is a mounting test on a board. Test circuit, 7 is a combination of the semiconductor cores 4, 5 and the test circuit 6, and a set of test terminals 2, 3
It is a semiconductor device provided with. The external test apparatus 1 is connected to the test input terminal 2 and the test output terminal 3, and the test input terminal 2 is connected to the input 101 of the test circuit included in the semiconductor core 4 and the output 102 of the test circuit included in the semiconductor core 4. Is input to the test circuit of the semiconductor core 5,
The output 103 of the test circuit included in the semiconductor core 5 is connected to the input of the test circuit 6, and the output 104 of the test circuit 6 is connected to the test output terminal 3 in a chain.

The operation of the semiconductor device configured as described above will be described focusing on the flow of test input data and output data. In the following description, the test terminal is a JTAG system, and the test circuit of the semiconductor core 4 and the semiconductor core 5 has an instruction code length of 4 bits and a data length of 16 bits for an instruction code having a binary value of 1010. To do. In the JTAG method, the bypass instruction is defined as an instruction that does not affect the operation of the semiconductor cores 4 and 5. When the instruction code length is 4 bits, the binary code of the bypass instruction is 1111 and the data length is 1 bit. Stipulated.

Since the registers in the test circuits of the semiconductor core 4 and the semiconductor core 5 are connected in a serial chain, when the semiconductor core 4 is controlled, the external test device 1 is used.
As in 2, input data in which the instruction code is connected to the 8-bit code 1001 and the data is connected to the 17-bit data 1002 is generated and transferred. At this time, it is necessary to arrange the instruction code and the data of the semiconductor core 4 which is the farthest connected to the test input data terminal at the head side to connect the data, and the instruction code to the uncontrolled semiconductor core 5 and the test circuit 6 Will set bypass instructions respectively.

When the input data connected as described above is input, the semiconductor device 7 has the output data of the semiconductor core 4 connected after the output data of the test circuit 6 and the bypass register of the semiconductor core 5 as shown in FIG. Output data 100
3 is output. The output data 1004 from the instruction register is output before the output data 1003, but normally, the output of the instruction register has no meaning. Therefore, the external test apparatus 1 needs to extract 16 bits of output data of the semiconductor core 4 from the output 17 bits of output data 1003.

In FIG. 10, 8, 9 and 10 are external test devices, 4 and 5 are semiconductor cores each having a test circuit, 6 is a test circuit for mounting test on a board, and 11 is a semiconductor core 4. Test input terminal, 1
2 is a test output terminal for the semiconductor core 4, 13 is a test input terminal for the semiconductor core 5, 14 is a test output terminal for the semiconductor core 5, 16 is a test input terminal for the test circuit 6, and 17 is for the test circuit 6. A test output terminal 17 is formed by integrating the semiconductor cores 4 and 5 and the test circuit 6 into three sets of test terminals 11, 12, 13, and 1.
It is a semiconductor device including 4, 15, and 16. The external test device 8 is connected to the input 101 and the output 105 of the semiconductor core 4 through the test terminals 11 and 12, and
Is the input 1 of the semiconductor core 5 through the test terminals 13 and 14.
06 and the output 107, the external test equipment 10 receives the input 108 of the test circuit 6 through the test terminals 15 and 16.
And output 104.

The operation of the semiconductor device configured as described above will be described. Since the test terminals exist independently for each of the semiconductor cores 4, 5 and the test circuit 6, the dedicated external test device is connected to each of the semiconductor cores 4, 5 and the test circuit 6, respectively. It can be controlled in exactly the same manner as in the case of a single semiconductor device. However, the provision of independent test terminals means that the number of test terminals increases in proportion to the number of integrated semiconductor cores.

In FIG. 11, reference numeral 18 denotes an external test device, 1
Reference numeral 9 is a test input terminal, 20 is a test output terminal, 4 and 5 are semiconductor cores each having a test circuit, 6 is a test circuit for mounting test on a board, and 21 is test terminals 19 and 20. Semiconductor core 4 or semiconductor core 5
Alternatively, a selector circuit for connecting to the test circuit 6, 2
Reference numeral 2 is a selection terminal for controlling the selector circuit, and 23 is a semiconductor device that integrates the semiconductor cores 4 and 5, the test circuit 6 and the selector circuit 21 and includes a pair of test terminals 19 and 20 and a selection terminal 22. .

The operation of the semiconductor device configured as described above will be described. The selector circuit 21 includes an input 101 and an output 105 of the semiconductor core 4, an input 106 and an output 107 of the semiconductor core 5, or an input 108 of the test circuit 6.
A pair of inputs and outputs is selected from the output 104 and the output 104 and connected to the test input terminal 19 and the test output terminal 20. Once the semiconductor core to be connected to the test input terminal 19 and the test output terminal 20 is determined by the selection terminal 22, the control method of the test terminals other than the selection terminal 22 is the semiconductor core 4 and the semiconductor. The core 5 and the test circuit 6 can be controlled in exactly the same manner as in the case of a single semiconductor device.
However, since it is not necessary to control the selection terminals in a semiconductor device in which the semiconductor core 4 and the semiconductor core 5 are single units, the external test apparatus 18 also includes the selection terminals 22 that increase according to the number of integrated semiconductor cores. New control is required.

[0012]

As described above, in the conventional serial chain connection configuration, the input data for controlling the test circuit of each semiconductor core is connected in consideration of the order of the semiconductor cores to be connected. Therefore, the method of generating test data is complicated, the amount of change of the external test equipment is large, and the length of data to be transferred at one time becomes long, so that the control speed of the test circuit also decreases. .

Further, the conventional configuration having a plurality of sets of test terminals has a problem that the number of test terminals increases in proportion to the number of semiconductor cores.

Further, in the conventional configuration in which the selection terminal is added, the selection terminal increases in accordance with the number of semiconductor cores to be connected, and the selection terminal also needs to be controlled. There was a problem that it would increase.

The present invention solves the above-mentioned problems, and provides a semiconductor device which does not increase the number of terminals, does not use a complicated external test device, and reduces the control speed of a test circuit. To aim.

[0016]

A semiconductor device according to claim 1, wherein two or more semiconductor cores each having a test circuit individually and input data are input and output to a test circuit provided in the semiconductor core. Data that transfers the input data to the semiconductor core specified by the input data and converts the input data to the semiconductor core not specified by the input data so as not to affect the operation of the semiconductor core. The converter includes a conversion unit and a circuit which inputs the input data, inputs the data output of the test circuit included in the semiconductor core, and outputs only the data output of the semiconductor core designated by the input data.

According to another aspect of the semiconductor device of the present invention, the data conversion unit receives the input data input from the test terminal, and the data conversion unit does not affect the operation of those semiconductor cores that are not designated. Since the code is replaced and the input instruction code is transferred to the designated semiconductor core as it is, only the designated semiconductor core is controlled. In addition, for example, a circuit such as a test circuit for mounting test on the board outputs the control result of the specified semiconductor core to the test terminal, so effective input / output control can be performed only for the specified semiconductor core. it can.

Therefore, by providing a data conversion section for converting an instruction code to an unspecified semiconductor core into an instruction code which does not affect the operation of the semiconductor core, the semiconductor core alone can be provided without increasing the number of test terminals. Without making complex changes to external test equipment for
An external test device for a semiconductor device in which a plurality of semiconductor cores are integrated can be developed, and a semiconductor device that can be tested in a test time equivalent to that of a single semiconductor core can be provided.

According to a second aspect of the present invention, there is provided a semiconductor device according to the first aspect, further comprising an external test device for generating input data or a synchronization control section for outputting control signals to a plurality of semiconductor cores simultaneously or individually by input from the semiconductor cores. It is further equipped.

According to the semiconductor device of the second aspect, in addition to the same effect as that of the first aspect, it is possible to simultaneously control a plurality of semiconductor cores, and further, based on the output of one semiconductor core, another semiconductor core can be controlled. A semiconductor device capable of controlling a core can be provided.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. The JTAG method will be described as an example of the test terminal control method.

FIG. 1 shows the structure of a semiconductor device according to the first embodiment of the present invention. 2 in FIG.
Reference numeral 4 is an external test device, 25 is a test input terminal, 26 is a test output terminal, 4 and 5 are semiconductor cores each having a test circuit individually, and 27 is data of a semiconductor core designated as a mounting test on a board. A test circuit that outputs only the output to the terminal, 28 is a data conversion unit that converts the input data to the semiconductor cores 4 and 5, 29 is a combination of the semiconductor core 4, the semiconductor core 5, the test circuit 27, and the data conversion unit 28. A semiconductor device having a set of test terminals.

The test circuit 27 is integrated with the semiconductor core 4,
5 is a test circuit provided with an instruction register having an instruction code length obtained by adding an additional bit length to the longest instruction register length in 5. 2A is a schematic block diagram of the data conversion unit 28, and FIG. 2B is a detailed block diagram of the data conversion unit 28. In FIG. 2, 30 is a conversion circuit for converting the input to the semiconductor core 4, 31 is a conversion circuit for converting the input to the semiconductor core 5, 32 is a conversion circuit 29, a conversion circuit by an additional bit added to the head of the instruction code. A control circuit for controlling 30. In FIG. 2B, 33 is a shift register for shifting in additional bits, 3
4 is a decoder that decodes all bits of the shift register 33, 35 is a latch that holds the output value for the conversion circuit 30 of the decoder 34, 36 is a latch that holds the output value for the conversion circuit 31 of the decoder 34, 37 is a latch 35, 36 is a latch timing control circuit for generating a latch clock to 36.

The operation of the semiconductor device of the present embodiment configured as described above will be described below focusing on the flow of test input data and output data.

First, the external test apparatus 24 for generating input data adds an additional bit corresponding to the semiconductor core 4 to be controlled to the head of the instruction code as shown in FIG. 3, and inputs it to the data conversion unit 28 and the test circuit 27. . Here, when the additional bit is 01 in binary, the semiconductor core 4 is designated,
When the additional bit is 10 in binary, the semiconductor core 5 is designated, and when the additional bit is 00 in binary, the test circuit 2
Suppose 7 is specified. In the data conversion unit 28, the instruction code with additional bits is simultaneously input to the control circuit 32 and the conversion circuits 30 and 31, but the control circuit 32 converts the control signals 109 and 110 into the conversion circuit 3 according to the value of the additional bits at the head.
The conversion circuits 30 and 31 are controlled so as to output to 0 and 31 and not convert to the designated semiconductor core 4 and convert to the undesignated semiconductor core 5 into the bypass instruction. When the binary code of the additional bits is 01, the conversion circuit 30 is controlled to output the instruction code and 4 bits as they are, and the conversion circuit 31 is controlled to output the instruction code converted to the bypass instruction code and 4 bits. It will be. When the instruction code with additional bits 1005 of FIG. 3 is input to the data conversion unit 28, FIG. 4 shows the output result of the conversion circuit 30,
FIG. 5 shows the output result of the conversion circuit 31. At this time, the 6-bit data 1006 of FIG. 4 is input to the test circuit included in the semiconductor core 4, and the 6-bit data 1007 of FIG. 5 is input to the test circuit included in the semiconductor core 5. Since the instruction code length of the test circuits included in the semiconductor cores 4 and 5 is 4 bits, the leading 2 bits of the additional bits are shifted out, and the 4-bit instruction code excluding the additional bits is executed. Although the 6-bit data of FIG. 3 is input to the test circuit 27, the test circuit 27 recognizes that the instruction code at the additional bit position is binary and is other than 00, which is a bypass instruction. As shown in FIG. 6, the instruction code 1005 is followed by the data 1
Although 008 also inputs 16 bits, the data conversion unit 28 passes the data to the semiconductor cores 4 and 5 without conversion. In the test circuit provided in the semiconductor core 4, the binary code 10
The 16-bit data corresponding to 10 is used for controlling the test circuit. Since the bypass command is set in the test circuit included in the semiconductor core 5, it is possible to operate the semiconductor core 5 simply by shifting out the 16-bit data. Has no effect.

Next, the data conversion unit 2 will be described with reference to FIG.
The detailed operation of No. 8 will be described. The instruction code 1005 with additional bits input to the control circuit 32 is the shift register 3
3 is shifted in, the output of all bits of the shift register 33 is decoded by the decoder, and the designated semiconductor core 4
The control signal 111 to the conversion circuit 30 to the low level, and the conversion circuit 31 to the unselected semiconductor core 5
The control signal 112 is set to the high level. The control signals 111 and 112 adjust the change timing so as to match the timing with the instruction code input next to the additional bit by the latches 35 and 36, and output the control signals 109 and 110. The timing of the latches 35 and 36 is controlled by the latch timing control circuit 37, and in the JTAG method, the instruction code is shifted in at the rising edge of the clock, so that the additional bits are shifted in all bits and the falling edge of the next clock is shifted in. You can latch it with. After the timing adjustment, the control signal 109 is set to the Low level and the control signal 11
0 becomes High level. Since the bypass instruction code of the JTAG method is 1111 in binary, the conversion circuits 30 and 3
1 may be a 2-input OR circuit, and the conversion circuit 30 controlled by the low-level control signal 109 outputs the input instruction code as it is and the high-level control signal 11
The control circuit 31 controlled by 0 fixes the instruction code to the high level and outputs it. In this way, the data conversion unit 28
Can be realized with a simple circuit.

As described above, according to the first embodiment of the present invention, the number of test terminals is at least one,
Without increasing the number, the semiconductor core 4 in the semiconductor device 29,
5 and the test circuit 27 can be controlled, and the external control unit only needs to add a process of adding an additional bit to the beginning of the instruction code, and the amount of data to be transferred is also added to the beginning of the instruction code. The increase in transfer time is small as the number of bits increases.

FIG. 7 shows the structure of a semiconductor device according to the second embodiment of the present invention. In FIG. 7, the same components as those of the first embodiment of the present invention are designated by the same reference numerals, the description thereof will be omitted, and different points will be mainly described. In FIG. 7, 38 is an external test device, 25 is a test input terminal,
26 is a test output terminal, 4 and 5 are semiconductor cores each having a test circuit, 39 is a synchronization control unit, 40 is a test circuit having a synchronization control unit 39, 41 is a semiconductor core 4, 5 and a test circuit 40. And a data conversion unit 28 are integrated to provide a set of test terminals 25 and 26.

FIG. 8 is a block diagram of the synchronization control unit 39. In FIG. 8, 42 is a register circuit expanded in the test circuit 40, and 43 is a control circuit for outputting a control signal to the semiconductor cores 4 and 5.

When the control data is written from the external test device 38 to the register circuit 42 of the synchronization control unit 39, the control signal 113 is simultaneously or individually written to the semiconductor cores 4 and 5.
And the control signal 114 is output. Further, by setting the designated condition in the register circuit 42 in advance, the control circuit 43 causes the signals 115, 1 indicating the states of the semiconductor cores 4 and 5 to be generated.
16 is input, and control signals 113 and 114 are output to the semiconductor cores 4 and 5 under specified conditions such as logical sum and logical product. In addition,
By extending the register circuit 42 of the synchronization control unit 39 to the test circuit 40, the register circuit 42 can be easily controlled from an external test device like other test registers.

As described above, according to the second embodiment of the present invention, in addition to the effect of the first embodiment, it is possible to perform synchronous control such as simultaneous reset generation for a plurality of semiconductor cores. Becomes Furthermore, it is possible to control the output of one semiconductor core to stop the execution of another semiconductor core.

[0032]

According to the semiconductor device of the first aspect, by providing the data conversion unit for converting the instruction code to the unspecified semiconductor core into the instruction code that does not affect the operation of the semiconductor core, It is possible to develop an external test device for a semiconductor device that integrates multiple semiconductor cores without increasing the number of test terminals and without making any complicated changes to the external test device for a single semiconductor core, and
It is possible to provide a semiconductor device that can be tested in a test time equivalent to that of a single semiconductor core.

According to the semiconductor device of the second aspect, in addition to the same effect as the first aspect, it is possible to simultaneously control a plurality of semiconductor cores, and further, based on the output of a certain semiconductor core, another semiconductor core can be controlled. A semiconductor device capable of controlling a core can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor device and a connection with an external test device according to a first embodiment of the present invention.

2A is a schematic block diagram of a data conversion unit in FIG. 1, and FIG. 2B is a detailed block diagram of the data conversion unit in FIG.

FIG. 3 is a diagram showing the content of an instruction code input to the data conversion unit of FIG.

4 is a diagram showing the content of data output from the conversion circuit 30 of FIG. 2 when the instruction code of FIG. 3 is input to the data conversion unit.

5 is a diagram showing the content of data output from the conversion circuit 31 of FIG. 2 when the instruction code of FIG. 3 is input to the data conversion unit.

6 is a diagram showing the contents of an instruction code and data input to the test input terminal of FIG.

FIG. 7 is a block diagram showing a configuration of a semiconductor device and a connection with an external test device according to a second embodiment of the present invention.

8 is a block diagram of an example of a synchronization controller of FIG.

FIG. 9 is a block diagram showing a configuration of a semiconductor device connected by a conventional serial chain and a connection with an external test device.

FIG. 10 is a block diagram showing a configuration of a conventional semiconductor device having a plurality of sets of test terminals and a connection with an external test device.

FIG. 11 is a block diagram showing a configuration of a conventional semiconductor device in which a terminal for selection is added and a connection with an external test device.

12 is a diagram showing the contents of an instruction code and data input to the test input terminal of FIG.

13 is a diagram showing the content of output data output to the test output terminal of FIG.

[Explanation of symbols]

1 External test equipment 2 Test input terminal 3 Test output terminal 4 Semiconductor core 5 Semiconductor core 6 Test circuit 7 Semiconductor device 8 External test equipment 9 External test equipment 10 External test equipment 11 Test input terminal 12 Test output terminal 13 Test input terminal 14 Test output terminal 15 Test input terminal 16 Test output terminal 17 Semiconductor device 18 External test equipment 19 Test input terminal 20 Test output terminal 21 Selector circuit 22 Selection terminal 23 Semiconductor device 24 External test equipment 25 Test input terminal 26 Test output terminal 27 Test circuit 28 Data converter 29 Semiconductor devices 30 conversion circuit 31 Conversion circuit 32 control circuit 33 shift register 34 Decoder 35 Latch 36 Latch 37 Latch timing control circuit 38 External test equipment 39 Synchronous control unit 40 test circuit 41 Semiconductor device 42 register circuit 43 Control circuit 101 Input signal to the semiconductor core 4 102 Input signal to the semiconductor core 5 103 Input signal to test circuit 6 104 Output signal of test circuit 6 105 Output signal of semiconductor core 4 106 Input signal to the semiconductor core 5 107 Output signal of semiconductor core 5 108 Input signal to test circuit 6 109 Control signal to conversion circuit 30 110 Control signal to conversion circuit 31 111 Input signal of latch 35 112 Input signal of latch 36 113 Control signal to semiconductor core 4 114 Control signal to semiconductor core 5 115 signal indicating the state of the semiconductor core 4 116 signal indicating the state of the semiconductor core 5 1001 Contents of linked instruction code 1002 Contents of linked data 1003 Output contents of linked instruction register 1004 Concatenated data output contents 1005 Instruction code contents with additional bits 1006 Output contents of conversion circuit 30 1007 Output contents of conversion circuit 31 1008 Data output contents of semiconductor core 4

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Claims (2)

[Claims] 1. Two or more semiconductor cores each having a test circuit, and inputting input data and outputting to the test circuit provided in the semiconductor core, which is designated by the input data. A data conversion unit that transfers the input data to the semiconductor core, and converts the input data to the semiconductor core not specified by the input data so as not to affect the operation of the semiconductor core; A semiconductor device comprising: a circuit that inputs input data, inputs a data output of the test circuit included in the semiconductor core, and outputs only the data output of the semiconductor core designated by the input data. 2. The semiconductor device according to claim 1, further comprising a synchronization control unit that outputs a control signal to the plurality of semiconductor cores simultaneously or individually by an input from an external test device that generates input data or a semiconductor core.