TW202018509A - Sas connector conduction detection system and method thereof - Google Patents

Abstract

A SAS connector conduction detection system and a method thereof are provided. A SAS connector of a detection circuit board and a SAS connector of a motherboard are connected. The detection circuit board and a test access port controller are series connection by a JTAG input connector and a JTAG output connector. Two detection circuit boards which are correspondence can be provided the SAS connectors of the motherboard which are connected with the two detection circuit boards connector conduction detection at the same time. Therefore, the improve efficiency of SAS connector conduction detection may be achieved.

Description

SAS connector conduction detection system and method

A detection system and method thereof, in particular, a test system through which the SAS connector on the circuit board and the motherboard SAS connector on the motherboard are plugged into each other, through the test circuit board JTAG input connector and JTAG output connector to make the test save The port controllers can form a serial connection with each other, so that the corresponding two detection circuit boards can simultaneously provide the SAS connector conduction detection system and method for the conduction detection of the corresponding plugged motherboard SAS connector.

The signal test on the motherboard/SC SAS connector, the previous SC test basically used the Function test. Many in the industry are buying SAS test fixtures, which are diagnosed through high-speed differential communication between the fixture and the device under test. Such test fixtures usually cost a lot (generally require a powerful MCU and peripheral circuits).

In summary, it can be seen that the prior art has long had the problem of excessively high cost of testing SAS connectors, so it is necessary to propose improved technical means to solve this problem.

In view of the prior art's existing problem of excessively high cost of SAS connector inspection, the present invention discloses a SAS connector conduction inspection system and method thereof, in which:

The SAS connector conduction detection system disclosed in the present invention includes: a motherboard and a detection circuit board. The motherboard further includes: multiple motherboard SAS connectors; the detection circuit board further includes: SAS connectors, JTAG input connectors, JTAG Output connector, buffer, complex programmable logic device (CPLD), first JTAG chip, second JTAG chip, first multiplexer, second multiplexer, microprocessor, electronic erasure Rewritable read-only memory, analog-to-digital converter and voltage regulator.

Each motherboard SAS connector on the motherboard is electrically connected to the corresponding motherboard SAS connector.

The SAS connector is electrically connected to the complex programmable logic device, the first JTAG chip, the second JTAG chip, the analog-to-digital converter and the voltage regulator; the JTAG input connector is respectively connected to the JTAG output connector, the buffer and the first The multiplexer forms an electrical connection; the JTAG output connector forms an electrical connection with the JTAG input connector and the first multiplexer; the buffer forms the electrical connection with the JTAG input connector, the JTAG output connector, and the complex programmable logic device, respectively Connection; the complex programmable logic device is electrically connected to the buffer, the first JTAG chip, the SAS connector, and the microprocessor; the first JTAG chip is connected to the SAS connector, the complex programmable logic device, and the second JTAG chip, respectively Form an electrical connection; the second JTAG chip is electrically connected to the SAS connector and the first JTAG chip respectively; the first multiplexer is respectively connected to the JTAG input connector, JTAG output connector, complex programmable logic device and microprocessor Form an electrical connection; the second multiplexer forms an electrical connection with a microprocessor, an electronically erasable rewritable read-only memory, and an analog-to-digital converter; the microprocessor is connected with a complex programmable logic device and the first The multiplexer, the second multiplexer, and the analog-to-digital converter form an electrical connection; the electronic erasable rewritable read-only memory forms an electrical connection with the second multiplexer; the analog-to-digital converter is connected to the SAS connector, the first The two multiplexers and the microprocessor form an electrical connection; the voltage regulator forms an electrical connection with the first multiplexer and the power supply; and when the two detection circuit boards are respectively connected to the corresponding motherboard through the SAS connector When the motherboard SAS connector, the corresponding two detection circuit boards can simultaneously provide continuity detection of the corresponding plugged motherboard SAS connector.

The SAS connector conduction detection method disclosed in the present invention includes the following steps:

First, provide a motherboard with multiple motherboard SAS connectors; then, each motherboard SAS connector forms an electrical connection with the corresponding motherboard SAS connector; then, provide a SAS connector, JTAG input connector, and JTAG output connection Memory, buffer, complex programmable logic device (CPLD), first JTAG chip, second JTAG chip, first multiplexer, second multiplexer, microprocessor, electronic erasable Duplicate read-only memory, analog-to-digital converter, and detection circuit board of voltage regulator; then, SAS connector and complex programmable logic device, first JTAG chip, second JTAG chip, analog-to-digital converter, and voltage regulator, respectively Form an electrical connection; then, the JTAG input connector forms an electrical connection with the JTAG output connector, the buffer, and the first multiplexer; then, the JTAG output connector forms with the JTAG input connector and the first multiplexer, respectively Electrical connection; then, the buffer is electrically connected to the JTAG input connector, JTAG output connector, and the complex programmable logic device; then, the complex programmable logic device is connected to the buffer, the first JTAG chip, and the SAS connector, respectively And the microprocessor to form an electrical connection; then, the first JTAG chip is electrically connected to the SAS connector, the complex programmable logic device and the second JTAG chip respectively; then, the second JTAG chip is respectively connected to the SAS connector and the first The JTAG chip forms an electrical connection; then, the first multiplexer forms an electrical connection with the JTAG input connector, JTAG output connector, complex programmable logic device, and microprocessor, respectively; The processor, the electronically erasable rewritable read-only memory and the analog-to-digital converter form an electrical connection; then, the microprocessor is respectively connected to the complex programmable logic device, the first multiplexer, the second multiplexer and the analog digital The converter is electrically connected; then, the electronically erasable rewritable read-only memory is electrically connected with the second multiplexer; then, the analog-to-digital converter is respectively connected with the SAS connector, the second multiplexer, and the microprocessor To form an electrical connection; then, the voltage regulator is electrically connected to the first multiplexer and the power supply; finally, when the two detection circuit boards are respectively plugged into the corresponding motherboard motherboard SAS connectors through the SAS connectors At this time, the corresponding two detection circuit boards can simultaneously provide continuity detection of the corresponding plugged motherboard SAS connector.

The system and method disclosed by the present invention are as above. The difference from the prior art is that the SAS connector on the circuit board and the motherboard SAS connector on the motherboard are plugged into each other, and the JTAG input connector on the circuit board is detected through The JTAG output connector enables the detection circuit board and the test access port controller to form a serial connection with each other, so that the corresponding two detection circuit boards can simultaneously provide conduction detection of the corresponding plugged motherboard SAS connector.

Through the above technical means, the present invention can achieve the technical efficiency of improving the detection efficiency of the SAS connector.

The embodiments of the present invention will be described in detail below in conjunction with the drawings and examples, so as to fully understand and implement the implementation process of how the present invention uses technical means to solve technical problems and achieve technical effects.

The following will describe the operation system and method of the embodiment of the present invention with an embodiment, and please refer to the "Figure 1" and "Figure 2", "Figure 1" shows the SAS connector of the present invention System block diagram of the continuity detection system; "Figure 2A" and "Figure 2B" are flow charts illustrating the method of the SAS connector conduction detection method of the present invention.

The SAS connector conduction detection system disclosed by the present invention includes: a motherboard 10 and a detection circuit board 20. The motherboard 10 further includes: a plurality of motherboard SAS connectors 11, that is, the motherboard 10 has a plurality of motherboard SAS connectors 11 (step 101), each motherboard SAS connector 11 forms an electrical connection with the corresponding motherboard SAS connector 11 (step 102); the detection circuit board 20 further includes: a SAS connector 201, a JTAG input connector 202, JTAG output connector 203, buffer 204, Complex Programmable Logic Device (CPLD) 205, first JTAG chip 206, second JTAG chip 207, first multiplexer 208, second multiplexer 209 , Microprocessor 210, electronic erasable rewritable read-only memory 211, analog-to-digital converter 212, and voltage regulator 213, that is, the detection circuit board 20 has a SAS connector 201, a JTAG input connector 202, and a JTAG output connector 203, buffer 204, Complex Programmable Logic Device (CPLD) 205, first JTAG chip 206, second JTAG chip 207, first multiplexer 208, second multiplexer 209, microprocessor 210. Electronic erasable rewritable read-only memory 211, analog-to-digital converter 212, and voltage regulator 213 (step 103).

The SAS connector 201 of the inspection circuit board 20 is connected to the complex programmable logic device 205 of the inspection circuit board 20, the first JTAG chip 206 of the inspection circuit board 20, the second JTAG chip 207 of the inspection circuit board 20, and the inspection circuit board 20 respectively. The analog-to-digital converter 212 and the voltage regulator 213 of the detection circuit board 20 are electrically connected (step 104).

The JTAG input connector 202 of the detection circuit board 20 is electrically connected to the JTAG output connector 203 of the detection circuit board 20, the buffer 204 of the detection circuit board 20, and the first multiplexer 208 of the detection circuit board 20 (step 105) ).

The JTAG output connector 203 of the detection circuit board 20 is electrically connected to the JTAG input connector 202 of the detection circuit board 20 and the first multiplexer 208 of the detection circuit board 20 (step 106).

The buffer 204 of the detection circuit board 20 is electrically connected to the JTAG input connector 202 of the detection circuit board 20, the JTAG output connector 203 of the detection circuit board 20, and the complex programmable logic device 205 of the detection circuit board 20 (step 107) ).

The complex programmable logic device 205 of the inspection circuit board 20 is respectively connected to the buffer 204 of the inspection circuit board 20, the first JTAG chip 206 of the inspection circuit board 20, the SAS connector 201 of the inspection circuit board 20, and the microprocessing of the inspection circuit board 20 The device 210 forms an electrical connection (step 108).

The first JTAG chip 206 of the inspection circuit board 20 is electrically connected to the SAS connector 201, the complex programmable logic device 205 of the inspection circuit board 20, and the second JTAG chip 207 of the inspection circuit board 20 (step 109).

The second JTAG wafer 207 of the inspection circuit board 20 is electrically connected to the SAS connector 201 of the inspection circuit board 20 and the first JTAG wafer 206 of the inspection circuit board 20 (step 110).

The first multiplexer 208 of the detection circuit board 20 is connected to the JTAG input connector 202 of the detection circuit board 20, the JTAG output connector 203 of the detection circuit board 20, the complex programmable logic device 205 of the detection circuit board 20, and the microprocessor 210 forms an electrical connection (step 111).

The second multiplexer 209 of the detection circuit board 20 is electrically connected to the microprocessor 210, the electronic erasable rewritable read-only memory 211 of the detection circuit board 20, and the analog-to-digital converter 212 of the detection circuit board 20 ( Step 112).

The microprocessor 210 of the detection circuit board 20 and the complex programmable logic device 205 of the detection circuit board 20, the first multiplexer 208 of the detection circuit board 20, the second multiplexer 209 of the detection circuit board 20, and the detection circuit board The analog-to-digital converter 212 of 20 forms an electrical connection (step 113).

The electronically erasable rewritable read-only memory 211 of the detection circuit board 20 is electrically connected to the second multiplexer 209 of the detection circuit board 20 (step 114).

The analog-to-digital converter 212 of the detection circuit board 20 is electrically connected to the SAS connector 201 of the detection circuit board 20, the second multiplexer 209 of the detection circuit board 20, and the microprocessor 210 of the detection circuit board 20 (step 115) ).

The voltage stabilizer 213 of the detection circuit board 20 is electrically connected to the first multiplexer 208 of the detection circuit board 20 and the power source (step 116).

The complex programmable logic device 205 of the detection circuit board 20 may use the chip model EPM240 as the implementation aspect, and the first JTAG chip 206 of the detection circuit board 20 may use the chip model SCAN15MB200TSQ as the implementation aspect, and the detection circuit board 20 The second JTAG chip 207 may use a chip model SCAN15MB200TSQ for implementation, the first multiplexer 208 of the inspection circuit board 20 may use a chip model 74CBTLV3257 for implementation, and the second multiplexer of the circuit board 20 209 can use the chip model PCA9548 for implementation, the microprocessor 210 of the inspection circuit board 20 can use the chip model LPC1113FBD48 for implementation, the electronic erasable rewritable read-only memory 211 of the inspection circuit board 20 The chip model 24LC32AT can be used for implementation. The analog digital converter 212 of the detection circuit board 20 can be implemented by the chip model MAX1039. The voltage regulator 213 of the detection circuit board 20 can be implemented by the chip model IR3842. In order to realize the aspect, it is only illustrated here, and does not limit the application scope of the present invention.

The first JTAG chip 206 of the detection circuit board 20 and the second JTAG chip 207 of the detection circuit board 20 respectively provide generating differential detection signals and generating input and output signals. The microprocessor 210 of the detection circuit board 20 is used to control the detection circuit board 20 The first JTAG chip 206 or the second JTAG chip 207 of the detection circuit board 20 generates input and output signals and controls switching of integrated circuit bus signals.

The motherboard SAS connector 11 on the motherboard 10 and its corresponding motherboard SAS connector 11 form an electrical connection with each other, and the JTAG input connector 202 of the test circuit board 20 can be connected to a Test Access Port (TAP) controller Or the JTAG output connector 202 of another detection circuit board 20 forms an electrical connection, and the JTAG output connector 203 of the detection circuit board 20 forms an electrical connection or detection circuit with the JTAG input connector 202 of another detection circuit board 20 The JTAG output connector 203 of the board 20 is unconnected. When a motherboard SAS connector 11 of the motherboard 10 and its corresponding motherboard SAS connector 11 are respectively plugged into the SAS connector 201 of the inspection circuit board 20, the test passes The access port controller provides a detection signal to the corresponding detection circuit board 20, and the corresponding detection circuit board 20 can simultaneously perform connector pin positioning on the two motherboard SAS connectors 11 corresponding to the motherboard 10 according to the detection signal Continuity detection (step 117).

The aforementioned motherboard SAS connector 11 of the motherboard 10 and the SAS connector 201 of the detection circuit board 20 respectively include an integrated circuit bus, input/output pins, ground pins, data transmission pins, and analog signal pins. This is only an example, and does not limit the scope of application of the present invention, that is, the detection signal can detect the differential signal pin, the ground signal pin of the motherboard SAS connector 11 of the motherboard 10, and the analog Signal pin detection, input and output signal pin detection, and integrated circuit bus pin detection are used to conduct continuity detection.

When conducting the continuity detection of the pin of the motherboard SAS connector 11 of the motherboard 10, the test access port controller will detect the complex programmable logic device 205 of the circuit board 20, the first JTAG chip 206 of the circuit board 20 and the detection The second JTAG chips 207 of the circuit board 20 are all set to the boundary scan working mode.

Please refer to "Figure 3A", which is a schematic diagram of a part of the test block of the SAS connector conduction detection of the present invention.

The complex programmable logic device 205 of the detection circuit board 20, the first JTAG chip 206 of the detection circuit board 20, the second JTAG chip 207 of the detection circuit board 20, and the microprocessor 210 of the detection circuit board 20 respectively generate differences based on the detection signals Signal or signal control.

The signal detection of the PE_TX_DP pin (ie data transmission pin) and PE_TX_DN pin (ie data transmission pin) in the motherboard SAS connector 11 is performed on the first JTAG chip 206 or the second of the first detection circuit board 21 When the JTAG chip 207 receives the detection signal, it generates a differential signal and transmits it to the second through the SAS connector 201 of the first detection circuit board 21, the motherboard SAS connector 11 of the motherboard 10, and the SAS connector 201 of the second detection circuit board 22 The first JTAG chip 206 or the second JTAG chip 207 of the circuit board 22 is inspected for inspection.

If the differential signal sent by the first JTAG chip 206 or the second JTAG chip 207 of the first detection circuit board 21 and the differential signal received by the first JTAG chip 206 or the second JTAG chip 207 of the second detection circuit board 22 When the signals are the same, the continuity detection of the PE_TX_DP pin and the PE_TX_DN pin in the motherboard SAS connector 11 will pass the test, otherwise the difference from the first JTAG chip 206 or the second JTAG chip 207 of the first detection circuit board 21 When the signal is different from the differential signal received by the first JTAG chip 206 or the second JTAG chip 207 of the second detection circuit board 22, the continuity detection of the PE_TX_DP pin and the PE_TX_DN pin in the motherboard SAS connector 11 is tested failure.

For the signal detection of the PE_RX_DP pin (namely the data transmission pin) and the PE_RX_DN pin (namely the data transmission pin) in the SAS connector 11 of the motherboard, it is detected on the first JTAG chip 206 or the second of the second detection circuit board 22 When the JTAG chip 207 receives the detection signal, it generates a differential signal and transmits it to the first through the SAS connector 201 of the second detection circuit board 22, the motherboard SAS connector 11 of the motherboard 10, and the SAS connector 201 of the first detection circuit board 21 The first JTAG chip 206 or the second JTAG chip 207 of the circuit board 21 is inspected for inspection.

If the differential signal sent by the first JTAG chip 206 or the second JTAG chip 207 of the second detection circuit board 22 and the differential signal received by the first JTAG chip 206 or the second JTAG chip 207 of the first detection circuit board 21 When the signals are consistent, the continuity detection of the PE_RX_DP pin and the PE_RX_DN pin in the motherboard SAS connector 11 will pass the test, otherwise the difference between the first JTAG chip 206 or the second JTAG chip 207 of the second detection circuit board 22 When the signal is different from the differential signal received by the first JTAG chip 206 or the second JTAG chip 207 of the first detection circuit board 21, then the conduction detection of the PE_RX_DP pin and the PE_RX_DN pin in the motherboard SAS connector 11 is tested failure.

Please refer to "Picture 3B" and "Picture 3C", "Picture 3B" and "Picture 3C" show schematic diagrams of part of the test block for continuity detection of the SAS connector of the present invention.

For the signal detection of the analog signal pin in the motherboard SAS connector 11, when the microprocessor 210 of the detection circuit board 20 receives the detection signal, the microprocessor 210 of the detection circuit board 20 is connected to the detection through the integrated circuit bus After the analog-to-digital converter 212 of the circuit board 20 reads the voltage value of the analog signal pin in the motherboard SAS connector 11 by the analog-to-digital converter 212 of the detection circuit board 20, the microprocessor 210 of the circuit board 20 stores Detect the voltage value of the analog signal pin in the motherboard SAS connector 11 read by the analog-to-digital converter 212 of the circuit board 20, and the microprocessor 210 of the circuit board 20 will judge whether the detection result is correct according to the voltage value Whether the analog signal pin in the motherboard SAS connector 11 is turned on.

It is worth noting that when considering that the power supply is open, the analog signal pin of the analog-to-digital converter 212 is empty, and the voltage of the analog signal pin of the analog-to-digital converter 212 is unstable. In order to avoid the unstable voltage of the analog signal converter 212 analog signal pin empty connection state during signal detection, the pull-down resistance (pull-down) is added to the analog signal pin of the analog digital converter 212 without pull-down resistor), the aforementioned pull-down resistors can be in the range of resistance values between 3M ohms and 4M ohms, which are only examples here, and do not limit the scope of application of the present invention.

Further, a resistance voltage divider circuit can be connected to the microprocessor 210 of the detection circuit board 20 and the analog-to-digital converter 212 of the detection circuit board 20 respectively. The resistance voltage divider circuit uses, for example, 10M ohm and 2M ohm resistance voltage divider The circuit is only an example here, and does not limit the scope of application of the present invention. A backup line can be added between the resistor divider circuit and the analog-to-digital converter 212 of the detection circuit board 20, that is, the resistor divider A 0 ohm resistor is connected in series between the voltage circuit and the analog-to-digital converter 212 of the detection circuit board 20, please refer to the "Figure 3C" shown above.

Please refer to the "3D diagram" shown in the "3D diagram" is a schematic diagram of a part of the test block of the SAS connector conduction detection of the present invention.

For the signal detection of the REFCLK_DP pin (real-time pulse pin) and the REFCLK_DN pin (real-time pulse pin) in the motherboard SAS connector 11, the complex programmable logic device 205 of the first detection circuit board 21 sends a detection according to the detection signal Data to the complex programmable logic device 205 of the second detection circuit board 22, if the detection data sent by the complex programmable logic device 205 of the first detection circuit board 21 and the complex programmable logic device 205 of the second detection circuit board 22 When the received test data is consistent, the conduction test of the REFCLK_DP pin and the REFCLK_DN pin in the motherboard SAS connector 11 will pass the test, otherwise the test data sent by the complex programmable logic device 205 of the first test circuit board 21 and When the detection data received by the complex programmable logic device 205 of the second detection circuit board 22 is inconsistent, the conduction detection of the REFCLK_DP pin and the REFCLK_DN pin in the motherboard SAS connector 11 fails the test.

For the signal detection of the REFCLK_DP pin and the REFCLK_DN pin in the motherboard SAS connector 11, the complex programmable logic device 205 of the second detection circuit board 22 may also send detection data to the first detection circuit board 21 according to the detection signal. Programmable logic device 205, if the detection data sent by the complex programmable logic device 205 of the second detection circuit board 22 is consistent with the detection data received by the complex programmable logic device 205 of the first detection circuit board 21, the host The continuity detection of the REFCLK_DP pin and the REFCLK_DN pin in the board SAS connector 11 will pass the test, otherwise the detection data sent by the complex programmable logic device 205 of the second detection circuit board 22 and the complex programming of the first detection circuit board 21 When the detection data received by the logic device 205 is inconsistent, the conduction detection of the REFCLK_DP pin and the REFCLK_DN pin in the motherboard SAS connector 11 fails the test.

In summary, the difference between the present invention and the prior art is that the SAS connector on the detection circuit board and the motherboard SAS connector on the motherboard are inserted into each other, and the JTAG input connector and JTAG output on the detection circuit board The connector enables the detection circuit board and the test access port controller to form a serial connection with each other, so that the corresponding two detection circuit boards can simultaneously provide the conduction detection of the corresponding plugged motherboard SAS connector.

With this technical method, the existing problems of the existing SAS connector inspection cost that are too high in the prior art can be solved, and then the technical efficiency of improving the SAS connector inspection efficiency can be achieved.

Although the disclosed embodiments of the present invention are as above, the content described is not intended to directly limit the patent protection scope of the present invention. Any person with ordinary knowledge in the technical field to which the present invention belongs can make slight changes in the form and details of implementation without departing from the spirit and scope disclosed by the present invention. The scope of patent protection of the present invention shall still be subject to those defined in the attached patent application scope.

10: motherboard 11: Motherboard SAS connector 20: Check the circuit board 21: The first detection circuit board 22: Second detection circuit board 201: SAS connector 202: JTAG input connector 203: JTAG output connector 204: buffer 205: Complex programmable logic device 206: First JTAG chip 207: Second JTAG chip 208: The first multiplexer 209: Second multiplexer 210: Microprocessor 211: Electronic erasable rewritable read-only memory 212: Analog to Digital Converter 213: Regulator Step 101: Provide a motherboard with multiple motherboard SAS connectors Step 102: Each motherboard SAS connector forms an electrical connection with the corresponding motherboard SAS connector Step 103: Provide a SAS connector, a JTAG input connector, a JTAG output connector, a buffer, a complex programmable logic device, a first JTAG chip, a second JTAG chip, a first multiplexer, a second multiplexer, Detection circuit board of microprocessor, electronic erasable rewritable read-only memory, analog-to-digital converter and voltage regulator Step 104: The SAS connector is electrically connected to the complex programmable logic device, the first JTAG chip, the second JTAG chip, the analog-to-digital converter, and the voltage regulator, respectively Step 105: The JTAG input connector is electrically connected to the JTAG output connector, the buffer, and the first multiplexer, respectively Step 106: The JTAG output connector forms an electrical connection with the JTAG input connector and the first multiplexer, respectively Step 107: The buffer is electrically connected to the JTAG input connector, JTAG output connector and complex programmable logic device Step 108: The complex programmable logic device is electrically connected to the buffer, the first JTAG chip, the SAS connector and the microprocessor, respectively Step 109: The first JTAG chip is electrically connected to the SAS connector, the complex programmable logic device and the second JTAG chip Step 110: The second JTAG chip is electrically connected to the SAS connector and the first JTAG chip respectively Step 111: The first multiplexer is electrically connected to the JTAG input connector, JTAG output connector, complex programmable logic device and microprocessor, respectively Step 112: The second multiplexer is electrically connected to the microprocessor, the electronically erasable rewritable read-only memory, and the analog-to-digital converter, respectively Step 113: The microprocessor is electrically connected to the complex programmable logic device, the first multiplexer, the second multiplexer, and the analog-to-digital converter Step 114: The electronically erasable rewritable read-only memory is electrically connected to the second multiplexer Step 115: The analog-to-digital converter is electrically connected to the SAS connector, the second multiplexer, and the microprocessor, respectively Step 116: The voltage regulator is electrically connected to the first multiplexer and the power supply respectively Step 117: When the two detection circuit boards are respectively plugged into the corresponding motherboard motherboard SAS connectors through the SAS connectors, the corresponding two detection circuit boards can simultaneously provide the conduction of the corresponding plugged motherboard SAS connectors Testing

FIG. 1 is a system block diagram of the SAS connector conduction detection system of the present invention. FIG. 2A and FIG. 2B are flowcharts of the method for detecting the continuity of the SAS connector of the present invention. FIG. 3A and FIG. 3D are schematic diagrams of the test block of the SAS connector of the present invention.

10: motherboard

11: Motherboard SAS connector

20: Check the circuit board

201: SAS connector

202: JTAG input connector

203: JTAG output connector

204: buffer

205: Complex programmable logic device

206: First JTAG chip

207: Second JTAG chip

208: The first multiplexer

209: Second multiplexer

210: Microprocessor

211: Electronic erasable rewritable read-only memory

212: Analog to Digital Converter

213: Regulator

Claims (10)

A SAS connector conduction detection system, comprising: a motherboard, the motherboard further comprising: a plurality of motherboard SAS connectors, each motherboard SAS connector is electrically connected with a corresponding motherboard SAS connector; and a detection A circuit board, the detection circuit board further includes a SAS connector, a JTAG input connector, a JTAG output connector, a buffer, a complex programmable logic device (CPLD), a first JTAG Chip, a second JTAG chip, a first multiplexer, a second multiplexer, a microprocessor, an electronic erasable rewritable read-only memory, an analog-to-digital converter and a voltage regulator, Wherein: the SAS connector forms an electrical connection with the complex programmable logic device, the first JTAG chip, the second JTAG chip, the analog-to-digital converter and the voltage regulator, respectively; A JTAG input connector is electrically connected to the JTAG output connector, the buffer, and the first multiplexer; the JTAG output connector is respectively connected to the JTAG input connector and the first multiplexer The tool is electrically connected; the buffer is electrically connected to the JTAG input connector, the JTAG output connector, and the complex programmable logic device; the complex programmable logic device is connected to the A buffer, the first JTAG chip, the SAS connector, and the microprocessor form an electrical connection; the first JTAG chip and the SAS connector, the complex programmable logic device, and the The second JTAG chip forms an electrical connection; the second JTAG chip forms an electrical connection with the SAS connector and the first JTAG chip respectively; the first multiplexer respectively connects with the JTAG input connector and the JTAG output connector, the complex programmable logic device and the microprocessor form an electrical connection; the second multiplexer is respectively connected to the microprocessor and the electronic erasable rewritable read-only memory And the analog-to-digital converter is electrically connected; the microprocessor is respectively formed with the complex programmable logic device, the first multiplexer, the second multiplexer, and the analog-to-digital converter Electrical connection; the electronically erasable rewritable read-only memory forms an electrical connection with the second multiplexer; the analog-to-digital converter is respectively connected to the SAS connector and the second multiplexer And the microprocessor to form an electrical connection; the voltage regulator is electrically connected to the first multiplexer and a power supply; and when the two detection circuit boards are respectively plugged into the SAS connector When corresponding to the motherboard SAS connector of the main board, the corresponding two detection circuit boards can simultaneously provide conduction detection of the corresponding plugged main board SAS connector. The SAS connector continuity detection system as described in item 1 of the patent application scope, wherein the JTAG input connector of the detection circuit board and a Test Access Port (TAP) controller or another laboratory The JTAG output connector of the detection circuit board forms an electrical connection, and the JTAG output connector of the detection circuit board forms an electrical connection with the JTAG input connector of another detection circuit board. The SAS connector continuity detection system as described in item 1 of the patent application scope, wherein the motherboard SAS connector and the SAS connector respectively include an integrated circuit bus, input and output pins, ground pins, and data transmission Pin position and analog signal pin position. The SAS connector conduction detection system as described in item 1 of the patent application scope, wherein the conduction detection of the motherboard SAS connector includes data transmission pin detection, analog signal pin detection and clock pin detection. The SAS connector continuity detection system as described in item 1 of the patent application scope, wherein the complex programmable logic device and the microprocessor can be set to the boundary scan mode through the test access port controller. A SAS connector continuity detection method, comprising: providing a motherboard with multiple motherboard SAS connectors; each motherboard SAS connector is electrically connected to a corresponding motherboard SAS connector; providing a SAS connector, a JTAG input connector, a JTAG output connector, a buffer, a Complex Programmable Logic Device (CPLD), a first JTAG chip, a second JTAG chip, a first multiplexer, a A detection circuit board of a second multiplexer, a microprocessor, an electronic erasable rewritable read-only memory, an analog-to-digital converter, and a voltage regulator, the detection circuit board further including; the SAS The connectors are respectively electrically connected with the complex programmable logic device, the first JTAG chip, the second JTAG chip, the analog-to-digital converter and the voltage regulator; the JTAG input connectors are respectively Forming an electrical connection with the JTAG output connector, the buffer and the first multiplexer; the JTAG output connector forms an electrical connection with the JTAG input connector and the first multiplexer respectively Connection; the buffer is electrically connected with the JTAG input connector, the JTAG output connector and the complex programmable logic device; the complex programmable logic device is respectively connected with the buffer and the A first JTAG chip, the SAS connector and the microprocessor form an electrical connection; the first JTAG chip is formed with the SAS connector, the complex programmable logic device and the second JTAG chip, respectively Electrical connection; the second JTAG chip is electrically connected to the SAS connector and the first JTAG chip respectively; the first multiplexer is respectively connected to the JTAG input connector and the JTAG output connector, The complex programmable logic device and the microprocessor form an electrical connection; the second multiplexer and the microprocessor, the electronically erasable rewritable read-only memory, and the analog digital, respectively The converter forms an electrical connection; the microprocessor forms an electrical connection with the complex programmable logic device, the first multiplexer, the second multiplexer, and the analog-to-digital converter, respectively; The electronic erasable rewritable read-only memory is electrically connected to the second multiplexer; the analog-to-digital converter is respectively connected to the SAS connector, the second multiplexer, and the microprocessing The voltage regulator forms an electrical connection; the voltage regulator forms an electrical connection with the first multiplexer and a power source; and when two detection circuit boards are respectively plugged into the corresponding host through the SAS connector When the main board SAS connector of the board is provided, the corresponding two detection circuit boards can simultaneously provide conduction detection of the corresponding plugged motherboard SAS connector. The SAS connector conduction detection method as described in item 6 of the patent application scope, wherein the JTAG input connector of the detection circuit board and a Test Access Port (TAP) controller or another laboratory The JTAG output connector of the detection circuit board forms an electrical connection, and the JTAG output connector of the detection circuit board forms an electrical connection with the JTAG input connector of another detection circuit board. The SAS connector continuity detection method as described in item 6 of the patent application scope, wherein the motherboard SAS connector and the SAS connector respectively include an integrated circuit bus, input/output pins, ground pins, and data transmission Pin position and analog signal pin position. The SAS connector conduction detection method as described in item 6 of the patent application scope, wherein the conduction detection of the motherboard SAS connector includes data transmission pin detection, analog signal pin detection and clock pin detection. The SAS connector continuity detection method as described in item 6 of the patent application scope, wherein the complex programmable logic device and the microprocessor can be set to the boundary scan mode through the test access port controller.

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