TWI550295B - Test circuit board for peripheral component interconnect express testing - Google Patents

Description

Test board for fast peripheral interconnect standard slots

A circuit board, in particular, a test for a fast peripheral interconnect standard slot having a first joint test work group connection interface and a second joint test work group connection interface to form a test circuit board with each other in series Circuit board.

Most of the existing tests for the standard peripheral slot of the peripheral device in the board to be tested are performed by a single test board. However, the test of the standard slot of the fast peripheral interconnect in the board to be tested can only be tested by a single test board. Fast peripheral interconnect standard slots often result in a lack of test signal coverage, which is not conducive to production testing.

In summary, it can be seen that in the prior art, there has been a problem that the test signal coverage of the standard slot of the shortcut peripheral interconnect in the board to be tested has been lacking for a long time, so it is necessary to propose an improved technical means to solve this problem.

In view of the prior art, there is a problem that the test signal coverage of the standard peripheral slot of the shortcut peripheral interconnect in the board to be tested is insufficient, and the present invention discloses a test circuit board suitable for the standard slot of the shortcut peripheral interconnection, wherein:

The test circuit board for the standard peripheral socket of the fast peripheral interconnection disclosed by the invention comprises: a test circuit board, and the test circuit board further comprises: a Peripheral Component Interconnect Express (PCI-E) connection interface, First Joint Test Action Group (JTAG) connection interface, second joint test work group connection interface, joint test work group signal processing chip, at least one joint test work group control chip, at least one analogy Analog-to-Digital Converter (ADC) chips, switch chips, and voltage conversion chips.

The standard interface of the fast peripheral interconnection is used to plug in the standard slot of the fast peripheral interconnection to form an electrical connection; the first joint test work group connection interface is used for the test access port (TAP) The controller is electrically connected or electrically connected to the second joint test work group connection interface of the other test circuit board to form a serial connection with the other test circuit boards; the second joint test work group connection interface is used The first joint test work group connection interface is electrically connected to the other test circuit board; the joint test work group signal processing chip is electrically connected to the first joint test work group and the second joint test work group, respectively. To improve the stability of the joint test work group signal transmitted by the first joint test work group and the second joint test work group; at least one joint test work group control chip, joint test work group control chip and joint test work The group signal processing chip is electrically connected, and is used for detecting, state control and integrated circuit of the standard slot of the shortcut peripheral interconnection. Inter-Integrated Circuit (IIC) simulation; at least one analog-to-digital conversion chip is an analog digital conversion chip and a joint test work group control chip electrical connection for fast peripheral interconnection standard socket pin voltage Detection; the switch chip is electrically connected to the joint test work group control chip and the analog digital conversion chip, respectively, for detecting the special signal of the standard peripheral pin slot of the fast peripheral interconnection, so that the special signal can pass the joint test work. The group control chip is detected by an analog digital conversion chip; and the voltage conversion chip is used to obtain power supply through the standard peripheral slot of the fast peripheral interconnection and convert the power supply to provide a joint test work group signal processing chip, joint test The working group controls the operating voltage required for the wafer, analog to digital conversion wafer switch wafer.

The circuit board disclosed in the present invention is different from the prior art in that the test circuit board is connected to each other through the first joint test work group connection interface and the second joint test work group connection interface of the test circuit board. The serial connection can be formed to reduce the requirement of the number of test access ports in the test access controller, and the test circuit board proposed by the present invention provides test signal coverage for all test signals, facilitating the use of the production line, thereby reducing the test. The cost of the board.

Through the above technical means, the present invention can achieve the technical effect of reducing the number of test access points in the test access controller and providing test signal coverage for all test signals.

The embodiments of the present invention will be described in detail below with reference to the drawings and embodiments, so that the application of the technical means to solve the technical problems and achieve the technical effects can be fully understood and implemented.

The following is a description of the test circuit board for the standard peripheral socket of the shortcut peripheral disclosed in the present invention. Please refer to "1" and "2", and "FIG. 1" is shown as the present invention. The schematic diagram of the architecture of the standard slot test circuit board for the fast peripheral interconnection; "Fig. 2" is a schematic diagram of the architecture of the test board for the standard peripheral socket test board of the invention.

The test circuit board 10 disclosed in the present invention further comprises: a Peripheral Component Interconnect Express (PCI-E) connection interface 11, a first Joint Test Action Group (JTAG) connection interface 12, a second joint test work group connection interface 13, a joint test work group signal processing chip 14, at least one joint test work group control chip 15, at least one analog-to-digital converter (ADC) chip 16, A switch 17 wafer and a voltage conversion wafer 18 are provided.

The board to be tested 20 further includes a central processing unit (CPU) 21, a plurality of fast peripheral interconnection standard slots 22, and a complex programmable logic device (CPLD) 23.

The fast peripheral interconnection standard connection interface 11 of the test circuit board 10 is for providing the test circuit board 10 to be inserted into the shortcut peripheral interconnection standard slot 22 of the board to be tested 20 to make the test circuit board 10 and the board to be tested. 20 forms an electrical connection, and each of the quick peripheral interconnection standard slots 22 of the board to be tested 20 can be plugged into a test board 10.

The first joint test work group connection interface 12 of the test circuit board 10 is for electrically connecting to the test access controller 30, or the first joint test work group connection interface 12 of the test circuit board 10 is for The second joint test work group connection interface 13 of the other test circuit board 10 is electrically connected to form the test circuit board 10 in series with the other test circuit boards 10.

Specifically, the to-be-tested board 20 has a first shortcut peripheral interconnection standard slot 221 and a second shortcut peripheral interconnection standard slot 222, and the first test circuit board 101 is plugged into the first shortcut of the to-be-tested board 20 The first test circuit group connection interface 221, the second test circuit board 102 is plugged into the second shortcut peripheral interconnection standard slot 222 of the board to be tested 20, and the first joint test work group connection interface of the first test circuit board 101 12 is electrically connected to the test access controller 30, and the first joint test work group connection interface 13 of the first test circuit board 101 and the first joint test work group connection interface 12 of the second test circuit board 102 are electrically connected. The connection is such that the first test circuit board 101 and the second test circuit board 102 form a series connection, which is merely illustrative here, and is not intended to limit the scope of application of the present invention.

The joint test work group signal processing chip 14 of the test circuit board 10 is electrically connected to the first joint test work group 12 of the test circuit board 10 and the second joint test work group 13 of the test circuit board 10, respectively. The joint test work group signal processing chip 14 of 10 is used to improve the first joint test work group 12 of the test circuit board 10 and the joint test work group signal transmitted by the second joint test work group 13 of the test circuit board 10. Stability.

The central processing unit 21 of the board 20 to be tested is used to provide a Boundary Scan mode for testing by the test circuit board 10. The complex programmable logic element 23 of the board 20 to be tested is used to control the machine to be tested. The power state of the board 20.

The test access controller 30 is also electrically coupled to the central processor 21 of the board 20 to be tested and the complex programmable logic element 23 of the board 20 to be tested, and the test access controller 30 controls the board to be tested. The complex programmable logic element 23 of 20 controls the power supply state of the board 20 to be tested, and the test access controller 30 also controls the central processor 21 of the board 20 to be tested and the complexity of the board 20 to be tested. The logic component 23 is programmed to the boundary scan mode of operation, and the test access controller 30 controls the test circuit board 10 to the boundary scan mode of operation through the first joint test workgroup connection interface 12 of the test circuit board 10.

The joint test work group control chip 15 of the test circuit board 10 is electrically connected to the joint test work group signal processing chip 14 of the test circuit board 10, and the joint test work group control chip 15 of the test circuit board 10 is used for waiting. The tester board 20's shortcut peripheral interconnects the detection of the standard slot 22 pin, the state control of the test board 10, and the simulation of the integrated circuit bus of the test board 10.

The analog digital conversion chip 16 of the test circuit board 10 is electrically connected to the joint test work group control chip 15 of the test circuit board 10, and the analog digital conversion chip 16 of the test circuit board 10 is used to perform the shortcut of the machine board 20 to be tested. Set the voltage detection of the interconnect standard slot pin 22.

The switch wafer 17 of the test circuit board 10 is electrically connected to the joint test work group control chip 15 of the test circuit board 10 and the analog digital conversion chip 16 of the test circuit board 10, respectively. The switch wafer 17 of the test circuit board 10 is used to The detection of the special signal of the fast peripheral interconnection standard slot 22 of the board to be tested 20 is performed so that the special signal can be detected by the joint test work group control chip 15 or by the analog digital conversion chip 16.

The voltage conversion chip 18 of the test circuit board 10 is a joint test work group signal processing chip 14 for obtaining power supply through the fast peripheral interconnection standard slot 22 of the test circuit board 10 and converting the power supply to provide the test circuit board 10. The joint test work group of the test circuit board 10 controls the operating voltage required for the wafer 15, the analog digital conversion wafer switch wafer 16 of the test circuit board 10, and the switch wafer 17 of the test circuit board 10.

The test access controller 30 is tested by the test circuit board 10 in the boundary scan mode of operation of the complex programmable logic component 23 of the board to be tested 20, the central processor 21 of the board 20 to be tested, and the test board 10. The work group control chip 14, the analog digital conversion chip 15 of the test circuit board 10, and the switch wafer 16 of the test circuit board 10 to perform detection, state control of the standard peripheral slot 22 of the fast peripheral interconnection of the board to be tested 20, and The simulation of the integrated circuit bus, the voltage detection of the standard peripheral slot 22 of the fast peripheral interconnect of the board to be tested 20, and the detection of the special signal of the standard slot 22 of the shortcut peripheral interconnect of the board 20 to be tested.

In summary, it can be seen that the difference between the present invention and the prior art is that the test circuit board can be connected to each other through the first joint test work group connection interface and the second joint test work group connection interface of the test circuit board. The serial connection is formed to reduce the requirement of the number of test access ports in the test access controller, and the test circuit board proposed by the present invention provides test signal coverage for all test signals, facilitating the use of the production line, thereby reducing the test circuit. The cost of the board.

The technical problem can be solved by the prior art that the test signal coverage of the standard peripheral slot of the fast peripheral interconnect in the board to be tested is insufficient, thereby reducing the number of test accesses in the test access controller. The requirements and technical capabilities to provide test signal coverage for all test signals.

While the embodiments of the present invention have been described above, the above description is not intended to limit the scope of the invention. Any changes in the form and details of the embodiments may be made without departing from the spirit and scope of the invention. The scope of the invention is to be determined by the scope of the appended claims.

10‧‧‧Test circuit board
101‧‧‧First test board
102‧‧‧Second test circuit board
11‧‧‧Quick Peripheral Interconnect Standard Connection Interface
12‧‧‧First Joint Test Workgroup Connection Interface
13‧‧‧Second joint test work group connection interface
14‧‧‧Joint test workgroup signal processing chip
15‧‧‧Joint Test Workgroup Control Wafer
16‧‧‧ analog digital conversion chip
17‧‧‧Switch wafer
18‧‧‧Voltage conversion chip
20‧‧‧Test board
21‧‧‧Central Processing Unit
22‧‧‧Quick Peripheral Interconnect Standard Slot
221‧‧‧First Fast Peripheral Interconnect Standard Slot
222‧‧‧Second Fast Peripheral Interconnect Standard Slot
23‧‧‧Complex programmable logic components

FIG. 1 is a schematic diagram showing the architecture of a test circuit board suitable for a fast peripheral interconnection standard slot according to the present invention. FIG. 2 is a schematic diagram showing the architecture of the present invention when it is applied to a test circuit board of a standard peripheral slot for a fast peripheral interconnection.

10‧‧‧Test circuit board

11‧‧‧Quick Peripheral Interconnect Standard Connection Interface

12‧‧‧First Joint Test Workgroup Connection Interface

13‧‧‧Second joint test work group connection interface

14‧‧‧Joint test workgroup signal processing chip

15‧‧‧Joint Test Workgroup Control Wafer

16‧‧‧ analog digital conversion chip

17‧‧‧Switch wafer

18‧‧‧Voltage conversion chip

Claims (7)

A test circuit board suitable for a standard peripheral slot for a fast peripheral interconnection, comprising: a test circuit board, the test circuit board further comprising: a Peripheral Component Interconnect Express (PCI-E) connection interface, Used to plug in the standard peripheral slot of the shortcut peripheral to form an electrical connection; a first Joint Test Action Group (JTAG) connection interface for testing access ports (Test Access Port, The TAP) controller is electrically connected or electrically connected to the second joint test work group connection interface of the other test circuit board to form a serial connection with the other test circuit boards; a joint test work group connection interface for electrically connecting to the first joint test work group connection interface of other test boards; a joint test work group signal processing chip, the joint test work group signal processing The chip is electrically connected to the first joint test work group and the second joint test work group, respectively, to improve the first joint test Stability of the joint test work group signal transmitted by the work group and the second joint test work group; at least one joint test work group control chip, the joint test work group control chip and the joint test work The group signal processing chip is electrically connected for detecting the position of the standard slot of the fast peripheral interconnection, the state control, and the simulation of the integrated circuit (IIC); at least one analog-to-digital conversion (Analog) a -to-Digital Converter (ADC) chip, the analog digital conversion chip being electrically connected to the joint test work group control chip for performing voltage detection of a standard peripheral pin position of a fast peripheral interconnection; a chip, the switch chip is electrically connected to the joint test work group control chip and the analog digital conversion chip, respectively, for detecting a special signal of a standard peripheral slot of the shortcut peripheral interconnect, so as to enable The special signal can be detected by the joint test work group control chip or by the analog digital conversion chip And a voltage conversion chip for obtaining power supply through the fast peripheral interconnection standard slot and converting the power supply to provide the joint test work group signal processing chip, the joint test work group control chip, the analogy The operating voltage required to digitally convert the wafer switch wafer. The test circuit board applicable to the standard peripheral of the shortcut peripheral interconnection, as described in claim 1, further comprising a board to be tested, wherein the board to be tested further comprises: a central processing unit (Central Processing Unit) , CPU) for providing a Boundary Scan mode for the test circuit board to detect; at least one shortcut peripheral interconnect standard slot for providing the test circuit board plug; and a complex A Complex Programmable Logic Device (CPLD) is used to control the power state of the board to be tested. A test circuit board suitable for a fast peripheral interconnection standard slot as described in claim 2, wherein the test access controller is respectively associated with the central processing unit, the complex programmable logic element, and The first joint test work group connection interface is electrically connected. A test circuit board suitable for a fast peripheral interconnect standard slot as described in claim 3, wherein the test access controller controls the complex programmable logic element to control the test board to be tested Power supply status. A test circuit board for a fast peripheral interconnect standard slot as described in claim 3, wherein the test access controller controls the complex programmable logic element and the central processor to a boundary Boundary Scan mode of operation. A test circuit board suitable for a fast peripheral interconnection standard slot as described in claim 1, wherein the test access controller controls the test circuit board to a boundary scan mode of operation. A test circuit board for a fast peripheral interconnect standard slot as described in claim 3, wherein the test access controller is in the complex programmable logic component, the central processor, and the In the boundary scan mode of the test circuit board, the detection of the standard slot of the fast peripheral interconnection, the state control, and the simulation of the integrated circuit bus, the voltage detection of the standard peripheral pin and the fast peripherals Detection of special signals for interconnecting standard slot slots.