TWI759380B - Pin of connector slot of circuit board conduction detection system and method thereof - Google Patents
Pin of connector slot of circuit board conduction detection system and method thereof Download PDFInfo
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一種檢測系統及其方法,尤其是指一種同時提供不同種類連接器插槽串接的導通檢測系統及其方法。A detection system and a method thereof, in particular, a continuity detection system and a method for simultaneously providing serial connection of different types of connector slots.
對於電路板上插槽的導通檢測,目前是採用對應於連接器插槽的測試電路板插設於對應的連接器插槽上,例如:DIMM插槽上插設DIMM的測試電路板、PCI-E插槽上插設測試PCI-E的測試電路板…等,並透過邊界掃描技術進行電路板上插槽的導通檢測。For the continuity detection of the slot on the circuit board, currently, the test circuit board corresponding to the connector slot is inserted into the corresponding connector slot, for example: the test circuit board with DIMM inserted in the DIMM slot, the PCI- A test circuit board for testing PCI-E is inserted into the E slot, etc., and the continuity detection of the slot on the circuit board is performed through the boundary scan technology.
然而,對於不同的連接器插槽,其所對應的測試電路板其設計上多少具有區別,亦即在透過邊界掃描的檢測過程中,會有不相同的檢測方式,一般是將同類型的連接器插槽互相串接後進行邊界掃描的測試,然而,對於TAP控制器所提供的測試埠有限的情況下,仍會發生TAP控制器提供的測試埠不足的情況,這不但影響測試效率,也會影響到測試的覆蓋率。However, for different connector slots, the corresponding test circuit boards are somewhat different in design, that is, during the detection process through boundary scan, there will be different detection methods. Generally, the same type of connection Boundary scan test is performed after the device slots are connected in series. However, when the test ports provided by the TAP controller are limited, there will still be insufficient test ports provided by the TAP controller, which not only affects the test efficiency, but also affects the test efficiency. will affect the test coverage.
綜上所述,可知先前技術中長期以來一直存在現有電路板上連接器插槽測試產生測試效率與覆蓋率不足的問題,因此有必要提出改進的技術手段,來解決此一問題。To sum up, it can be seen that in the prior art, there has been a long-standing problem of insufficient test efficiency and coverage for connector socket testing on existing circuit boards. Therefore, it is necessary to propose improved technical means to solve this problem.
有鑒於先前技術存在現有連接器插槽測試產生測試效率與覆蓋率不足的問題,本發明遂揭露一種電路板的連接器插槽腳位導通檢測系統及其方法,其中:In view of the problem of insufficient test efficiency and coverage in the prior art of the existing connector socket test, the present invention discloses a connector socket pin continuity detection system and method for a circuit board, wherein:
本發明所揭露的電路板的連接器插槽腳位導通檢測系統,其包含:具有至少一連接器插槽的待檢測電路板、至少一連接器插槽檢測電路板以及測試存取埠(test access port,TAP)控制器。The connector socket pin continuity detection system for a circuit board disclosed in the present invention includes: a circuit board to be tested with at least one connector socket, at least one connector socket detection circuit board, and a test access port (test access port). access port, TAP) controller.
連接器插槽檢測電路板具有連接器插槽連接器、輸入聯合測試工作群組(joint test action group,JTAG)連接器、輸出JTAG連接器、JTAG晶片以及至少一類比數位轉換器(Analog to digital converter,ADC)、微處理器(microcontroller,MCU)或是開關(switch)其中之一,ADC或是微處理器分別與連接器插槽連接器以及JTAG晶片電性連接或是開關分別與連接器插槽連接器、JTAG晶片以及輸入JTAG連接器電性連接,輸入JTAG連接器分別與JTAG晶片以及輸出JTAG連接器電性連接。The connector slot detection circuit board has a connector slot connector, an input joint test action group (JTAG) connector, an output JTAG connector, a JTAG chip, and at least an analog to digital converter (Analog to digital converter). converter, ADC), microprocessor (MCU) or switch (switch), ADC or microprocessor is respectively electrically connected with the connector socket connector and JTAG chip, or the switch is respectively connected with the connector The socket connector, the JTAG chip and the input JTAG connector are electrically connected, and the input JTAG connector is electrically connected with the JTAG chip and the output JTAG connector respectively.
TAP控制器與連接器插槽檢測電路板其中之一的輸入JTAG連接器電性連接。The TAP controller is electrically connected to the input JTAG connector of one of the connector slot detection circuit boards.
其中,輸出JTAG連接器與其他的連接器插槽檢測電路板之一的輸入JTAG連接器電性連接;及TAP控制器控制JTAG晶片設定邊界掃描(boundary scan)工作模式,並發送對應的控制訊號至對應的JTAG晶片以藉由ADC、微處理器或是開關其中之一讀取對應連接器插槽連接器的檢測腳位的檢測訊號,TAP控制器透過JTAG晶片所提供的檢測訊號以進行對應連接器插槽腳位的導通檢測。The output JTAG connector is electrically connected to the input JTAG connector of one of the other connector socket detection circuit boards; and the TAP controller controls the JTAG chip to set the boundary scan working mode and sends corresponding control signals To the corresponding JTAG chip to read the detection signal of the detection pin of the corresponding connector socket by one of the ADC, microprocessor or switch, the TAP controller uses the detection signal provided by the JTAG chip to correspond Continuity detection of connector socket pins.
本發明所揭露的電路板的連接器插槽腳位導通檢測方法,其包含下列步驟:The method for detecting the continuity of the connector socket pins of the circuit board disclosed in the present invention includes the following steps:
首先,提供具有至少一連接器插槽的待檢測電路板;接著,提供具有連接器插槽連接器、輸入聯合測試工作群組(joint test action group,JTAG)連接器、輸出JTAG連接器、JTAG晶片以及至少一類比數位轉換器(Analog to digital converter,ADC)、微處理器(microcontroller,MCU)或是開關(switch)其中之一的至少一連接器插槽檢測電路板,ADC或是微處理器分別與連接器插槽連接器以及JTAG晶片電性連接或是開關分別與連接器插槽連接器、JTAG晶片以及輸入JTAG連接器電性連接,輸入JTAG連接器分別與JTAG晶片以及輸出JTAG連接器電性連接;接著,提供測試存取埠(test access port,TAP)控制器,TAP控制器與連接器插槽檢測電路板其中之一的輸入JTAG連接器電性連接;接著,其中,輸出JTAG連接器與其他的連接器插槽檢測電路板之一的輸入JTAG連接器電性連接;最後,TAP控制器控制JTAG晶片設定邊界掃描(boundary scan)工作模式,並發送對應的控制訊號至對應的JTAG晶片以藉由ADC、微處理器或是開關其中之一讀取對應連接器插槽連接器的檢測腳位的檢測訊號,TAP控制器透過JTAG晶片所提供的檢測訊號以進行對應連接器插槽腳位的導通檢測。First, provide a circuit board to be tested with at least one connector slot; then, provide a connector with a connector slot, an input joint test action group (JTAG) connector, an output JTAG connector, a JTAG connector A chip and at least one connector slot of at least one of an analog to digital converter (Analog to digital converter, ADC), a microprocessor (microcontroller, MCU), or a switch (switch) detect the circuit board, ADC or microprocessor The connector is respectively electrically connected with the connector socket connector and the JTAG chip, or the switch is electrically connected with the connector socket connector, the JTAG chip and the input JTAG connector respectively, and the input JTAG connector is respectively connected with the JTAG chip and the output JTAG The device is electrically connected; then, a test access port (TAP) controller is provided, and the TAP controller is electrically connected to the input JTAG connector of one of the connector socket detection circuit boards; then, the output The JTAG connector is electrically connected to the input JTAG connector of one of the other connector socket detection circuit boards; finally, the TAP controller controls the JTAG chip to set the boundary scan working mode, and sends the corresponding control signal to the corresponding The JTAG chip is used to read the detection signal of the detection pin of the corresponding connector socket connector by one of ADC, microprocessor or switch, and the TAP controller uses the detection signal provided by the JTAG chip to carry out the corresponding connector. Continuity detection of socket pins.
本發明所揭露的系統及方法如上,與先前技術之間的差異在於於待檢測電路板的連接器插槽上插設對應的連接器插槽檢測電路板,並同時串接不同類型連接器插槽的連接器插槽檢測電路板,透過TAP控制器控制JTAG晶片設定邊界掃描以藉由ADC、微處理器或是開關其中之一讀取對應連接器插槽連接器的檢測腳位的檢測訊號,TAP控制器透過JTAG晶片所提供的檢測訊號以進行對應連接器插槽腳位的導通檢測。The system and method disclosed in the present invention are as above, and the difference between the system and the prior art is that a corresponding connector slot detection circuit board is inserted into the connector slot of the circuit board to be detected, and different types of connector sockets are connected in series at the same time. The connector slot detection circuit board of the slot, controls the JTAG chip to set the boundary scan through the TAP controller, and reads the detection signal corresponding to the detection pin of the connector slot by one of the ADC, the microprocessor or the switch. , The TAP controller conducts the conduction detection of the corresponding connector socket pins through the detection signal provided by the JTAG chip.
透過上述的技術手段,本發明可以達成提高電路板上連接器插槽測試測試效率與覆蓋率的技術功效。Through the above technical means, the present invention can achieve the technical effect of improving the testing efficiency and coverage of the connector socket on the circuit board.
以下將配合圖式及實施例來詳細說明本發明的實施方式,藉此對本發明如何應用技術手段來解決技術問題並達成技術功效的實現過程能充分理解並據以實施。The embodiments of the present invention will be described in detail below with the drawings and examples, so as to fully understand and implement the implementation process of how the present invention applies technical means to solve technical problems and achieve technical effects.
以下將以一個實施例來說明本發明實施態樣的運作系統與方法,並請同時參考「第1圖」、「第2圖」以及「第3A圖」至「第3C圖」所示,「第1圖」繪示為本發明電路板的連接器插槽腳位導通檢測系統的系統方塊圖;「第2圖」繪示為本發明電路板的連接器插槽腳位導通檢測方法的方法流程圖;「第3A圖」至「第3C圖」繪示為本發明電路板的連接器插槽腳位導通檢測的連接器插槽檢測電路板方塊圖。Hereinafter, an embodiment will be used to illustrate the operation system and method of the embodiment of the present invention, and please refer to "Fig. 1", "Fig. 2", and "Fig. 3A" to "Fig. 3C" at the same time, " Figure 1" shows the system block diagram of the connector socket pin continuity detection system of the circuit board of the present invention; "Figure 2" shows the method of the connector socket pin continuity detection method of the circuit board of the present invention Flow charts; "FIG. 3A" to "FIG. 3C" are block diagrams of the connector socket detection circuit board for the connector socket pin conduction detection of the circuit board of the present invention.
本發明所揭露的電路板的連接器插槽腳位導通檢測系統,其包含:具有至少一連接器插槽11的待檢測電路板10(步驟101)、至少一連接器插槽檢測電路板20以及測試存取埠(test access port,TAP)控制器30,上述連接器插槽11包含雙列直插式記憶體模組(dual in-line memory module,DIMM)插槽、快捷外設互聯標準(peripheral component interconnect express,PCI-E)插槽以及通用序列匯流排(universal serial bus,USB)插槽…等,在此僅為舉例說明之,並不以此侷限本發明的應用範疇。The connector socket pin conduction detection system for a circuit board disclosed in the present invention includes: a circuit board to be tested 10 having at least one connector socket 11 (step 101 ), and at least one connector socket
如「第3A圖」所示,連接器插槽檢測電路板20的連接器插槽連接器21為DIMM連接器,連接器插槽檢測電路板20具有連接器插槽連接器21、輸入聯合測試工作群組(joint test action group,JTAG)連接器22、輸出JTAG連接器23、JTAG晶片24以及微處理器(microcontroller,MCU)25(步驟102)。As shown in "FIG. 3A", the
連接器插槽檢測電路板20藉由連接器插槽連接器21插接於待檢測電路板10的連接器插槽11上,且微處理器25分別與連接器插槽連接器21以及JTAG晶片24電性連接,輸入JTAG連接器22分別與JTAG晶片24以及輸出JTAG連接器23電性連接(步驟102)。The connector socket
如「第3B圖」所示,連接器插槽檢測電路板20的連接器插槽連接器21為PCI-E連接器,連接器插槽檢測電路板20具有連接器插槽連接器21、輸入JTAG連接器22、輸出JTAG連接器23、JTAG晶片24以及至少一類比數位轉換器(Analog to digital converter,ADC)26(步驟102)。As shown in FIG. 3B, the
連接器插槽檢測電路板20藉由連接器插槽連接器21插接於待檢測電路板10的連接器插槽11上,且ADC26分別與連接器插槽連接器21以及JTAG晶片24電性連接,輸入JTAG連接器22分別與JTAG晶片24以及輸出JTAG連接器23電性連接(步驟102)。The connector socket
如「第3C圖」所示,連接器插槽檢測電路板20的連接器插槽連接器21為USB連接器,連接器插槽檢測電路板20具有連接器插槽連接器21、輸入JTAG連接器22、輸出JTAG連接器23、JTAG晶片24以及開關(switch)27(步驟102)。As shown in FIG. 3C, the
連接器插槽檢測電路板20藉由連接器插槽連接器21插接於待檢測電路板10的連接器插槽11上,且開關27分別與連接器插槽連接器21、JTAG晶片24以及輸入JTAG連接器22電性連接,輸入JTAG連接器22分別與JTAG晶片24以及所述輸出JTAG連接器23電性連接(步驟102)。The connector socket
TAP控制器30與連接器插槽檢測電路板20其中之一的輸入JTAG連接器22電性連接(步驟103),且連接器插槽檢測電路板20的輸出JTAG連接器23與其他的連接器插槽檢測電路板20之一的輸入JTAG連接器22電性連接(步驟104)。The
TAP控制器30控制連接器插槽檢測電路板20中JTAG晶片24設定邊界掃描(boundary scan)工作模式(步驟105),並且假設正在進行測試的連接器插槽檢測電路板20的連接器插槽連接器21為PCI-E連接器時,該連接器插槽檢測電路板20的JTAG晶片24會被進一步設定為EXTEST模式,其餘未進行測試的連接器插槽檢測電路板20中的JTAG晶片24會被進一步設定為BYPASS模式。The
透過上述設定後,TAP控制器30發送對應的控制訊號至對應的JTAG晶片24以透過ADC26、微處理器25或是開關27其中之一讀取對應連接器插槽連接器21的檢測腳位(檢測腳位例如是:電源腳位、接地腳位、輸入輸出腳位以及差分輸入輸出腳位…等,在此僅為舉例說明之,並不以此侷限本發明的應用範疇)的檢測訊號,TAP控制器30透過JTAG晶片24所提供的檢測訊號以進行對應連接器插槽11腳位的導通檢測(步驟105)。After the above setting, the
在搜索主機板原理圖,確定測試目標引腳時,整條掃描鏈上的所有介面統一處理;具體收集參數和測試時,仍按類型進行分類;測試時,對掃描鏈中不參與測試的治具使用邊界掃描BYPASS指令。如此,可以保證混插在一條掃描鏈上的所有測試治具都被高覆蓋率的測試,且節省測試時間,與拆分成多鏈測試達到相同的測試效率。When searching the schematic diagram of the motherboard and determining the test target pins, all the interfaces on the entire scan chain are processed uniformly; when collecting parameters and testing, they are still classified by type; when testing, the management of the scan chain that does not participate in the test is processed. With the use of boundary scan BYPASS instruction. In this way, it can be ensured that all test fixtures mixed in one scan chain are tested with high coverage rate, and test time is saved, and the test efficiency is the same as that of splitting into multi-chain tests.
綜上所述,可知本發明與先前技術之間的差異在於於待檢測電路板的連接器插槽上插設對應的連接器插槽檢測電路板,並同時串接不同類型連接器插槽的連接器插槽檢測電路板,透過TAP控制器控制JTAG晶片設定邊界掃描以藉由ADC、微處理器或是開關其中之一讀取對應連接器插槽連接器的檢測腳位的檢測訊號,TAP控制器透過JTAG晶片所提供的檢測訊號以進行對應連接器插槽腳位的導通檢測。To sum up, it can be seen that the difference between the present invention and the prior art lies in that a corresponding connector slot detection circuit board is inserted into the connector slot of the circuit board to be detected, and the connectors of different types of connector slots are connected in series at the same time. The connector socket detection circuit board controls the JTAG chip to set the boundary scan through the TAP controller to read the detection signal corresponding to the detection pin of the connector socket by one of the ADC, the microprocessor or the switch, TAP The controller uses the detection signal provided by the JTAG chip to perform the conduction detection of the corresponding connector socket pins.
藉由此一技術手段可以來解決先前技術所存在現有電路板上連接器插槽測試產生測試效率與覆蓋率不足的問題,進而達成提高電路板上連接器插槽測試測試效率與覆蓋率的技術功效。This technical means can solve the problem of insufficient test efficiency and coverage in the prior art for connector socket testing on the existing circuit board, thereby achieving a technology for improving the testing efficiency and coverage of the connector socket on the circuit board. effect.
雖然本發明所揭露的實施方式如上,惟所述的內容並非用以直接限定本發明的專利保護範圍。任何本發明所屬技術領域中具有通常知識者,在不脫離本發明所揭露的精神和範圍的前提下,可以在實施的形式上及細節上作些許的更動。本發明的專利保護範圍,仍須以所附的申請專利範圍所界定者為準。Although the embodiments disclosed in the present invention are as above, the above-mentioned contents are not used to directly limit the scope of the patent protection of the present invention. Anyone with ordinary knowledge in the technical field to which the present invention pertains can make some changes in the form and details of the implementation without departing from the spirit and scope of the present invention. The scope of patent protection of the present invention shall still be defined by the appended patent application scope.
10‧‧‧待檢測電路板11‧‧‧連接器插槽20‧‧‧連接器插槽檢測電路板21‧‧‧連接器插槽連接器22‧‧‧輸入JTAG連接器23‧‧‧輸出JTAG連接器24‧‧‧JTAG晶片25‧‧‧微處理器26‧‧‧ADC27‧‧‧開關30‧‧‧TAP控制器步驟 101‧‧‧提供具有至少一連接器插槽的待檢測電路板步驟 102‧‧‧提供具有連接器插槽連接器、輸入JTAG連接器、輸出JTAG連接器、JTAG晶片以及至少一ADC、微處理器或是開關其中之一的至少一連接器插槽檢測電路板,ADC或是微處理器分別與連接器插槽連接器以及JTAG晶片電性連接或是開關分別與連接器插槽連接器、JTAG晶片以及輸入JTAG連接器電性連接,輸入JTAG連接器分別與JTAG晶片以及輸出JTAG連接器電性連接步驟 103‧‧‧提供TAP控制器,TAP控制器與連接器插槽檢測電路板其中之一的輸入JTAG連接器電性連接步驟 104‧‧‧輸出JTAG連接器與其他的連接器插槽檢測電路板之一的輸入JTAG連接器電性連接步驟 105‧‧‧TAP控制器控制JTAG晶片設定邊界掃描工作模式,並發送對應的控制訊號至對應的JTAG晶片以藉由ADC、微處理器或是開關其中之一讀取對應連接器插槽連接器的檢測腳位的檢測訊號,TAP控制器透過JTAG晶片所提供的檢測訊號以進行對應連接器插槽腳位的導通檢測10‧‧‧Circuit board to be tested 11‧‧‧
第1圖繪示為本發明電路板的連接器插槽腳位導通檢測系統的系統方塊圖。 第2圖繪示為本發明電路板的連接器插槽腳位導通檢測方法的方法流程圖。 第3A圖至第3C圖繪示為本發明電路板的連接器插槽腳位導通檢測的連接器插槽檢測電路板方塊圖。FIG. 1 is a system block diagram of the connector socket pin continuity detection system of the circuit board of the present invention. FIG. 2 is a flow chart of the method for detecting the continuity of the connector socket pins of the circuit board according to the present invention. FIG. 3A to FIG. 3C are block diagrams of the connector socket detection circuit board for detecting the continuity of the connector socket pins of the circuit board of the present invention.
10‧‧‧待檢測電路板 10‧‧‧Circuit board to be tested
11‧‧‧連接器插槽 11‧‧‧Connector slot
20‧‧‧連接器插槽檢測電路板 20‧‧‧Connector socket detection circuit board
21‧‧‧連接器插槽連接器 21‧‧‧Connector Slot Connector
22‧‧‧輸入JTAG連接器 22‧‧‧Input JTAG connector
23‧‧‧輸出JTAG連接器 23‧‧‧Output JTAG connector
30‧‧‧TAP控制器 30‧‧‧TAP Controller
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US20100153797A1 (en) * | 2008-12-17 | 2010-06-17 | Samsung Electronics Co., Ltd. | Apparatus and method of authenticating Joint Test Action Group (JTAG) |
US20170184668A1 (en) * | 2015-12-24 | 2017-06-29 | Inventec (Pudong) Technology Corporation | Test circuit board adapted to be used on memory slot |
US20170184669A1 (en) * | 2015-12-24 | 2017-06-29 | Inventec (Pudong) Technology Corporation | Test circuit board adapted to be used on peripheral component interconnect express slot |
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US20100153797A1 (en) * | 2008-12-17 | 2010-06-17 | Samsung Electronics Co., Ltd. | Apparatus and method of authenticating Joint Test Action Group (JTAG) |
US20170184668A1 (en) * | 2015-12-24 | 2017-06-29 | Inventec (Pudong) Technology Corporation | Test circuit board adapted to be used on memory slot |
US20170184669A1 (en) * | 2015-12-24 | 2017-06-29 | Inventec (Pudong) Technology Corporation | Test circuit board adapted to be used on peripheral component interconnect express slot |
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