TWI550294B - Test circuit board for memory slot testing - Google Patents

Description

Test board for memory slots

A circuit board, in particular, a test circuit board suitable for a memory socket having a first joint test work group connection interface and a second joint test work group connection interface to form a test circuit board in series with each other.

Most of the tests for the memory slots in the board to be tested are mostly performed using a single test board. However, the test of the memory slots in the board to be tested using a single test board can only test a single memory slot, often There will be problems with the lack of coverage of the test signal, which is not conducive to production test use.

In summary, it has been known in the prior art that there has been a problem in the prior art that the test signal coverage of the memory slot in the board to be tested is insufficient, and therefore it is necessary to propose an improved technical means to solve this problem.

In view of the prior art, there is a problem that the test signal coverage of the memory slot in the board to be tested is insufficient. The present invention discloses a test circuit board suitable for a memory socket, wherein:

The test circuit board suitable for the memory socket disclosed in the present invention comprises: a test circuit board, the test circuit board further comprises: a memory connection interface, a first joint test work group (JTAG) connection Interface, second joint test work group connection interface, joint test work group signal processing chip, at least one joint test work group control chip, at least one analog-to-digital converter (ADC) chip, switch ( Switch) wafer and voltage conversion wafer.

The memory connection interface is for inserting into the memory slot to form an electrical connection; the first joint test work group connection interface is for electrically connecting to the test access port (TAP) controller. Or used to electrically connect with the second joint test work group connection interface of other test boards to form a serial connection with other test boards; the second joint test work group connection interface is used with other test boards The first joint test work group connection interface electrical connection; the joint test work group signal processing chip is electrically connected to the first joint test work group and the second joint test work group, respectively, to improve the first joint test The stability of the joint test work group signal transmitted by the work group and the second joint test work group; at least one joint test work group control chip, joint test work group control chip and joint test work group signal processing chip power Sexual connection for detecting the position of the memory slot, status control, and integrated circuit (IIC) Simulation; at least one analog-to-digital conversion chip is an analog digital conversion chip and a joint test work group control chip electrical connection for voltage detection of the memory socket pin; the switch chip is separately controlled with the joint test work group The chip and the analog digital conversion chip are electrically connected to detect the special signal of the memory socket, so that the special signal can be detected through the joint test work group control chip or through the analog digital conversion chip; and the voltage The conversion chip is used to obtain a power supply through the memory slot and convert the power supply to provide a combined test work group signal processing chip, a joint test work group control chip, and an analog digital conversion wafer switch wafer.

The circuit board disclosed in the present invention is different from the prior art in that the test circuit board is connected to each other through the first joint test work group connection interface and the second joint test work group connection interface of the test circuit board. The serial connection can be formed to reduce the requirement of the number of test access ports in the test access controller, and the test circuit board proposed by the present invention provides test signal coverage for all test signals, facilitating the use of the production line, thereby reducing the test. The cost of the board.

Through the above technical means, the present invention can achieve the technical effect of reducing the number of test access points in the test access controller and providing test signal coverage for all test signals.

The embodiments of the present invention will be described in detail below with reference to the drawings and embodiments, so that the application of the technical means to solve the technical problems and achieve the technical effects can be fully understood and implemented.

The following is a description of the test circuit board for the memory slot disclosed in the present invention. Please refer to "1" and "2", and "FIG. 1" shows the present invention for memory. Schematic diagram of the structure of the body socket test circuit board; "Fig. 2" shows the architecture of the present invention when it is applied to the test of the memory socket test circuit board.

The test circuit board 10 disclosed by the present invention further includes: a memory connection interface 11, a first joint test work group (JTAG) connection interface 12, a second joint test work group connection interface 13, and a joint test. The work group signal processing chip 14, the at least one joint test work group control chip 15, the at least one analog-to-digital converter (ADC) chip 16, the switch chip 17 and the voltage conversion chip 18.

The board to be tested 20 further includes a central processing unit (CPU) 21, a plurality of memory slots 22, and a complex programmable logic device (CPLD) 23.

The memory connection interface 11 of the test circuit board 10 is configured to provide the test circuit board 10 to be inserted into the memory socket 22 of the board to be tested 20 to electrically connect the test circuit board 10 to the board 20 to be tested. Each of the memory slots 22 of the board to be tested 20 can be plugged into a test board 10.

The first joint test work group connection interface 12 of the test circuit board 10 is for electrically connecting to the test access controller 30, or the first joint test work group connection interface 12 of the test circuit board 10 is for The second joint test work group connection interface 13 of the other test circuit board 10 is electrically connected to form the test circuit board 10 in series with the other test circuit boards 10.

Specifically, the to-be-tested board 20 has a first memory slot 221 and a second memory slot 222. The first test circuit board 101 is plugged into the first memory slot 221 of the board 20 to be tested. The second test circuit board 102 is inserted into the second memory slot 222 of the board 20 to be tested. The first joint test work group connection interface 12 of the first test circuit board 101 is electrically connected to the test access controller 30. The second joint test working group connection interface 13 of the first test circuit board 101 is electrically connected to the first joint test work group connection interface 12 of the second test circuit board 102, so that the first test circuit board 101 and the first The two test circuit boards 102 are formed in series and are merely illustrative here and are not intended to limit the scope of application of the present invention.

The joint test work group signal processing chip 14 of the test circuit board 10 is electrically connected to the first joint test work group 12 of the test circuit board 10 and the second joint test work group 13 of the test circuit board 10, respectively. The joint test work group signal processing chip 14 of 10 is used to improve the first joint test work group 12 of the test circuit board 10 and the joint test work group signal transmitted by the second joint test work group 13 of the test circuit board 10. Stability.

The central processing unit 21 of the board 20 to be tested is used to provide a Boundary Scan mode for testing by the test circuit board 10. The complex programmable logic element 23 of the board 20 to be tested is used to control the machine to be tested. The power state of the board 20.

The test access controller 30 is also electrically coupled to the central processor 21 of the board 20 to be tested and the complex programmable logic element 23 of the board 20 to be tested, and the test access controller 30 controls the board to be tested. The complex programmable logic element 23 of 20 controls the power supply state of the board 20 to be tested, and the test access controller 30 also controls the central processor 21 of the board 20 to be tested and the complexity of the board 20 to be tested. The logic component 23 is programmed to the boundary scan mode of operation, and the test access controller 30 controls the test circuit board 10 to the boundary scan mode of operation through the first joint test workgroup connection interface 12 of the test circuit board 10.

The joint test work group control chip 15 of the test circuit board 10 is electrically connected to the joint test work group signal processing chip 14 of the test circuit board 10, and the joint test work group control chip 15 of the test circuit board 10 is used for waiting. The detection of the memory slot 22 of the tester board 20, the control of the state of the test board 10, and the simulation of the integrated circuit bus of the test board 10.

The analog digital conversion chip 16 of the test circuit board 10 is electrically connected to the joint test work group control chip 15 of the test circuit board 10, and the analog digital conversion chip 16 of the test circuit board 10 is used for the memory of the machine board 20 to be tested. Voltage detection at slot pin 22.

The switch wafer 17 of the test circuit board 10 is electrically connected to the joint test work group control chip 15 of the test circuit board 10 and the analog digital conversion chip 16 of the test circuit board 10, respectively. The switch wafer 17 of the test circuit board 10 is used to The detection of the special signal of the memory slot 22 of the board to be tested 20 is performed so that the special signal can be detected by the joint test work group control chip 15 or by the analog digital conversion chip 16.

The voltage conversion chip 18 of the test circuit board 10 is used to obtain a power supply through the memory slot 22 of the test circuit board 10 and convert the power supply to provide the test circuit board 10 for the joint test work group signal processing chip 14, the test circuit The joint test work group of the board 10 controls the operating voltage required for the wafer 15, the analog digital conversion wafer switch wafer 16 of the test circuit board 10, and the switch wafer 17 of the test circuit board 10.

The test access controller 30 is tested by the test circuit board 10 in the boundary scan mode of operation of the complex programmable logic component 23 of the board to be tested 20, the central processor 21 of the board 20 to be tested, and the test board 10. The work group control chip 14, the analog digital conversion chip 15 of the test circuit board 10, and the switch wafer 16 of the test circuit board 10 for detecting the position of the memory socket 22 of the board to be tested 20, state control, and integrated circuit The simulation of the bus bar, the voltage detection of the memory slot 22 of the board to be tested 20, and the detection of the special signal of the memory slot 22 of the board 20 to be tested.

In summary, it can be seen that the difference between the present invention and the prior art is that the test circuit board can be connected to each other through the first joint test work group connection interface and the second joint test work group connection interface of the test circuit board. The serial connection is formed to reduce the requirement of the number of test access ports in the test access controller, and the test circuit board proposed by the present invention provides test signal coverage for all test signals, facilitating the use of the production line, thereby reducing the test circuit. The cost of the board.

The technical problem can be solved by the prior art that the existing test signal coverage of the memory slot in the board to be tested is insufficient, and the requirement for reducing the number of test access points in the test access controller is achieved. Provides technical power for test signal coverage of all test signals.

While the embodiments of the present invention have been described above, the above description is not intended to limit the scope of the invention. Any changes in the form and details of the embodiments may be made without departing from the spirit and scope of the invention. The scope of the invention is to be determined by the scope of the appended claims.

10‧‧‧Test circuit board
101‧‧‧First test board
102‧‧‧Second test circuit board
11‧‧‧Memory connection interface
12‧‧‧First Joint Test Workgroup Connection Interface
13‧‧‧Second joint test work group connection interface
14‧‧‧Joint test workgroup signal processing chip
15‧‧‧Joint Test Workgroup Control Wafer
16‧‧‧ analog digital conversion chip
17‧‧‧Switch wafer
18‧‧‧Voltage conversion chip
20‧‧‧Test board
21‧‧‧Central Processing Unit
22‧‧‧Memory slot
221‧‧‧First memory slot
222‧‧‧Second memory slot
23‧‧‧Complex programmable logic components

FIG. 1 is a schematic diagram showing the structure of a test circuit board suitable for a memory socket according to the present invention. FIG. 2 is a schematic diagram showing the architecture of the present invention when it is applied to a memory socket test circuit board.

10‧‧‧Test circuit board

11‧‧‧Memory connection interface

12‧‧‧First Joint Test Workgroup Connection Interface

13‧‧‧Second joint test work group connection interface

14‧‧‧Joint test workgroup signal processing chip

15‧‧‧Joint Test Workgroup Control Wafer

16‧‧‧ analog digital conversion chip

17‧‧‧Switch wafer

18‧‧‧Voltage conversion chip

Claims (7)

A test circuit board suitable for a memory socket, comprising: a test circuit board, the test circuit board further comprising: a memory connection interface for plugging in a memory socket to form an electrical connection; a first Joint Test Action Group (JTAG) connection interface for electrically connecting to a Test Access Port (TAP) controller or for use with other test circuit boards The second joint test work group connection interface is electrically connected to form a serial connection with the other test circuit boards; a second joint test work group connection interface is used for the other test board a joint test work group connection interface electrical connection; a joint test work group signal processing chip, the joint test work group signal processing chip and the first joint test work group and the second joint test respectively The work group is electrically connected to improve the stability of the joint test work group signal transmitted by the first joint test work group and the second joint test work group At least one joint test work group control chip, the joint test work group control chip and the joint test work group signal processing chip are electrically connected for detecting and controlling the state of the memory slot And an analog of an integrated circuit (IIC); at least one analog-to-digital converter (ADC) chip, the analog digital conversion chip and the joint test work group control chip Electrically connected for voltage detection of a memory socket; a switch chip electrically connected to the joint test work group control chip and the analog digital conversion chip, Detecting a special signal for the memory slot pin so that the special signal can be detected by the joint test work group control chip or by the analog digital conversion chip; and a voltage conversion chip, For obtaining power supply through the memory slot and converting the power to provide the joint test work group signal Wafer processing, the wafer joint control testing group, the ADCs wafer wafer switches required operating voltage. The test circuit board for a memory slot according to the first aspect of the patent application, further comprising a board to be tested, wherein the board to be tested further comprises: a central processing unit (CPU) For providing a Boundary Scan mode for detection by the test board; a plurality of memory slots for providing the test circuit board plug; and a complex programmable logic component (Complex Programmable) Logic Device (CPLD) is used to control the power state of the board to be tested. The test circuit board for a memory slot as described in claim 2, wherein the test access controller is respectively associated with the central processor, the complex programmable logic element, and the A joint test work group connection interface is electrically connected. The test circuit board for a memory slot as described in claim 3, wherein the test access controller controls the complex programmable logic element to control power supply of the board to be tested status. A test circuit board for a memory slot as described in claim 3, wherein the test access controller controls the complex programmable logic element and the central processor to boundary scan (Boundary Scan) working mode. A test circuit board for a memory slot as described in claim 1, wherein the test access controller controls the test circuit board to a boundary scan mode of operation. A test circuit board suitable for a memory slot as described in claim 3, wherein the test access controller is in the complex programmable logic element, the central processing unit, and the test circuit In the boundary scan mode of the board, the detection of the memory slot pin, the state control, the simulation of the integrated circuit bus, the voltage detection of the memory slot pin, and the detection of the special signal of the memory slot pin are performed.