CN103901340A - Chip testing method - Google Patents
Chip testing method Download PDFInfo
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- CN103901340A CN103901340A CN201410153911.8A CN201410153911A CN103901340A CN 103901340 A CN103901340 A CN 103901340A CN 201410153911 A CN201410153911 A CN 201410153911A CN 103901340 A CN103901340 A CN 103901340A
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- chip
- toggle switch
- tektronix
- graphic instrument
- electrically connected
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Abstract
The invention discloses a chip testing method which comprises the followings steps that a chip to be tested is arranged on a chip testing seat, the chip testing seat with the installed chip to be tested is electrically connected with a Tektronix 370A type transistor graphic instrument in a pluggable mode, and the Tektronix 370A type transistor graphic instrument is used for testing parameters of the chip to be tested. In test, operators only need to plug or unplug the chip testing seat for connection, manual wiring is omitted, operation is simple, errors can not easily occur, and chip testing efficiency is greatly improved.
Description
Technical field
The present invention relates to chip testing field, particularly a kind of chip detecting method that utilizes Tektronix370A transistor graphic instrument test chip.
Background technology
While utilizing at present Tektronix 370A transistor graphic instrument to semiconductor die testing, need to manually use with the conductor connecting core sheet respective pins of plug and arrive in the respective socket of transistor graphic instrument, realize being connected of chip and transistor graphic instrument, thereby complete the test of follow-up different unit for electrical property parameters, this mode needs the artificial line of operating personnel, and do not stop to plug line trap and be connected on transistor graphic instrument, complex operation is easily made mistakes, and chip testing efficiency is low.
Summary of the invention
The object of the invention is to overcome existing above-mentioned deficiency in prior art, provide a kind of simple to operate, the chip detecting method that chip testing efficiency is high.
In order to realize foregoing invention object, the technical solution used in the present invention is:
A kind of chip detecting method, comprises the steps:
A, chip to be measured is installed on chip test base;
B, the chip test base that installs chip to be measured is pegged graft and is electrically connected with Tektronix 370A transistor npn npn graphic instrument;
C, utilize Tektronix 370A transistor npn npn graphic instrument to carry out parameter testing to chip to be measured.
Wherein, described chip test base comprises pedestal, described pedestal lower surface arranges at least one pair of pin for socket connection Tektronix 370A transistor npn npn graphic instrument, described pair of pins is connected with one group of test jack adaptation on Tektronix 370A transistor npn npn graphic instrument, described pedestal upper surface is provided with the first toggle switch, the second toggle switch and chip fixture, a pin and described the first toggle switch in described pair of pins are electrically connected, described the first toggle switch and described chip fixture are electrically connected, described chip fixture and described the second toggle switch are electrically connected, another pin in described the second toggle switch and described pair of pins is electrically connected.
Preferably, the pin of the pedestal lower surface of described chip test base has 3 pairs, every pair of pins respectively with Tektronix 370A transistor npn npn graphic instrument on one group of test jack adaptation.
Preferably, described the first toggle switch and described the second toggle switch are symmetricly set on described pedestal upper surface two ends, and described chip fixture is between the first toggle switch and the second toggle switch.
Preferably, described chip fixture comprises body, and this body has for the fixing pickup groove of chip and stitch for contacting with chip pin, and described stitch is positioned at the two bottom sides of described pickup groove and stretches out described body.
compared with prior art, beneficial effect of the present invention:
The inventive method is installed on chip to be measured on chip test base, the chip test base that installs chip to be measured is electrically connected with Tektronix 370A transistor npn npn graphic instrument, then utilize Tektronix 370A transistor npn npn graphic instrument to carry out parameter testing to chip to be measured, operating personnel only need plug chip test base and connect chip and testing tool, remove manual line from, simple to operate being difficult for makes mistakes, and chip testing efficiency improves greatly.
accompanying drawing explanation:
Fig. 1 is chip detecting method process flow diagram of the present invention;
Fig. 2 is the structural representation of the chip test base in the embodiment of the present invention;
Fig. 3 is the structural representation of the chip fixture in Fig. 2;
Fig. 4 is the circuit block diagram of the chip test base in the embodiment of the present invention;
Fig. 5 is the transistor graphic instrument schematic diagram in the embodiment of the present invention.
Embodiment
Below in conjunction with embodiment, the present invention is described in further detail.But this should be interpreted as to the scope of the above-mentioned theme of the present invention only limits to following embodiment, all technology realizing based on content of the present invention all belong to scope of the present invention.
Chip detecting method process flow diagram as shown in Figure 1, chip detecting method of the present invention comprises the steps:
S1, chip to be measured is installed on chip test base.
Concrete, referring to Fig. 2, this chip test base comprises pedestal 1, described pedestal 1 lower surface arranges at least one pair of pin 2 for socket connection Tektronix 370A transistor npn npn graphic instrument (see figure 4).One group of test jack adaptation on described pair of pins and this Tektronix 370A transistor npn npn graphic instrument, pin 2 described in the present embodiment is take two pairs as example explanation, on described transistor graphic instrument, there are multiple test jack, one group of test jack adaptation on described pair of pins 2 and this transistor graphic instrument, Fig. 2 is only schematic diagram, where pin 2 is to determine according to the test jack position on transistor graphic instrument if being arranged on pedestal 1 lower surface, both want adaptive mutually, peg graft so that aim at.Described pedestal 1 upper surface is provided with the first toggle switch 3, the second toggle switch 4 and chip fixture 5, referring to Fig. 4, a pin and described the first toggle switch 3 in described pair of pins 2 are electrically connected, described the first toggle switch 3 is electrically connected with described chip fixture 5, described chip fixture 5 is electrically connected with described the second toggle switch 4, and described the second toggle switch 4 is electrically connected with another pin in described pair of pins 2.Preferably, described the first toggle switch 3 is symmetricly set on described pedestal 1 upper surface two ends with described the second toggle switch 4, and described chip fixture 5 is between the first toggle switch 3 and the second toggle switch 4.Toggle switch (3,4) comprises multiple toggle switches unit, the present embodiment is take 2 waved switch unit as example explanation, a waved switch unit on each toggle switch, i.e. one end, one group of waved switch unit pair of pins 2 of connecting test seat lower surface respectively, this group waved switch unit other end is electrically connected with described chip fixture 5 respectively again.Referring to Fig. 3, chip fixture 5 comprises body 501, on body 501, there is the pickup groove 502 and the stitch 503 that with chip pin contact fixing for chip, described stitch 503 is positioned at the two bottom sides of described pickup groove 502 and stretches out described body 501, chip to be measured is put into chip fixture 5 fixing, chip respective pins is electrically connected with two toggle switchs (3,4) by the stitch 503 on chip fixture 5.
S2, the chip test base that installs chip to be measured is electrically connected with Tektronix 370A transistor npn npn graphic instrument.The pin 2 of chip test base inserts the corresponding test jack of Tektronix 370A transistor npn npn graphic instrument, has so just realized the electric connection of chip to be measured and Tektronix 370A transistor npn npn graphic instrument, after having tested, can extract chip test base.
S3, utilize Tektronix 370A transistor npn npn graphic instrument to carry out parameter testing to chip to be measured, realize the control of test circuit by two toggle switchs on chip test base, chip to be measured is carried out at least one unit for electrical property parameters test, when test, operating personnel only need plug chip test base connection, remove manual line from, simple to operate being difficult for makes mistakes, and also makes chip testing efficiency greatly improve.
The present invention utilizes for convenience Tektronix 370A transistor npn npn graphic instrument test chip and invents, design for Tektronix 370A transistor npn npn graphic instrument specially, when test, chip is put into chip fixture 5 fixing, chip respective pins is by stitch 503 and two toggle switchs (3 on chip fixture 5, 4) electrical connection, and two toggle switchs (i.e. one group of waved switch unit) are electrically connected with the pair of pins 2 of chip test base lower surface respectively, when test, at least one pair of pin 2 of chip test base lower surface is inserted in the corresponding test jack of Tektronix 370A transistor npn npn graphic instrument, realize being electrically connected of chip pin and Tektronix 370A transistor npn npn graphic instrument, realize the control of test circuit by two toggle switchs on chip test base, operating personnel only need plug chip test base and connect, remove manual line from, simple to operate being difficult for makes mistakes, also make chip testing efficiency greatly improve.
As preferred version of the present invention, the pin of described test bench lower surface has 3 pairs of (not shown), every pair of pins respectively with Tektronix 370A transistor npn npn graphic instrument on one group of test jack adaptation.Toggle switch comprises multiple toggle switches unit, a waved switch unit on each toggle switch, i.e. one group of waved switch unit pair of pins of connecting test seat lower surface respectively, this group waved switch unit other end is electrically connected with described chip fixture respectively again, chip fixture has the stitch contacting with chip pin, waved switch unit is connected with the corresponding stitch of chip fixture, test bench pin inserts the corresponding test jack of Tektronix 370A transistor npn npn graphic instrument, so just realize being connected of chip and Tektronix 370A transistor npn npn graphic instrument, each group jack on Tektronix 370A transistor npn npn graphic instrument is for testing different parameters, break-make by toggle switch unit on two toggle switchs when test combines, realize the connection of chip pin and the different test jack of Tektronix 370A transistor npn npn graphic instrument, can conveniently carry out multiple parameters test, testing efficiency further improves.
The present invention is installed on chip to be measured on chip test base, the chip test base and the Tektronix 370A transistor npn npn graphic instrument that install chip to be measured are pegged graft, then utilize Tektronix 370A transistor npn npn graphic instrument to carry out parameter testing to chip to be measured, operating personnel only need plug chip test base and connect, remove manual line from, simple to operate being difficult for makes mistakes, and chip testing efficiency improves greatly.
By reference to the accompanying drawings the specific embodiment of the present invention is had been described in detail above, but the present invention is not restricted to above-mentioned embodiment, in the spirit and scope situation of claim that does not depart from the application, those skilled in the art can make various modifications or remodeling.
Claims (5)
1. a chip detecting method, is characterized in that, comprises the steps:
A, chip to be measured is installed on chip test base;
B, the chip test base that installs chip to be measured is pegged graft and is electrically connected with Tektronix 370A transistor npn npn graphic instrument;
C, utilize Tektronix 370A transistor npn npn graphic instrument to carry out parameter testing to chip to be measured.
2. chip detecting method according to claim 1, it is characterized in that, described chip test base comprises pedestal, described pedestal lower surface arranges at least one pair of pin for socket connection Tektronix 370A transistor npn npn graphic instrument, described pair of pins is connected with one group of test jack adaptation on Tektronix 370A transistor npn npn graphic instrument, described pedestal upper surface is provided with the first toggle switch, the second toggle switch and chip fixture, a pin and described the first toggle switch in described pair of pins are electrically connected, described the first toggle switch and described chip fixture are electrically connected, described chip fixture and described the second toggle switch are electrically connected, another pin in described the second toggle switch and described pair of pins is electrically connected.
3. chip detecting method according to claim 2, is characterized in that, the pin of the pedestal lower surface of described chip test base has 3 pairs, every pair of pins respectively with Tektronix 370A transistor npn npn graphic instrument on one group of test jack adaptation.
4. chip detecting method according to claim 2, is characterized in that, described the first toggle switch and described the second toggle switch are symmetricly set on described pedestal upper surface two ends, and described chip fixture is between the first toggle switch and the second toggle switch.
5. chip detecting method according to claim 2, it is characterized in that, described chip fixture comprises body, and this body has for the fixing pickup groove of chip and stitch for contacting with chip pin, and described stitch is positioned at the two bottom sides of described pickup groove and stretches out described body.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410153911.8A CN103901340A (en) | 2014-04-16 | 2014-04-16 | Chip testing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410153911.8A CN103901340A (en) | 2014-04-16 | 2014-04-16 | Chip testing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103901340A true CN103901340A (en) | 2014-07-02 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410153911.8A Pending CN103901340A (en) | 2014-04-16 | 2014-04-16 | Chip testing method |
Country Status (1)
| Country | Link |
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| CN (1) | CN103901340A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107526026A (en) * | 2017-08-31 | 2017-12-29 | 京东方科技集团股份有限公司 | Inspection tool for FPC grafting |
| CN111707929A (en) * | 2020-06-29 | 2020-09-25 | 深圳赛西信息技术有限公司 | PGA packaging microwave test fixture |
Citations (8)
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|---|---|---|---|---|
| US6262581B1 (en) * | 1998-04-20 | 2001-07-17 | Samsung Electronics Co., Ltd. | Test carrier for unpackaged semiconducter chip |
| US6340838B1 (en) * | 1998-04-08 | 2002-01-22 | Samsung Electronics Co., Ltd. | Apparatus and method for containing semiconductor chips to identify known good dies |
| CN2704050Y (en) * | 2003-12-12 | 2005-06-08 | 上海新建仪器设备有限公司 | Surface-pasted semiconductor device test seat |
| CN101226224A (en) * | 2008-01-16 | 2008-07-23 | 深圳国人通信有限公司 | Test system and method for circuit board |
| CN101226233A (en) * | 2007-01-19 | 2008-07-23 | 旺宏电子股份有限公司 | Method and apparatus for testing chip testing mechanism |
| CN101452030A (en) * | 2007-11-28 | 2009-06-10 | 京元电子股份有限公司 | Test device with switching element on socket substrate |
| CN102128956A (en) * | 2010-01-19 | 2011-07-20 | 中芯国际集成电路制造(上海)有限公司 | Connecting plate for test socket |
| CN203519658U (en) * | 2013-09-03 | 2014-04-02 | 苏州创瑞机电科技有限公司 | Automatic test socket of megapixel-level CMOS optical chip module |
-
2014
- 2014-04-16 CN CN201410153911.8A patent/CN103901340A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6340838B1 (en) * | 1998-04-08 | 2002-01-22 | Samsung Electronics Co., Ltd. | Apparatus and method for containing semiconductor chips to identify known good dies |
| US6262581B1 (en) * | 1998-04-20 | 2001-07-17 | Samsung Electronics Co., Ltd. | Test carrier for unpackaged semiconducter chip |
| CN2704050Y (en) * | 2003-12-12 | 2005-06-08 | 上海新建仪器设备有限公司 | Surface-pasted semiconductor device test seat |
| CN101226233A (en) * | 2007-01-19 | 2008-07-23 | 旺宏电子股份有限公司 | Method and apparatus for testing chip testing mechanism |
| CN101452030A (en) * | 2007-11-28 | 2009-06-10 | 京元电子股份有限公司 | Test device with switching element on socket substrate |
| CN101226224A (en) * | 2008-01-16 | 2008-07-23 | 深圳国人通信有限公司 | Test system and method for circuit board |
| CN102128956A (en) * | 2010-01-19 | 2011-07-20 | 中芯国际集成电路制造(上海)有限公司 | Connecting plate for test socket |
| CN203519658U (en) * | 2013-09-03 | 2014-04-02 | 苏州创瑞机电科技有限公司 | Automatic test socket of megapixel-level CMOS optical chip module |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107526026A (en) * | 2017-08-31 | 2017-12-29 | 京东方科技集团股份有限公司 | Inspection tool for FPC grafting |
| CN107526026B (en) * | 2017-08-31 | 2020-04-28 | 京东方科技集团股份有限公司 | A inspection tool for FPC pegs graft |
| CN111707929A (en) * | 2020-06-29 | 2020-09-25 | 深圳赛西信息技术有限公司 | PGA packaging microwave test fixture |
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Application publication date: 20140702 |
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