TW201823754A - Testing circuit board with self-detection function and self-detection method thereof - Google Patents

Abstract

A Testing circuit board with self-detection function and a self-detection method are provided. A test for tested circuit board is executed and a self-detection testing for test circuit board is performed by a JTAG chip at the same time. A first JTAG connection interface and a second JTAG connection interface are conducted by a controller, a multiplexer and a switch chip to connect test circuit boards in series. Therefore, the efficiency of solving self-detection of JTAG chip with series connection conveniently and quickly may be achieved.

Description

Test circuit board with self-detection function and self-detection method thereof

A test circuit board and a self-detection method thereof, in particular, a method for testing a circuit board to be tested and self-testing of a test circuit board by jointly testing a work group chip, and working on the first joint test when the self test passes The group connection interface and the second joint test work group connection interface are connected through the controller, the data multiplexer, and the switch chip to connect the test circuit board with the self-test function test board and the self-test method thereof.

In the board test and detection technology, boundary scan technology is used more and more widely. When using boundary scan in practice, one way is to connect multiple test boards together to form a joint test work group chain. To conduct a large number of joint test work group connection interface tests.

It is connected in series through multiple test boards by connecting the joint test work group signals of the joint test work group chip, that is, the test clock (TCK) and the test mode selection (Test Mode Select). , TMS) is connected in parallel, and Test Data Input (TDI) and Test Data Output (TDO) are connected in series to form a joint test work group chain for a large number of Test the joint test workgroup connection interface.

However, if there is a failure of the joint test work group chip in the joint test work group chain, it will be difficult to find out which joint test work group chip is faulty under the existing test architecture. If the joint test is to confirm the fault. The workgroup chip will inevitably take a huge amount of inspection time to find the failed joint test workgroup chip.

In summary, it can be seen that the existing tandem joint test work group wafer method has long been inconvenient and time consuming in the prior art, and therefore it is necessary to propose an improved technical means to solve this problem.

In view of the prior art, the existing tandem joint test work group wafer method has the problem of inconvenient and time-consuming fault detection, and the present invention discloses a test circuit board with self-detection function and a self-test method thereof, wherein:

The self-detecting test circuit board disclosed in the present invention comprises: a first joint test work group (Joint Test Action Group) connection interface, a joint test work group chip, a controller, a data multiplexer (multiplexer, MUX), a switch chip, a buffer, a second joint test work group connection interface, and a test connection interface, wherein the first joint test work group connection interface includes a first test clock (TCK) pin Bit, the first Test Mode Select (TMS) pin, the first Test Data Input (TDI) pin, and the first Test Data Output (TDO) pin; and the second The joint test work group connection interface includes a second test clock pin, a second test mode select pin, a second test data input pin, and a second test data output pin.

The first joint test work group connection interface is used to electrically connect with the joint test work group controller or other test circuit boards; jointly test the work group chip and the first test clock pin, the first test mode selection The pin and the first test data input pin are electrically connected, and the joint test work group controller controls the joint test work group wafer for self-test of the test circuit board, and when the joint test work group wafer passes the test circuit board The self-test generates a communication signal; the controller is electrically connected to the joint test work group chip; the data multiplexer and the joint test work group chip data output pin and the controller are electrically connected, in the preset setting, the first A test data output pin is electrically connected to the data output pin of the joint test work group chip through the data multiplexer; the switch chip is electrically connected to the first test data output pin, the controller, and the data multiplexer; The register is electrically connected to the first test clock pin and the first test mode selection pin; the second joint test work group is connected The first test test work group connection interface is electrically connected to the other test circuit board, the second test clock pin and the second test mode selection pin are electrically connected to the temporary register, and the second test data input The pin is electrically connected to the data multiplexer, and the second test data output pin is electrically connected to the switch chip; and the test connection interface is electrically connected to the joint test work group chip and the circuit board to be tested respectively, and the joint test work group The group wafer is tested by the test connection interface to test the board.

When the joint test work group chip generates a communication signal, the controller receives the communication signal from the joint test work group chip to generate a selection signal (Select, SEL), and the data multiplexer turns on the first test data input pin according to the selection signal. The second test data input pin, the switch chip interrupts the electrical connection between the first test data output pin and the data output pin of the joint test work group chip according to the selection signal, and turns on the second test data output pin and the joint test. The data output pin of the work group chip is such that the first joint test work group connection interface and the second joint test work group connection interface are mutually conductive, and the test circuit boards are provided to each other through the first joint test work group The connection interface and the second joint test work group connection interface are connected in series.

The self-detection method for the self-test function test circuit board disclosed in the present invention comprises the following steps:

First, provide a joint test action group (Joint Test Action Group) connection interface, joint test work group chip, controller, data multiplexer (MUX), switch chip, buffer (Buffer) a second joint test work group connection interface and a test circuit board for testing the connection interface; then, the first joint test work group connection interface includes a first test clock (TCK) pin, and a first test mode selection ( Test Mode Select, TMS) pin, the first Test Data Input (TDI) pin and the first Test Data Output (TDO) pin; then, the second joint test work group connection interface The second test clock pin, the second test mode select pin, the second test data input pin, and the second test data output pin are included; then, the first joint test work group connection interface and the joint test work group control Or the second joint test work group of the other test circuit board is connected to the interface electrical connection; then, the joint test work group crystal The chip is electrically connected to the first test clock pin, the first test mode select pin, and the first test data input pin; then, the controller is electrically connected to the joint test work group chip; then, the data multiplexer and The data output pin of the joint test work group chip and the controller are electrically connected. In the preset setting, the first test data output pin is transmitted through the data multiplexer and the data output pin of the joint test work group chip. The switch is electrically connected to the first test data output pin, the controller, and the data multiplexer; then, the register is electrically connected to the first test clock pin and the first test mode select pin. Then, the second test clock pin and the second test mode selection pin are electrically connected to the temporary register, the second test data input pin is electrically connected to the data multiplexer, and the second test data output pin and switch The chip is electrically connected; then, the test connection interface is electrically connected to the joint test work group chip and the circuit board to be tested respectively; then, the joint test work group controller controls Testing the workgroup wafer to test the test board through the test connection interface; then, the joint test workgroup controller controls the joint test workgroup wafer for self-test of the test board; then, when the joint test The working group chip generates a communication signal by self-detection of the test circuit board; then, the controller receives the communication signal from the joint test work group chip to generate a selection signal (Select, SEL); finally, the data multiplexer is interrupted according to the selection signal The first test data output pin is electrically connected with the data output pin of the joint test work group chip, and the second test data input pin and the data output pin of the joint test work group chip are turned on, and the switch chip is selected according to the selection. The signal turns on the first test data output pin and the second test data output pin, so that the first joint test work group connection interface and the second joint test work group connection interface are mutually conductive, and the test circuit boards are provided to each other. Through the first joint test work group connection interface and the second joint test For a group connection interface connected with each other.

The test circuit board and self-detection method disclosed in the present invention are as above, and the difference from the prior art is that the present invention performs self-test by jointly testing the work group wafer for detecting the circuit board to be tested and self-testing the test circuit board. When passing, the first joint test work group connection interface and the second joint test work group connection interface are turned on through the controller, the data multiplexer, and the switch chip to connect the test circuit boards in series.

Through the above technical means, the present invention can achieve the technical effect of providing convenient and quick solution to the self-fault detection of the tandem joint test work group wafer.

The embodiments of the present invention will be described in detail below with reference to the drawings and embodiments, so that the application of the technical means to solve the technical problems and achieve the technical effects can be fully understood and implemented.

The test circuit board with self-test function and the self-test method thereof disclosed in the present invention are described below, and please refer to "1st picture", "2nd picture", and "3A picture" to "3C picture". FIG. 1 is a block diagram of a test circuit board having a self-test function according to the present invention; FIG. 2 is a circuit diagram showing a test circuit board having a self-test function according to the present invention; FIG. 3C is a flow chart showing the self-detection method of the self-test function test circuit board of the present invention.

The self-detecting test circuit board 10 disclosed in the present invention comprises: a first joint test work group (Joint Test Action Group) connection interface 11, a joint test work group chip 12, a controller 13, and data multiplexing. a multiplexer (MUX) 14, a switch chip 15, a buffer 16, a second joint test work group connection interface 17, and a test connection interface 18 (step 101), wherein the first joint test work group is connected The interface 11 includes a first test clock (TCK) pin 111, a first test mode select (TMS) pin 112, a first test data input (TDI) pin 113, and a first A test data output (TDO) pin 114 (step 102); a second joint test work group connection interface 17 includes a second test clock pin 171, a second test mode select pin 172, a second test The data input pin 173 and the second test data output pin 174 (step 103).

The first joint test work group connection interface 11 is used to electrically connect with the joint test work group controller 20 or other test circuit boards 10 (step 104), and the second joint test work group connection interface 17 is used. In order to electrically connect with other test circuit boards 10, the test circuit boards 10 are formed in series with each other.

Specifically, the first joint test work group connection interface 11 of the first test circuit board is electrically connected to the joint test work group controller 20, and the second joint test work group connection interface 17 of the first test circuit board is The first joint test work group connection interface 11 of the second test circuit board is electrically connected, and the second joint test work group connection interface 17 of the second test circuit board and the first joint test work group of the third test circuit board The connection interface 11 is electrically connected, and so on, thereby causing the test circuit boards 10 to form a series connection with each other.

The joint test work group chip 12 is electrically connected to the first test clock pin 111, the first test mode select pin 112, and the first test data input pin 113 (step 105), and the joint test work group controller 20 controls The joint test workgroup wafer 12 is for self-testing of the test circuit board 10 (step 113), and generating a communication signal when the joint test workgroup wafer 12 passes the self-test of the test circuit board 10 (step 114).

The controller 13 is electrically connected to the joint test work group chip 12 (step 106). The joint test work group chip 12 and the controller 13 perform signal communication by using a custom communication protocol, and the above custom communication protocol includes using 8 requests. Request data pin, 8 response data pin, load command (Load_cmd) pin, update (Update) pin, busy setting (Busy_N) pin, please refer to "Figure 4" 4, FIG. 4 is a schematic diagram showing a communication protocol between a controller of a test circuit board having a self-test function and a joint test work group, and the controller 13 can receive a communication signal from the joint test work group chip 12. Generate a selection signal (Select, SEL).

It should be noted that the following is a communication process of the joint test work group chip 12 and the controller 13 custom communication protocol, the joint test work group chip 12 and the controller 13 are at the load command pin low (low) When the request data pin is active, when the update pin is high, the controller 13 reads the request data pin and sets the busy set pin to be valid (ie, busy). When the test work group wafer 12 checks that the busy set pin is valid (ie, the controller 13 receives the command successfully), the joint test work group chip 12 sets the update pin to a low level and sets the load command pin to a high level. Potential, after the controller 13 performs the corresponding operation, the controller 13 sets the response data pin, and then sets the busy setting pin to be invalid (indicating that the controller 13 has completed the instruction, the controller 13 is in an idle state) for The joint test work group wafer 12 is read.

The data multiplexer 14 is electrically connected to the data output pin of the joint test work group chip 12 and the controller 13. In the preset setting, the first test data output pin 114 is transmitted through the data multiplexer 14 and the joint test. The data output pin of the work group chip 12 is electrically connected (step 107), and the switch chip 15 is electrically connected to the first test data output pin 114, the controller 13, and the data multiplexer 14 (step 108), and temporarily stored. The first test clock pin 111 is electrically connected to the first test mode select pin 112 and the second test mode pin 171 and the second test mode select pin 172 (step 109, step 110), the register 16 is used to provide signal strength enhancement and signal interference resistance of the first test clock pin 111 and the signal between the first test mode select pin 112 and the second test clock pin 171 and the second test mode select pin 172. The signal reflection effects of other test boards 10 are further prevented.

The second test data input pin 113 is electrically connected to the data multiplexer 14, and the second test data output pin 114 is electrically connected to the switch chip 15 (step 110), when the joint test work group wafer 12 passes the test circuit board. When the self-test 10 generates a communication signal, the controller receives the communication signal from the joint test work group chip 12 to generate a selection signal (step 115), and the data multiplexer 14 obtains the selection signal from the controller 13, and the data multiplexer 14 The electrical connection between the first test data output pin and the data output pin of the joint test work group chip may be interrupted according to the selection signal, and the second test data input pin 173 and the data output of the joint test work group chip 12 are turned on. a pin position, and when the switch chip 15 obtains the selection signal from the controller 13, the switch chip 15 can selectively turn on the first test data output pin 114 and the second test data output pin 174 according to the selection signal to enable the first joint test. The work group connection interface 11 and the second joint test work group connection interface 17 are electrically connected to each other, and provide the test circuit board 10 through the first connection Testing group connection interface 11 and the second joint testing group connection interface 17 connected with each other (step 116).

The joint test work group controller 20 controls the joint test work group wafer 12 to detect the test circuit board or self-test the test circuit board 10 through a Boundary Scan technology. The joint test work group The controller 20 first scans the identity identification code (IDCODE) of the joint test work group chip, and determines whether the identity identifiers of the chips read into the joint test work group are consistent, and then pushes the boundary scan samples and the large amount of data through the boundary scan technology. And determine whether the output results are consistent, and detect the stability of the Boundary Scan Chain of the joint test work group to self-test the test circuit board.

The test connection interface 18 is electrically connected to the circuit board to be tested and the joint test work group chip 12 respectively (step 111), and the test connection interface 18 is electrically connected to the circuit board to be tested through the plug connection mode, and the joint test work group control The device 20 can control the joint test workgroup wafer 12 to detect the test circuit board (step 112).

In summary, it can be seen that the difference between the present invention and the prior art is that the present invention passes the joint test work group wafer to perform detection of the circuit board to be tested and self-test of the test circuit board, and when the self-test passes, A joint test workgroup connection interface and a second joint test workgroup connection interface are conducted through the controller, the data multiplexer, and the switch wafer to connect the test circuit board in series.

The prior art technology can solve the problem of inconvenient and time-consuming fault detection of the existing tandem joint test work group wafer method, thereby achieving convenient and quick solution to the serial joint test group wafer self-fault detection. Technical efficacy.

While the embodiments of the present invention have been described above, the above description is not intended to limit the scope of the invention. Any changes in the form and details of the embodiments may be made without departing from the spirit and scope of the invention. The scope of the invention is to be determined by the scope of the appended claims.

10‧‧‧Test circuit board

11‧‧‧First Joint Test Workgroup Connection Interface

111‧‧‧First test clock pin

112‧‧‧First test mode selection pin

113‧‧‧First test data input pin

114‧‧‧First test data output pin

12‧‧‧Joint Test Workgroup Wafer

13‧‧‧ Controller

14‧‧‧Data multiplexer

15‧‧‧Switch wafer

16‧‧‧Scratch

17‧‧‧Second joint test workgroup connection interface

171‧‧‧Second test clock pin

172‧‧‧Second test mode selection pin

173‧‧‧Second test data input pin

174‧‧‧Second test data output pin

18‧‧‧Test connection interface

20‧‧‧Joint Test Workgroup Controller

Step 101‧‧‧ provides a first joint test workgroup connection interface, a joint test workgroup chip, a controller, a data multiplexer, a switch chip, a scratchpad, a second joint test workgroup connection interface, and Test the test board of the connection interface

Step 102‧‧‧ The first joint test work group connection interface includes a first test clock pin, a first test mode select pin, a first test data input pin, and a first test data output pin

Step 103‧‧‧ The second joint test work group connection interface includes a second test clock pin, a second test mode select pin, a second test data input pin, and a second test data output pin

Step 104‧‧‧ First joint test work group connection interface and joint test work group controller or other test circuit board second joint test work group connection interface electrical connection

Step 105‧‧‧ Joint test work group chip is electrically connected to the first test clock pin, the first test mode selection pin and the first test data input pin

Step 106‧‧‧The controller and the joint test work group chip are electrically connected

Step 107‧‧‧ The data multiplexer and the joint test work group chip data output pin and the controller are electrically connected. In the preset setting, the first test data output pin will pass the data multiplexer and the joint test Workout chip data output pin electrical connection

Step 108‧‧‧ Switch chip is electrically connected to the first test data output pin, controller, and data multiplexer

Step 109‧‧‧ The register is electrically connected to the first test clock pin and the first test mode select pin

Step 110‧‧‧ The second test clock pin and the second test mode selection pin are electrically connected to the temporary register, the second test data input pin is electrically connected to the data multiplexer, and the second test data output pin is connected Electrically connected to the switch chip

Step 111‧‧‧ Test connection interface is electrically connected to the joint test work group chip and the circuit board to be tested

Step 112‧‧‧Joint Test Workgroup Controller Controls the Joint Test Workgroup Wafer to pass the test connection interface to test the test board

Step 113‧‧‧Joint Test Workgroup Controller Controls Joint Test Workgroup Wafer for Self-Test of Test Board

Step 114‧‧‧Communication signals are generated when the joint test workgroup chip passes the self-test of the test board

Step 115‧‧‧The controller receives the communication signal from the joint test workgroup chip to generate the selection signal

Step 116‧‧‧ The data multiplexer interrupts the electrical connection between the first test data output pin and the data output pin of the joint test work group chip according to the selection signal, and turns on the second test data input pin and the joint test work The data output pin of the group chip, the switch chip turns on the first test data output pin and the second test data output pin according to the selection signal, so that the first joint test work group connection interface and the second joint test work group The connection interfaces are electrically connected to each other, and the test circuit boards are connected to each other through the first joint test work group connection interface and the second joint test work group connection interface

FIG. 1 is a block diagram of a test circuit board with self-detection function according to the present invention. FIG. 2 is a schematic circuit diagram of a test circuit board with self-detection function according to the present invention. 3A to 3C are flow charts showing a self-detection method of the self-detection function test circuit board of the present invention. FIG. 4 is a schematic diagram showing the communication protocol between the controller of the test circuit board with self-detection function and the joint test work group.

Claims (10)

A test circuit board with self-detection function, comprising: a first Joint Test Action Group connection interface for cooperating with a joint test work group controller or other said test circuit board The first joint test work group connection interface includes a first test clock (TCK) pin, a first test mode select (TMS) pin, and a first test data. a Test Data Input (TDI) pin and a first Test Data Output (TDO) pin; a joint test work group chip, the joint test work group chip and the first test clock a pin, the first test mode selection pin, and the first test data input pin are electrically connected, and the joint test work group controller controls the joint test work group chip to perform the test circuit board Self-detecting, and generating a communication signal when the joint test work group wafer passes the self-test of the test circuit board; a controller, the control Electrically connecting with the joint test work group chip; a data multiplexer (MUX), the data multiplexer and the data output pin of the joint test work group chip and the controller a first connection, the first test data output pin is electrically connected to the data output pin of the joint test work group chip through the data multiplexer; The switch chip is electrically connected to the first test data output pin, the controller, and the data multiplexer; a buffer, the register and the first test clock pin And the first test mode selection pin electrical connection; and a second joint test work group connection interface for connecting the interface electrical properties with the first joint test work group of the other test circuit boards Connected, the second joint test work group connection interface includes a second test clock pin, a second test mode select pin, a second test data input pin, and a second test data output pin. The second test clock pin and the second test mode select pin are electrically connected to the register, and the second test data input pin is electrically connected to the data multiplexer, The test data output pin is electrically connected to the switch chip; and a test connection interface, the test connection interface is electrically connected to the joint test work group chip and the circuit board to be tested respectively, and the joint test work The group chip is detected by the test connection interface to be tested by the test circuit board; wherein, when the joint test work group chip generates the communication signal, the controller receives from the joint test work group wafer The communication signal generates a selection signal (Select, SEL), and the data multiplexer interrupts the first test data output pin and the data output pin of the joint test work group chip according to the selection signal Electrically connecting, and conducting the second test data input pin and the data output pin of the joint test work group chip, the switch chip according to the Selecting a signal to turn on the first test data output pin and the second test data output pin, so that the first joint test work group connection interface and the second joint test work group connection interface are mutually conductive And providing the test circuit boards in series with each other through the first joint test work group connection interface and the second joint test work group connection interface. The test circuit board with self-detection function as described in claim 1, wherein the joint test work group controller controls the joint test work group wafer to be tested by Boundary Scan technology. The board performs a test or self-tests the test board. The test circuit board with self-detection function according to claim 2, wherein the joint test work group controller scans the identity identification code (IDCODE) of the joint test work group chip to detect the joint test work group. The stability of the Boundary Scan Chain. The test circuit board with self-detection function according to claim 3, wherein the joint test work group controller will return to the boundary scan chain of the joint test work group wafer, and read the joint test work. The identity identification code of the group wafer is judged whether it is consistent, and the boundary scan technology is used to push the boundary scan sample and a large amount of data to determine whether the output result is consistent, so as to self-detect the test circuit board. The test circuit board with self-detection function according to claim 1, wherein the register is configured to provide the first test clock pin and the first test mode selection pin and the second The signal strength enhancement of the signal between the test clock pin and the second test mode selection pin and the signal interference resistance further prevent signal reflection effects of other test boards. A self-detection method with a self-test function test circuit board, comprising the following steps: providing a first joint test work group (Joint Test Action Group) connection interface, a joint test work group chip, a controller, and a a data multiplexer (MUX), a switch chip, a buffer (Buffer), a second joint test work group connection interface, and a test circuit board for testing the connection interface; the first joint test work The group connection interface includes a first test clock (TCK) pin, a first test mode select (TMS) pin, and a first test data input (TDI) pin. And a first test data output (TDO) pin; the second joint test work group connection interface includes a second test clock pin, a second test mode select pin, and a second test a data input pin and a second test data output pin; the first joint test work group connection interface and the joint test work group control Or the second joint test work group connection interface of the other test circuit board is electrically connected; the joint test work group chip and the first test clock pin, the first test mode selection The pin and the first test data input pin are electrically connected; the controller is electrically connected to the joint test work group chip; and the data multiplexer and the joint test work group chip data The output pin and the controller are electrically connected. In a preset setting, the first test data output pin is electrically transmitted through the data multiplexer and the data output pin of the joint test work group chip. The switch chip is electrically connected to the first test data output pin, the controller, and the data multiplexer; the register and the first test clock pin and the The first test mode selects a pin electrical connection; the second test clock pin and the second test mode select pin are electrically connected to the register, and the second test data input pin and the ground More data Electrically connecting, the second test data output pin is electrically connected to the switch chip; the test connection interface is electrically connected to the joint test work group chip and the circuit board to be tested respectively; a workgroup controller controlling the joint test workgroup wafer to detect the test circuit board through the test connection interface; a joint test workgroup controller controlling the joint test workgroup wafer to perform the Testing the self-test of the circuit board; generating a communication signal when the joint test work group wafer passes the self-test of the test circuit board; the controller receives the communication signal from the joint test work group chip Generating a selection signal (Select, SEL); and the data multiplexer turns on the first test data input pin and the second test data input pin according to the selection signal, the switch chip according to the Selecting a signal to interrupt the electrical connection between the first test data output pin and the data output pin of the joint test work group chip And turning on the second test data output pin and the data output pin of the joint test work group chip, so that the first joint test work group connection interface and the second joint test work group The connection interfaces are electrically connected to each other, and the test circuit boards are provided in series with each other through the first joint test work group connection interface and the second joint test work group connection interface. The self-detection method with a self-test function test circuit board according to claim 6, wherein the joint test work group controller controls the joint test work group chip through a Boundary Scan technology. The test connection interface is tested through the test connection interface and self-testing of the test circuit board is performed. The self-detection method with a self-test function test circuit board according to claim 7, wherein the joint test work group controller scans an identity identification code (IDCODE) of the joint test work group chip to detect Joint test work group Boundary Scan Chain stability. The self-detection method with a self-test function test circuit board according to claim 8, wherein the joint test work group controller will return to the boundary scan chain of the joint test work group wafer, and read the The test identity of the work group chip is jointly tested and judged to be consistent. The boundary scan technology is used to push the boundary scan sample and a large amount of data to determine whether the output result is consistent, so as to self-test the test circuit board. The self-detection method with a self-test function test circuit board according to claim 6, wherein the register is configured to provide the first test clock pin and the first test mode selection pin and the The signal strength enhancement of the signal between the second test clock pin and the second test mode selection pin and the signal interference resistance further prevent signal reflection effects of other test boards.