TWI736721B - Pin connection testing system for connector and method thereof - Google Patents

Abstract

A pin connection testing system for connector and method thereof is disclosed. By transmitting a joint test action group (JTAG) command to a programmable logic device (PLD) for controlling, so as to drive at least one demultiplexer transmits an under test signal from a connector to a first line or a second line, and conversing and encoding the under test signal to transmit to a set of input/output pins of the PLD for reading when transmitting the first line, and reading a state of the set of input/output pins electrically connected to the second line when transmitting the second line. Then, generates a test result according to the under test signal and the state of the input/output pins. The mechanism is help to improve the testing convenience of the connection status of the connector.

Description

Pin connection test system and method of connector

The present invention relates to a test system and a method thereof, in particular in a Boundary Scan (Boundary Scan) test environment, it is more capable of interconnecting signals other than Input/Output (I/O) signals, such as: pull-up The signal, pull-down signal, power signal, and ground signal are connected to the pin of the connector to test the system and its method.

In recent years, with the popularization and vigorous development of electronic circuits, how to quickly and correctly test the connection state of the connector has become one of the problems that various manufacturers urgently want to solve.

Generally speaking, the connection status includes open circuit (Open) and short circuit (Short). The purpose of the test is to confirm whether all the connector pins (or pin positions) are correctly connected, and to confirm that no pins are connected with Other pins are short-circuited, or are short-circuited with power (Power), ground (Ground, GND) and other pins. Traditionally, the test method is that the probes of the three-meter electric meter touch the two end points of the circuit to be tested and apply a current. If it can be turned on, it is regarded as a short circuit, otherwise, it is regarded as an open circuit. However, this method is difficult to test on a complicated circuit, so it has the problem of inconvenience to test the connection state of the connector.

In view of this, some manufacturers have proposed boundary scan technology to connect the input and output pins of programmable logic components to the connector in order to test the connection status of the input and output interconnection signals. However, this method cannot be used for non-simple Input and output interconnection signals, such as: pull-up signal, pull-down signal, power signal and ground signal, etc. for testing. Therefore, the problem of the inconvenience of the connection state of the test connector still cannot be effectively solved.

In summary, it can be seen that the prior art has always had the problem of inconvenience in testing the connection state of the connector. Therefore, it is necessary to propose improved technical means to solve this problem.

The invention discloses a pin connection test system and method of a connector.

First, the present invention discloses a pin connection test system of a connector, which is applied in a boundary scan test environment. The system includes a unit to be tested and a test unit. The unit under test has a connector, and the connector includes a plurality of connection pins, and each connection pin has a corresponding signal to be tested.

Then, the test unit includes: a demultiplexer, an analog-to-digital converter, a microcontroller, and a programmable logic element. Wherein, each demultiplexer is electrically connected to the connector to select the signal to be tested from the connector to be transmitted to the first line or the second line; each analog-to-digital converter has a set of analog input pins. The first line is electrically connected to convert the signal to be measured into a corresponding digital voltage value; the microcontroller is electrically connected to an analog-to-digital converter to convert the code of the digital voltage value into an N-bit output, where N is a positive integer ; Programmable logic element has a set of input and output pins, of which, K pins are electrically connected to the demultiplexer to control the demultiplexer to select the first line or the second line, and the M pins are electrically connected The second circuit reads the state of each signal under test, and is electrically connected to the microcontroller through N pins to read the N-bit digital voltage value. When the signal under test is an input/output interconnection signal, execute The boundary scan interconnection test detects the status of each signal under test and generates a connection message. When the signal under test is a power signal or a pull-up signal, the demultiplexer is controlled to select the first line and read the digits from the microcontroller Voltage value. When the read digital voltage value is zero, the first open circuit message is generated. When the signal to be measured is a ground signal or a pull-down signal, the demultiplexer is controlled to select the second line and perform boundary scan reading Corresponding to the potential state of the signal to be measured, when the potential state is not a low potential, a second open circuit message is generated, where K and M are positive integers.

In addition, the present invention discloses a connector pin connection test method, which is applied in a boundary scan test environment. The steps include: providing a unit to be tested, the unit to be tested has a connector, and the connector includes a plurality of connection pins, Each connection pin has a corresponding signal to be tested; a test unit is provided, which is electrically connected to the unit to be tested through a connector to receive the signal to be tested; when the signal to be tested is an input/output interconnection signal , Perform a boundary scan interconnection test to detect the state of each signal to be tested and generate a connection message; when the signal to be tested is a power signal or a pull-up signal, the test unit transmits the signal to be tested to the first line for The test signal is converted into a digital voltage value. When the digital voltage value is zero, the first open circuit message is generated; when the test signal is a ground signal or a pull-down signal, the test unit transmits the test signal to the second circuit for execution The boundary scan reads the potential state corresponding to the signal to be measured, and when the potential state is not a low potential, a second open circuit message is generated.

The system and method disclosed in the present invention are as above. The difference from the prior art is that the present invention uses JTAG commands to control programmable logic elements so as to drive the demultiplexer to transmit the signal under test from the connector to the first line or the second line. When the signal is transmitted to the first circuit, the signal to be measured is converted and coded by analog to digital, and then transmitted to the input and output pins of the programmable logic element for reading. When transmitted to the second circuit, the reading and the first The state of the input and output pins that are electrically connected to the two lines, and then generate corresponding test results according to the signal to be tested and the read input and output pins.

Through the above-mentioned technical means, the present invention can achieve the technical effect of improving the convenience of testing the connection state of the connector pins.

The following describes the implementation of the present invention in detail with the drawings and embodiments, so as to fully understand and implement the implementation process of how the present invention uses technical means to solve technical problems and achieve technical effects.

Before describing the pin connection test system and method of the connector disclosed in the present invention, the environment in which the present invention is applied will be described. The connector pins on the test unit are judged whether there are errors such as open circuit, short circuit with the ground wire, short circuit between the pins. Among them, the unit under test and the test unit are electrically connected to each other through the connector, and through the joint test group Group (Joint Test Action Group, JTAG) instructions control the programmable logic components of the test unit, which are used to set and read its input and output pins.

The following diagrams are used to further explain the pin connection test system and method of the connector of the present invention. Please refer to "Figure 1" first. "Figure 1" is a system block diagram of the pin connection test system of the connector of the present invention. , Applied in a boundary scan test environment, this system includes: a unit under test 110 and a test unit 120. The unit under test 110 has a connector 111, and the connector 111 includes a plurality of connection pins, and each connection pin has a corresponding signal to be tested. In actual implementation, the signal to be tested can be generated by a JTAG device, a central processing unit, etc., provided on the unit under test 110. In addition, the connector 111 may be various slots, such as: Peripheral Component Interconnect (PCI), PCIe (PCI Express), dual in-line memory module (Dual In-line Memory Module, DIMM), Small Outline Dual In-line Memory Module (SODIMM), etc.

As for the part of the test unit 120, it includes a demultiplexer 121 (Demultiplexer, DEMUX), an analog-to-digital converter 122, a microcontroller 123, and a programmable logic element 124. Wherein, the demultiplexer 121 is electrically connected to the connector 111 to select the signal to be tested from the connector 111 to be transmitted to the first line 151 or the second line 152. In actual implementation, you can choose an electronic component of the model such as "74CBTLV3257" as the demultiplexer 121. In addition, in fact, there is a channel selection signal line between the demultiplexer 121 and the programmable logic component 124 (not shown in the figure). Show), one end of this channel selection signal line is electrically connected to the input and output pins of the programmable logic element 124, and the other end is electrically connected to the selection pin of the demultiplexer 121. Take the electronic element of "74CBTLV3257" as an example. : "Pin 1". The programmable logic element 124 controls the demultiplexer 121 to transmit the signal under test to the first line 151 or the second line 152 through the channel selection signal line. It should be added that the difference between a demultiplexer and a multiplexer (MUX) is only in the direction of data flow. The former is one input to multiple output; the latter is multiple input to one input.

The analog to digital converter 122 (Analog to Digital Converter, ADC) has a set of analog input pins electrically connected to the first circuit 151 for converting the signal to be measured into a corresponding digital voltage value. Simply put, the analog-to-digital converter 122 is an element for converting a continuous signal in an analog form into a discrete signal in a digital form.

The microcontroller 123 is electrically connected to the analog-to-digital converter 122 for converting the digital voltage value code into N bits to output to the programmable logic element 124, where N is a positive integer. In actual implementation, assuming that it is converted to 8 bits, it means that N is equal to 8, and eight wires need to be electrically connected between the microcontroller 123 and the programmable logic element 124 to transmit the 8-bit digital voltage value. In other words, these eight wires are electrically connected to the input and output pins of the programmable logic element 124.

The programmable logic element 124 has a set of input and output pins, wherein the demultiplexer 121 is electrically connected to the demultiplexer 121 through K pins to control the demultiplexer 121 to select the first line 151 or the second line 152, and through M pins The second circuit 152 is electrically connected to read the state of each signal to be tested, and the microcontroller 123 is electrically connected to the microcontroller 123 through N pins to read the N-bit digital voltage value. Among them, the above-mentioned K and M All are positive integers. When the signal to be tested is an input/output interconnection signal, a boundary scan interconnection test is performed to detect the state of each signal to be tested and generate a connection message. For example, the potential of each signal to be tested is recorded in the connection message, record Whether each signal under test has short circuit, open circuit, etc. Then, when the signal to be measured is a power signal or a pull-up signal, the demultiplexer 121 is controlled to select the first line 151, and the digital voltage value is read from the microcontroller 123, when the read digital voltage value is zero At the time, the first open circuit message is generated. For example, the first open circuit message may be a message that records the text "The power signal or the pull-up signal is in an open circuit state." Next, when the signal to be measured is a ground signal or a pull-down signal, the demultiplexer 121 is controlled to select the second line 152, and the boundary scan is performed to read the potential state corresponding to the signal to be measured. When the potential is not low, a second open-circuit message is generated. For example, the second open-circuit message is a message in which the text "ground signal or pull-down signal is in an open state" is recorded. In actual implementation, the programmable logic element 124 can control the demultiplexer 121 to switch from the first line 151 to the second line after the signal to be tested is a pull-up signal and the read digital voltage value is not zero. 152, and perform a boundary scan interconnection test to read the state of each signal to be tested according to the M pins, so as to detect whether there is a short circuit between the connecting pins of the connector 111. In addition, the programmable logic element 124 can also perform a boundary scan interconnection test after the signal to be tested is a pull-down signal and the read potential state is not a high potential to read each pin based on the M pins. The state of the signal to be tested is used to detect whether there is a short circuit between the connecting pins of the connector 111. In a specific implementation, the programmable logic element 124 may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), and so on.

Then, please refer to "Figure 2A" and "Figure 2B", "Figure 2A" and "Figure 2B" are the method flowcharts of the pin connection test method of the connector of the present invention, which is applied in the boundary scan test environment Next, the steps include: providing a unit under test 110, the unit under test 110 has a connector 111, the connector 111 includes a plurality of connection pins, and each connection pin has a corresponding signal to be tested (step 210); A test unit 120 is provided, and the test unit 120 is electrically connected to the unit under test 110 through the connector 111 to receive the signal under test (step 220); the test unit 120 executes the boundary when the signal under test is an input/output interconnection signal Scan the interconnection test to detect the state of each signal under test and generate a connection message (step 230); when the signal under test is a power signal or a pull-up signal, the test unit 120 transmits the signal under test to the first line 151, and uses To convert the signal to be tested into a digital voltage value, when the digital voltage value is zero, a first open circuit message is generated (step 240); when the signal to be tested is a ground signal or a pull-down signal, the test unit 120 transmits the signal to be tested The second line 152 is used to perform boundary scan to read the potential state corresponding to the signal to be measured. When the potential state is not a low potential, a second open circuit message is generated (step 250). Through the above steps, the programmable logic element 124 can be controlled through JTAG commands to drive the demultiplexer 121 to transmit the signal to be tested from the connector 111 to the first line 151 or the second line 152, and then to the first line At 151, the signal to be tested is converted and coded by analog to digital, and then sent to the input and output pins of the programmable logic element 124 for reading. When sent to the second line 152, the reading is electrically connected to the second line 152. The status of the connected input and output pins, and then the corresponding test results are generated according to the signal to be tested and the read input and output pins.

In addition, after step 240, the test unit 120 can switch and transmit the signal to be tested from the first line 151 to the second line 152 after the signal to be tested is a pull-up signal and the read digital voltage value is not zero. , And perform a boundary scan interconnection test to read the state of each signal to be tested to detect whether there is a short circuit between the connection pins (step 241); and after step 250, the test unit 120 can determine whether the signal to be tested is After the signal is pulled down and the read potential state is not high, a boundary scan interconnection test is performed to read the state of each signal to be tested to detect whether there is a short circuit between the connection pins (step 251). It should be added that, in actual implementation, the unit under test 110 and the test unit 120 have JTAG interfaces for receiving JTAG commands from the terminal, so that the terminal can control the test unit 120 according to the JTAG commands, and read through The state of the signal to be measured transmitted by the second line 152 is, for example, a high potential (High) or a low potential (Low).

The following description will be given in the form of embodiment in conjunction with "Figure 3" and "Figure 4". Please refer to "Figure 3" first. "Figure 3" is a schematic diagram of applying the present invention to control programmable logic components with JTAG instructions. . In actual implementation, when the boundary scan interconnection test is performed, the input and output pins (I/O pins) of the programmable logic element 124 are controlled through JTAG instructions to capture the value of each pin and output it with the unit under test 110 Compare the value of, if the two are the same, it means that no short circuit, open circuit, etc. have occurred. The following describes the processes where the signals to be tested are "input/output interconnection signal", "power signal", "pull-up signal", "pull-down signal" and "ground signal":

1. "Input and output interconnection signals"

1. Assuming that the demultiplexer 121 of the test unit 120 is electrically connected to the JTAG device 310 via the connector 111, when the pin connection status is to be tested according to the signal under test sent by the JTAG device 310, the signal under test mentioned here The type is the input and output interconnection signal.

2. The terminal 300 uses JTAG commands to control the programmable logic element 124, for example: according to the boundary scan description language (Boundary Scan Description Language, BSDL) to send the "Extest" command (such as: "11010101"), so that the programmable logic element 124 enters Boundary scan mode.

3. The terminal 300 uses JTAG commands to send data to the boundary scan register (Register) of the programmable logic element 124. By default, the data sent are all "1", and all "1" means that all output and input pins are Input mode. In actual implementation, each input and output pin of the programmable logic element 124 has a corresponding element (Cell) in the boundary scan register. The input and output pins can be set to input mode, output mode, and set output The value of (for example: "0" or "1"). Therefore, by controlling the boundary scan register of the programmable logic element 124, the input and output pin mode of the programmable logic element 124 can be set. When the input mode is set, the boundary scan register will record the external input The value of the output pin, (for example: "0" or "1").

4. Switch the demultiplexer 121 to the second line 152. The second line 152 is electrically connected to the K pins of the input and output pins of the programmable logic element 124. As a result, the JTAG device 310 sends out the waiting The test signal can be transmitted to the input and output pins of the programmable logic element 124.

5. Then, the terminal 300 can read the components (Cell) corresponding to the K pins in the boundary scan register through the JTAG interface 301, that is, grab the corresponding value from it, for example: "0" or "1" , Used to compare whether the signal to be tested and the captured value are the same. If the same means that the test passes, otherwise it means that there is a fault, and the corresponding connection message is generated according to the comparison result, for example: record the signal to be tested and all captured To the value.

2. "Power signal" or "pull up signal"

1. Assuming that the demultiplexer 121 of the test unit 120 is electrically connected to the power supply (for example: 3.3V) of the unit under test 110, it means that the signal under test is the power signal; if it is electrically connected to the pull-up signal, it represents the signal under test. It is a pull-up signal.

2. The terminal 300 uses JTAG commands to control the programmable logic element 124, and sends the "Extest" command according to the boundary scan description language to make the programmable logic element 124 enter the boundary scan mode.

3. The terminal 300 uses the JTAG command to send data to the boundary scan register of the programmable logic element 124, which is used to connect to the programmable logic element 124 of the demultiplexer 121 (ie: the input and output pins). K pins) set corresponding values to switch the demultiplexer 121 to the first line 151.

4. Use the 8 input and output pins on the programmable logic element 124 as the instruction code, and send the instruction code to the microcontroller 123. For example, suppose you want to request to read the 5th pin of the analog-to-digital converter 122 Bit (AD pin) value, then the value of the 8 input and output pins can be set to "00000101", which means that you want to read the code of the fifth pin.

5. The microcontroller 123 uses Inter-Integrated Circuit (IIC) to control the analog-to-digital converter 122 to read the digital voltage value from the analog-to-digital converter 122 and save it, and to convert the digital voltage value to 8-bit code to output this code to the 8 input and output pins of the programmable logic element 124. For example, the code is "00000000" for 0V; the code is "11111111" for 3.3V; the code is "10000000" "Means 1.67V and so on.

6. Finally, the terminal 300 uses the JTAG interface 301 to send a JTAG command to read the value of the boundary scan register to extract the 8-bit code returned by the microcontroller 123 to confirm whether the voltage is normal. 0V represents an open circuit, and the corresponding first open circuit message is generated, such as: "Power signal is open circuit state" or "Pull-up signal is open circuit state" in text.

3. "Pull-down signal" or "ground signal"

1. Assuming that the demultiplexer 121 of the test unit 120 is electrically connected to the ground of the unit under test 110, it represents that the signal under test is a ground signal; if it is electrically connected to the pull-down signal, it represents that the signal under test is a pull-down signal.

2. The terminal 300 uses JTAG commands to control the programmable logic element 124, and sends the "Extest" command according to the boundary scan description language to make the programmable logic element 124 enter the boundary scan mode.

3. The terminal 300 uses the JTAG command to send data to the boundary scan register of the programmable logic element 124. By default, the data sent are all "1" to set the output and input pins in the input mode.

4. Switch the demultiplexer 121 to the second line 152. The second line 152 is electrically connected to the K pins of the input and output pins of the programmable logic element 124. In this way, the signal to be tested can be transmitted To the input and output pins of the programmable logic element 124.

5. Then, the terminal 300 can read the potential status of the K pins in the boundary scan register through the JTAG interface 301, for example: "0" (Low) or "1" (High), assuming the potential is read The state is not low, that is, "0" (Low), and the corresponding second open-circuit message is generated, for example: "Ground signal is open circuit state" or "Pull-down signal is open circuit state" in text.

In particular, assuming that the received signal to be measured is a pull-up signal and the read digital voltage value is not zero, the signal to be measured can be switched from the first line 151 to the second line 152, and Perform a boundary scan interconnection test to read the status of each signal under test to detect whether there is a short circuit between the connection pins of the connector 111; assume that the received signal under test is a pull-down signal and the read potential status After it is not at a high potential, a boundary scan interconnection test can be performed to read the state of each signal under test to detect whether there is a short circuit between the connection pins of the connector 111.

In actual implementation, the first line 151 is electrically connected to one end of the pull-down resistor 320, and the other end of the pull-down resistor 320 is grounded, and the resistance value of the pull-down resistor 320 is at least 1M ohm. In this way, when the power signal or the pull-up signal has an open circuit, the presence of the pull-down resistor 320 will make the digital voltage value converted by the analog-to-digital converter 122 a value of zero, so it can be used as a judgment for whether the power signal or the pull-up signal is open. in accordance with. In addition, the terminal 130 is a computer device, such as a personal computer, a notebook computer, a wearable device, a smart phone, etc., which can transmit JTAG commands through the JTAG interface 301 to control the programmable logic element 124 and read The input and output pins of the programmable logic element 124, such as General-Purpose Input/Output (GPIO). The terminal 300 can also be directly designated by the user or perform circuit analysis to determine whether the received signal to be tested is an input/output interconnection signal, a power signal, a pull-up signal, a ground signal, or a pull-down signal, and the corresponding signal is generated according to the determination result. The JTAG command is sent to the JTAG interface 301 to control the programmable logic element 124 of the test unit 120 and read the input and output pins of the programmable logic element 124.

As shown in "Fig. 4", "Fig. 4" is a schematic diagram of testing memory sockets using the present invention. Assume that the connector is a 240-pin memory socket 420, which is electrically connected to the central processing unit 410, the ground wire, the power wire, and the like. In this example, since the connector has 240 pins/pins, it means that there are 240 signals to be tested. Therefore, the boundary scan I/O expansion connector 430 of the test unit 120 also needs 240 pins in order to pass through the row. The cable or adapter card is electrically connected to the 240 pin memory slot 420. Next, the boundary scan I/O expansion connector 430 is also electrically connected to a plurality of demultiplexers 121 through 240 wires. Take the demultiplexer IC 401 of model "74CBTLV3257" as an example, because it provides four sets of demultiplexers. Multiplexer 121, so 60 demultiplexer ICs 401 can be used as input terminals corresponding to these 240 wires. In addition, these 60 demultiplexer ICs 401 and programmable logic components 124 and analog-to-digital conversion Between the ICs 402, as shown in "Figure 4", there are also 240 wires used to transmit the signal under test, which are used as the output terminals of the demultiplexer IC 401. In actual implementation, take the analog-to-digital conversion IC 402 of the model "MAX1038" as an example. It has 10 sets of analog-to-digital converters 122 inside, so 24 analog-to-digital conversion ICs 402 can be used for all demultiplexer ICs 401. 240 wires are used for analog-to-digital conversion. In this way, it can be based on the type of signal to be tested, such as: "input and output interconnection signal", "power signal", "pull-up signal", "pull-down signal" and "ground signal", etc., as in the above "No. 3 The description of "Figure" executes the corresponding process.

In summary, it can be seen that the difference between the present invention and the prior art is that the programmable logic element 124 is controlled through JTAG instructions so as to drive the demultiplexer 121 to transmit the signal under test from the connector 111 to the first line 151 or The second line 152, when transmitted to the first line 151, performs analog-to-digital conversion and coding of the signal to be tested, and then transmits it to the input and output pins of the programmable logic element 124 for reading. When it is transmitted to the second line 152 , Read the state of the input and output pins that are electrically connected to the second line 152, and then generate corresponding test results based on the signal to be tested and the read input and output pins. This technical means can solve the prior art The existing problems, and then achieve the technical effect of improving the convenience of the connection state of the connector pins.

Although the present invention is disclosed in the foregoing embodiments as above, it is not intended to limit the present invention. Anyone familiar with similar art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of patent protection shall be subject to the definition of the scope of patent application attached to this specification.

110‧‧‧Unit under test 111‧‧‧Connector 120‧‧‧Test unit 121‧‧‧Demultiplexer 122‧‧‧Analog-to-digital converter 123‧‧‧Microcontroller 124‧‧‧Programmable logic element 1515 Analog-to-digital conversion IC410‧‧‧CPU 420‧‧‧240pin memory slot 430‧‧‧Boundary scan I/O expansion connector Step 210‧‧‧Provide a unit to be tested, the unit to be tested has a connector , The connector includes a plurality of connection pins, and each connection pin has a corresponding signal to be tested. Step 220‧‧‧ provides a test unit, which is electrically connected to the unit to be tested through the connector. In step 230‧‧‧ of receiving the signal under test, the test unit performs a boundary scan interconnection test when the signal under test is an input/output interconnection signal to detect the state of each signal under test and generate a connection message Step 240‧‧‧When the signal under test is a power signal or a pull-up signal, the test unit transmits the signal under test to a first circuit for converting the signal under test into a digital voltage value When the digital voltage value is zero, a first open circuit message is generated. Step 241‧‧‧After the test unit is a pull-up signal and the read digital voltage value is not zero, The signal to be tested is switched from the first line to the second line, and the boundary scan interconnection test is performed to read the state of each signal to be tested to detect whether there is a connection between the pins Short-circuit step 250‧‧‧When the signal under test is a ground signal or a pull-down signal, the test unit transmits the signal under test to a second line for performing boundary scan to read the corresponding signal under test A potential state, when the potential state is not a low potential, a second open circuit message is generated Step 251‧‧‧The test unit after the signal to be tested is a pull-down signal and the potential state read is not a high potential , Perform the boundary scan interconnection test to read the state of each signal under test to detect whether there is a short circuit between the connection pins

Figure 1 is a system block diagram of the pin connection test system of the connector of the present invention. Figures 2A and 2B are flowcharts of the method for testing the pin connection of the connector of the present invention. Figure 3 is a schematic diagram of applying the present invention to control programmable logic elements with JTAG commands. Figure 4 is a schematic diagram of testing memory sockets using the present invention.

110‧‧‧Unit to be tested

111‧‧‧Connector

120‧‧‧Test Unit

121‧‧‧Demultiplexer

122‧‧‧Analog-to-digital converter

123‧‧‧Microcontroller

124‧‧‧Programmable logic element

151‧‧‧First Route

152‧‧‧Second Route

Claims (10)

A connector pin connection test system, applied in a boundary scan (Boundary Scan) test environment, the system includes: a unit to be tested, the unit to be tested has a connector, and the connector includes a plurality of connection pins , Each connection pin has a corresponding signal to be tested; and a test unit for electrically connecting with the unit to be tested through the connector, the test unit includes: at least one demultiplexer, each demultiplexer The worker is electrically connected to the connector for selecting to transmit the signal to be measured from the connector to a first line or a second line; at least one analog-to-digital converter, each analog-to-digital converter having a set The analog input pin is electrically connected to the first circuit for converting the signal to be measured into a corresponding digital voltage value; a microcontroller, which is electrically connected to the analog-to-digital converter, Convert the digital voltage value code into N-bit output, where N is a positive integer; and a programmable logic element, the programmable logic element has a set of input and output pins, which are electrically connected through K pins The demultiplexer controls the demultiplexer to select the first line or the second line, electrically connect the second line through M pins to read the state of each signal under test, and N pins are electrically connected to the microcontroller to read the N-bit digital voltage value. When the signal to be tested is an input/output interconnection signal, a boundary scan interconnection test is performed to detect each The state of the signal is measured and a connection message is generated. When the signal to be measured is a power signal or a pull-up signal, the demultiplexer is controlled to select the first line, and the digital voltage value is read from the microcontroller When the read digital voltage value is zero, a first open circuit message is generated, and when the signal to be measured is a ground signal or a pull-down signal, the demultiplexer is controlled to select the second line, and Perform boundary scan to read a potential state corresponding to the signal to be measured. When the potential state is not a low potential, a second open circuit message is generated, where K and M are positive integers. The pin connection test system of the connector according to item 1 of the scope of patent application, wherein the first line is electrically connected to one end of a pull-down resistor, the other end of the pull-down resistor is grounded, and the resistance value of the pull-down resistor is at least 1M ohm. According to the first item of the scope of patent application, the connector pin connection test system, wherein the programmable logic element controls the device after the signal to be tested is a pull-up signal and the read digital voltage value is not zero. The solution multiplexer switches from the first line to the second line, and performs the boundary scan interconnection test to read the state of each signal to be tested according to the M pins to detect the connection Whether there is a short circuit between the pins. According to the first item of the scope of patent application, the connector pin connection test system, wherein the programmable logic element executes the boundary scan after the signal to be tested is a pull-down signal and the potential state read is not high The interconnection test reads the state of each signal to be tested according to the M pins to detect whether there is a short circuit between the connection pins. According to the first item of the scope of patent application, the pin connection test system of the connector, wherein the programmable logic element and the unit under test have a Joint Test Action Group (JTAG) interface for receiving data from a A JTAG command of the terminal allows the terminal to control the set of input and output pins according to the JTAG command, and to read the states of the M pins. A method for testing connector pin connections, which is applied in a boundary scan (Boundary Scan) test environment, and the steps include: providing a unit to be tested, the unit to be tested having a connector, and the connector includes a plurality of connecting pins Each connection pin has a corresponding signal to be tested; a test unit is provided, and the test unit is electrically connected to the unit to be tested through the connector to receive the signal to be tested; the test unit is in place When the signal to be tested is an input/output interconnection signal, a boundary scan interconnection test is performed to detect the state of each signal to be tested and generate a connection message; the test unit when the signal to be tested is a power signal or a pull-up signal When the signal to be tested is transmitted to a first circuit for converting the signal to be tested into a digital voltage value, when the digital voltage value is zero, a first open circuit message is generated; and the test When the signal to be measured is a ground signal or a pull-down signal, the unit transmits the signal to be measured to a second line for performing boundary scan to read a potential state corresponding to the signal to be measured. When it is not low, a second open circuit message is generated. The pin connection test method of the connector according to item 6 of the scope of patent application, wherein the method further includes the test unit after the signal to be tested is a pull-up signal and the read digital voltage value is not a value of zero, The signal to be tested is switched from the first line to the second line, and the boundary scan interconnection test is performed to read the state of each signal to be tested to detect whether there is a connection between the pins Short circuit steps. The pin connection test method of the connector according to item 6 of the scope of patent application, wherein the method further includes the test unit executing the test unit after the signal to be tested is a pull-down signal and the read potential state is not high. The boundary scan interconnection test is a step of reading the state of each signal under test to detect whether there is a short circuit between the connecting pins. The pin connection test method of the connector according to item 6 of the scope of patent application, wherein the unit to be tested and the test unit have a Joint Test Action Group (JTAG) interface for receiving from a terminal A JTAG instruction of the terminal enables the terminal to control the test unit according to the JTAG instruction and read the state of the signal to be tested. According to the pin connection test method of the 9th item of the scope of patent application, the terminal performs a circuit analysis to determine whether the signal to be tested is an input/output interconnection signal, a power signal, a pull-up signal, a ground signal, or a pull-down signal Signal, and generate the corresponding JTAG command according to the judgment result to be transmitted to the JTAG interface to control the test unit.

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