CN104090226A - Circuit for testing connectivity of chip pins - Google Patents
Circuit for testing connectivity of chip pins Download PDFInfo
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- CN104090226A CN104090226A CN201410326192.5A CN201410326192A CN104090226A CN 104090226 A CN104090226 A CN 104090226A CN 201410326192 A CN201410326192 A CN 201410326192A CN 104090226 A CN104090226 A CN 104090226A
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Abstract
The invention discloses a circuit for testing the connectivity of chip pins. The circuit for testing the connectivity of the chip pins comprises a logic gate sub-circuit, a selection sub-circuit, N input pins and M output pins, wherein N and M are natural numbers greater than or equal to two, and each input pin is connected with the logic gate sub-circuit. When external excitation is input to each input pin, each input pin inputs the external excitation to the logic gate sub-circuit. When the external excitation is changed, an output signal of the logic gate sub-circuit is changed correspondingly. The input end of the selection sub-circuit and the output end of the logic gate sub-circuit are connected with a chip body, the output end of the selection sub-circuit is connected with the output pins, and output signals of the selection sub-circuit are selected by the logic gate sub-circuit and output to the output pins. The circuit for testing the connectivity of the chip pins is simple in structure, the area and manufacturing cost of a chip are reduced, testing of the connectivity of the chip pins can be achieved rapidly, an external testing environment is simplified, and testing cost is reduced.
Description
Technical field
The present invention relates to chip testing field, relate more specifically to a kind of circuit of test chip pin connectedness.
Background technology
At present, the test mode of conventional chip pin continuity testing is in chip, to increase JTAG (Joint Test Action Group, joint test working group) to control.External testing environment is by jtag interface and jtag controller communication, and then controls polarity, the state of each chip pin.Thereby external devices only need detect each pin status, can determine whether the connection of chip pin has problems.
But by above-mentioned test mode, only the connectedness for test chip pin just need to increase jtag interface and jtag controller in chip, not only increased the manufacturing cost of area and the chip of chip, in addition, in order to test, external testing environment also must be equipped with jtag interface environment, and operation is trouble more.
Therefore, be necessary to provide a kind of circuit of improved test chip pin connectedness to overcome above-mentioned defect.
Summary of the invention
The object of this invention is to provide a kind of circuit of test chip pin connectedness, simple in structure, saved chip area and manufacturing cost, can realize rapidly the test to chip pin connectedness, external testing environment is also simplified, and has reduced testing cost.
For achieving the above object, the invention provides a kind of circuit of test chip pin connectedness, it comprises logic gate electronic circuit, chooser circuit, N input pin and M output pin, N, M is more than or equal to 2 natural number, described in each, input pin is all connected with described logic gate electronic circuit, when described in external drive inputs to each during input pin, described in each, input pin inputs to described logic gate electronic circuit by external drive, when external drive changes, the output signal of described logic subcircuit is along with respective change, the input end of described chooser circuit is connected with output terminal and the chip body of described logic gate electronic circuit respectively, the output terminal of described chooser circuit is connected with output pin described in each, described chooser circuit selects the output signal of described logic subcircuit to export output pin described in each to.
Preferably, described chooser circuit comprises M selector switch, and described in each, the input end of selector switch is connected with output terminal and the chip body of described logic gate electronic circuit respectively, and described in each, the output terminal of selector switch connects with corresponding output pin.
Preferably, described logic gate electronic circuit comprises at least two logic gate devices.
Preferably, described logic gate electronic circuit comprises N-1 XOR gate, described first input pin and second input pin are all connected with the input end of described first XOR gate, the output terminal of described first XOR gate and described the 3rd input pin are all connected with the input end of described second XOR gate, and the output terminal of described i XOR gate and i+2 input pin are connected with the input end of described i+1 XOR gate, i ∈ (2, N-2), the output terminal of described N-2 XOR gate and N input pin are connected with the input end of described N-1 XOR gate, the output terminal of described N-1 XOR gate is connected with the input end of selector switch described in each.
Compared with prior art, the circuit of test chip pin connectedness of the present invention, while changing due to external drive, the output signal of described logic subcircuit is along with respective change, thereby whether identical with the variation of external drive by the described logic subcircuit output signal of contrast, can judge that whether the connectedness of chip input pin is normal; And described chooser circuit directly inputs to the output signal of described logic subcircuit the output pin of chip, therefore, whether consistent with each output pin output signal by contrasting described logic subcircuit output signal, can judge that whether the connectedness of chip output pin is normal.Therefore, the circuit of test chip pin connectedness of the present invention, simple in structure, saved chip area and manufacturing cost, can realize rapidly the test to chip pin connectedness, external testing environment is also simplified, and has reduced testing cost.
By following description also by reference to the accompanying drawings, it is more clear that the present invention will become, and these accompanying drawings are used for explaining the present invention.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of the circuit of test chip pin connectedness of the present invention.
Fig. 2 is example structure block diagram of circuit of test chip pin connectedness of the present invention.
Embodiment
With reference now to accompanying drawing, describe embodiments of the invention, in accompanying drawing, similarly element numbers represents similar element.As mentioned above, the invention provides a kind of circuit of test chip pin connectedness, simple in structure, saved chip area and manufacturing cost, external testing environment is also simplified, and has reduced testing cost.
Please refer to Fig. 1, Fig. 1 is the structured flowchart of the circuit of test chip pin connectedness of the present invention.As shown in the figure, the circuit of test chip pin connectedness of the present invention comprises logic gate electronic circuit, chooser circuit, a N input pin (in1, in21, in3 ... in (N)) and M output pin (out1, out2, out3 ... and N, M are the natural number that is more than or equal to 2 out (M)).Input pin described in each (in1, in21, in3 ... in (N)) be all connected with described logic gate electronic circuit, when external drive inputs to input pin (in1, in21, in3 described in each ... in (N)) time, input pin described in each (in1, in21, in3 ... in (N)) external drive is inputed to described logic gate electronic circuit, and make the input signal of described logic gate electronic circuit synchronize and change with output signal by concrete logic gate electronic circuit composite design, thereby, in the present invention, if input pin described in each (in1, in21, in3 ... when connectedness in (N)) is normal, when external drive changes, the output signal of described logic gate electronic circuit is along with respective change, therefore by contrasting the output signal of described logic gate electronic circuit and the variation of input stimulus, can judge input pin (in1, in21, in3 described in each ... whether connectedness in (N)) is normal, the input end of described chooser circuit is connected with output terminal and the chip body of described logic gate electronic circuit respectively, the output terminal of described chooser circuit and output pin (out1 described in each, out2, out3 ... out (M)) connect, described chooser circuit selects the output signal of described logic subcircuit to export output pin (out1 described in each to, out2, out3 ... out (M)), also in test process, described chooser circuit only selects the output signal of described logic gate electronic circuit to transfer to output pin (out1 described in each, out2, out3 ... out (M)), thus output pin (out1 described in each, out2, out3 ... out (M)) output signal is only relevant with the output signal of described logic gate electronic circuit, irrelevant with described chip body, therefore, and as output pin (out1 described in each, out2, out3 ... when connectedness out (M)) is normal, output pin (out1 described in each, out2, out3 ... out (M)) signal of output is synchronizeed and is changed with the output of described logic gate electronic circuit, thereby judges the output signal of described logic gate electronic circuit and output pin (out1 described in each, out2, out3 ... whether output signal out (M)) synchronously changes can judge output pin (out1 described in each, out2, out3 ... whether connectedness out (M)) is normal.
Particularly, in the present invention, described chooser circuit comprises M selector switch (ch1, ch21, ch3 ... ch (M)), described in each, the input end of selector switch is connected with output terminal and the chip body of described logic gate electronic circuit respectively, described in each, the output terminal of selector switch connects with corresponding output pin, the output terminal that is selector switch ch1 is connected with output pin out1, the output terminal of selector switch ch2 is connected with output pin out2, the output terminal of selector switch ch (j) is connected with output pin out (j), j ∈ (1, M), the output terminal of selector switch ch (M) is connected with output pin out (M), thereby described selector switch (ch1, ch21, ch3 ... ch (M)) with output pin (out1, out2, out3 ... out (M)) connect one to one, thereby selector switch (ch1 described in each, ch21, ch3 ... ch (M)) signal of described logic gate electronic circuit being exported one by one correspondence transfers to described output pin (out1, out2, out3 ... out (M)).And in the present invention, described logic gate electronic circuit comprises at least two logic gate devices, in actual applications, the concrete quantity of logic gate device can be according to described input pin (in1, in21, in3 ... the type of concrete quantity in (N)) and concrete logic gate device and determining, makes the output signal of described logic gate electronic circuit react the variation of input stimulus.
Please, again in conjunction with reference to figure 2, a specific embodiment of the present invention is described.In the present embodiment, described logic gate electronic circuit comprises N-1 XOR gate (xor1, xor2, xor3 ... xor (N-1)), described first input pin in1 and second input pin in2 are all connected with the input end of described first XOR gate xor1, the output terminal of described first XOR gate xor1 and described the 3rd input pin in3 are all connected with the input end of described second XOR gate xor2, and output terminal and i+2 the input pin in (i+2) of described i XOR gate xor (i) are connected with the input end of described i+1 XOR gate xor (i+1), i ∈ (2, N-2) output terminal of described N-2 XOR gate xor (N-2) and N input pin in (N) are connected with the input end of described N-1 XOR gate xor (N-1), the output terminal of described N-1 XOR gate xor (N-1) and selector switch (ch1 described in each, ch21, ch3 ... ch (M)) input end connects.For example, when N is 3, M value is any, external drive original state is 111 o'clock, described XOR gate xor2 is output as 1, selector switch described in each (ch1, ch21, ch3 ... ch (M)) select the output correspondence of described XOR gate xor2 to input to output pin (out1, out2, out3 described in each ... out (M)), thus output pin (out1, out2, out3 described in each ... out (M)) output is 1; When if the connectedness of each input pin of chip and output pin is all normal, when external drive is changed to 011, described XOR gate xor2 is output as 0, output pin described in each (out1, out2, out3 ... out (M)) output is 0, when if the connectedness of the input pin of chip and output pin is undesired, now, the output of described XOR gate xor2 is uncertain, output pin described in each (out1, out2, out3 ... out (M)) output is not 0 entirely yet; Therefore by contrast external drive variation, can judge fast that with the whether consistent of logic gate electronic circuit output signal variation whether the connectedness of described chip input pin is normal, correspondingly, by contrast logic gate electronic circuit output signal, change change with output pin output signal whether consistent and can judge that whether the connectedness of described chip output pin is normal.
Invention has been described for above combination most preferred embodiment, but the present invention is not limited to the embodiment of above announcement, and should contain the various modifications of carrying out according to essence of the present invention, equivalent combinations.
Claims (4)
1. the circuit of a test chip pin connectedness, it is characterized in that, comprise logic gate electronic circuit, chooser circuit, N input pin and M output pin, N, M is more than or equal to 2 natural number, described in each, input pin is all connected with described logic gate electronic circuit, when described in external drive inputs to each during input pin, described in each, input pin inputs to described logic gate electronic circuit by external drive, when external drive changes, the output signal of described logic subcircuit is along with respective change, the input end of described chooser circuit is connected with output terminal and the chip body of described logic gate electronic circuit respectively, the output terminal of described chooser circuit is connected with output pin described in each, described chooser circuit selects the output signal of described logic subcircuit to export output pin described in each to.
2. the circuit of test chip pin connectedness as claimed in claim 1, it is characterized in that, described chooser circuit comprises M selector switch, described in each, the input end of selector switch is connected with output terminal and the chip body of described logic gate electronic circuit respectively, and described in each, the output terminal of selector switch connects with corresponding output pin.
3. chip pin continuity testing circuit as claimed in claim 2, is characterized in that, described logic gate electronic circuit comprises at least two logic gate devices.
4. the circuit of test chip pin connectedness as claimed in claim 3, it is characterized in that, described logic gate electronic circuit comprises N-1 XOR gate, described first input pin and second input pin are all connected with the input end of described first XOR gate, the output terminal of described first XOR gate and described the 3rd input pin are all connected with the input end of described second XOR gate, and the output terminal of described i XOR gate and i+2 input pin are connected with the input end of described i+1 XOR gate, i ∈ (2, N-2), the output terminal of described N-2 XOR gate and N input pin are connected with the input end of described N-1 XOR gate, the output terminal of described N-1 XOR gate is connected with the input end of selector switch described in each.
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| CN201410326192.5A CN104090226B (en) | 2014-07-09 | 2014-07-09 | Circuit for testing connectivity of chip pins |
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| CN201410326192.5A CN104090226B (en) | 2014-07-09 | 2014-07-09 | Circuit for testing connectivity of chip pins |
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| CN104090226B CN104090226B (en) | 2017-01-18 |
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Cited By (4)
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| CN110118921A (en) * | 2018-02-07 | 2019-08-13 | 龙芯中科技术有限公司 | Integrated circuit input end test device and integrated circuit |
| CN110118922A (en) * | 2018-02-07 | 2019-08-13 | 龙芯中科技术有限公司 | Ic output test device and integrated circuit |
| CN110736919A (en) * | 2019-10-25 | 2020-01-31 | 深圳忆联信息系统有限公司 | Method and test circuit for improving test coverage rate in SoC design |
| CN115865747A (en) * | 2022-12-30 | 2023-03-28 | 上海芯联芯智能科技有限公司 | Method and device for detecting connectivity of chip |
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| CN104090226B (en) | 2017-01-18 |
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