CN204008991U - The circuit of test chip pin connectedness - Google Patents
The circuit of test chip pin connectedness Download PDFInfo
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- CN204008991U CN204008991U CN201420378744.2U CN201420378744U CN204008991U CN 204008991 U CN204008991 U CN 204008991U CN 201420378744 U CN201420378744 U CN 201420378744U CN 204008991 U CN204008991 U CN 204008991U
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Abstract
The utility model discloses a kind of circuit of test chip pin connectedness, it comprises chooser circuit, N input pin and N output pin, N is more than or equal to 2 natural number, the input end of described chooser circuit respectively with chip body and described in each input pin be connected, the output terminal of described chooser circuit is connected with output pin described in each, when described in external drive inputs to each when input pin, described in each, external drive is inputed to described chooser circuit by input pin, described chooser circuit selects described in each output signal of input pin to export output pin described in each to.The circuit of test chip pin connectedness of the present utility model, simple in structure, save chip area and manufacturing cost, can realize rapidly the test to chip pin connectedness, external testing environment is also simplified, and has reduced testing cost.
Description
Technical field
The utility model relates to chip testing field, relates more specifically to a kind of circuit of test chip pin connectedness.
Background technology
At present, the test mode of conventional chip pin continuity testing is in chip, to increase JTAG (JointTest Action Group, joint test working group) to control.External testing environment is by jtag interface and jtag controller communication, and then controls polarity, the state of each chip pin.Thereby external devices only need detect each pin status, can determine whether the connection of chip pin has problems.
But by above-mentioned test mode, only for the connectedness of test chip pin just need to increase jtag interface and jtag controller in chip, not only increase the manufacturing cost of area and the chip of chip, in addition, in order to test, external testing environment also must be equipped with jtag interface environment, and operation is trouble more.
Therefore, be necessary to provide a kind of circuit of improved test chip pin connectedness to overcome above-mentioned defect.
Utility model content
The purpose of this utility model is to provide a kind of circuit of test chip pin connectedness, simple in structure, has saved chip area and manufacturing cost, can realize rapidly the test to chip pin connectedness, and external testing environment is also simplified, and has reduced testing cost.
For achieving the above object, the utility model provides a kind of circuit of test chip pin connectedness, it comprises chooser circuit, N input pin and N output pin, N is more than or equal to 2 natural number, the input end of described chooser circuit respectively with chip body and described in each input pin be connected, the output terminal of described chooser circuit is connected with output pin described in each, when described in external drive inputs to each when input pin, described in each, external drive is inputed to described chooser circuit by input pin, described chooser circuit selects described in each output signal of input pin to export output pin described in each to.
Preferably, described chooser circuit comprises N selector switch, and the input end of each described selector switch is connected with chip body and corresponding input pin respectively, and the output terminal of each described selector switch connects with corresponding output pin.
Preferably, described the 1st input pin is inputted in external drive, described the 1st output pin is connected with described the 2nd input pin, and described i output pin is connected with described i+1 input pin, i ∈ (2, N-2), described N-1 output pin is connected with described N defeated pin, and described N output pin is only connected with the output terminal of described N selector switch.Preferably, described chooser circuit comprises N selector switch, and the input end of each described selector switch is connected with output terminal and the chip body of described logic gate electronic circuit respectively, and the output terminal of each described selector switch connects with corresponding output pin.
Compared with prior art, the circuit of test chip pin connectedness of the present utility model, each input pin is connected with each output pin by described chooser circuit, therefore, whether the external drive signal of inputting described input pin by contrast is consistent with each output pin output signal, can judge that whether the connectedness of chip output pin and input pin is normal.Therefore, the circuit of test chip pin connectedness of the present utility model, simple in structure, save chip area and manufacturing cost, can realize rapidly the test to chip pin connectedness, external testing environment is also simplified, and has reduced testing cost.
By following description also by reference to the accompanying drawings, it is more clear that the utility model will become, and these accompanying drawings are used for explaining the utility model.
Brief description of the drawings
Fig. 1 is the structured flowchart of the circuit of the utility model test chip pin connectedness.
Fig. 2 is the structured flowchart of an embodiment of circuit of the utility model test chip pin connectedness.
Embodiment
With reference now to accompanying drawing, describe embodiment of the present utility model, in accompanying drawing, similarly element numbers represents similar element.As mentioned above, the utility model provides a kind of circuit of test chip pin connectedness, simple in structure, has saved chip area and manufacturing cost, and external testing environment is also simplified, and has reduced testing cost.
Please refer to Fig. 1, Fig. 1 is the structured flowchart of the circuit of the utility model test chip pin connectedness.As shown in the figure, the circuit of test chip pin connectedness of the present utility model comprises chooser circuit, a N input pin (in1, in21, in3......in (N)) and N output pin (out1, out2, out3......out (N)), and N is more than or equal to 2 natural number.The input end of described chooser circuit is connected with input pin described in each (in1, in21, in3......in (N)) and chip body respectively, and the output terminal of described chooser circuit is connected with output pin described in each (out1, out2, out3......out (N)).In the time that each pin is tested, input pin (in1, in21, in3......in (N)) described in each is inputted in external drive, and described chooser circuit is selected the external drive that input pin (in1, in21, in3......in (N)) receives described in each and exported output pin (out1, out2, out3......out (N)) described in each to; Also in test process, described chooser circuit only selects described in each output signal (external drive) of input pin (in1, in21, in3......in (N)) to transfer to output pin (out1, out2, out3......out (N)) described in each, thereby the output signal of output pin described in each (out1, out2, out3......out (N)) is only corresponding with the input/output signal of input pin described in each (in1, in21, in3......in (N)), and irrelevant with described chip body; Therefore, when when input pin described in each (in1, in21, in3......in (N)) and described in each, the connectedness of output pin (out1, out2, out3......out (N)) is normal, the signal of output pin described in each (out1, out2, out3......out (N)) output is synchronizeed and is changed with the I/O of input pin described in each (in1, in21, in3......in (N)); Thereby, input/output signal by judging input pin (in1, in21, in3......in (N)) described in each and the output signal of output pin described in each (out1, out2, out3......out (N)) whether synchronize change can judge the input pin of chip and the connectedness of output pin whether normal, therefore, the circuit of test chip pin connectedness of the present utility model can be realized the test to chip pin connectedness rapidly, external testing environment is also simplified, and has reduced testing cost.
Particularly, in the utility model, described chooser circuit comprises N selector switch (ch1, ch21, ch3......ch (N)), the input end of each described selector switch is connected with corresponding input pin and chip body respectively, and the output terminal of each described selector switch connects with corresponding output pin.The input end that is selector switch ch1 is connected with input pin in1, and its output terminal is connected with output pin out1; The input end of selector switch ch2 is connected with input pin in2, and its output terminal is connected with output pin out2; The input end of selector switch ch (j) is connected with input pin in (j), and its output terminal is connected with output pin out (j), j ∈ (1, N); The input end of selector switch ch (N) is connected with input pin in (N), and its output terminal is connected with output pin out (N); Described selector switch (ch1, ch21, ch3......ch (N)) and input pin (in1, in21, in3......in (N)) and output pin (out1, out2, out3......out (N)) are connected one to one; Thereby the signal that selector switch described in each (ch1, ch21, ch3......ch (N)) is exported input pin described in each (in1, in21, in3......in (N)) one by one correspondence transfers to described output pin (out1, out2, out3......out (N)); Therefore the difference of, inputting external drive and each output pin (out1, out2, out3......out (N)) output signal by contrast can judge that to the connectedness of I/O pin normally whether N rapidly.
Please, again in conjunction with reference to figure 2, a specific embodiment of the present utility model is described.In the present embodiment, described the 1st input pin in1 is inputted in external drive, described the 1st output pin out1 is connected with described the 2nd input pin in2, make described the 1st output pin out1 export the external drive of described the 1st input pin in1 input to the 2nd input pin in2, using the input stimulus as described the 2nd input pin in2; And described i output pin is connected with described i+1 input pin, i ∈ (2, N-2), make the output signal of described i output pin out (i) input to described i+1 input pin in (i+1), using the input stimulus as i+1 input pin in (i+1); So corresponding repetition, until the output signal of described N-1 output pin out (N-1) inputs to described N input pin in (N), using as N input pin in (N), described N output pin is only connected with the output terminal of described N selector switch.Therefore, in the present embodiment, only input external drive to described input pin in1, can make other all input pin and output pin all have excitation I/O, and the output signal of previous output pin is as the input stimulus of next input pin, so repeat, thereby whether the output signal that only need contrast output pin out (N) is consistent with the variation of the external drive of the described input pin in1 of input, whether the connectedness that can judge described chip I/O pin is normal, further simplify external testing environment, and test process is quick, result is accurate.
In conjunction with most preferred embodiment, the utility model is described above, but the utility model is not limited to the embodiment of above announcement, and should contains the various amendments of carrying out according to essence of the present utility model, equivalent combinations.
Claims (3)
1. the circuit of a test chip pin connectedness, it is characterized in that, comprise chooser circuit, N input pin and N output pin, N is more than or equal to 2 natural number, the input end of described chooser circuit respectively with chip body and described in each input pin be connected, the output terminal of described chooser circuit is connected with output pin described in each, when described in external drive inputs to each when input pin, described in each, external drive is inputed to described chooser circuit by input pin, described chooser circuit selects described in each output signal of input pin to export output pin described in each to.
2. the circuit of test chip pin connectedness as claimed in claim 1, it is characterized in that, described chooser circuit comprises N selector switch, the input end of each described selector switch is connected with chip body and corresponding input pin respectively, and the output terminal of each described selector switch connects with corresponding output pin.
3. the circuit of test chip pin connectedness as claimed in claim 2, it is characterized in that, described the 1st input pin is inputted in external drive, described the 1st output pin is connected with described the 2nd input pin, and described i output pin is connected with described i+1 input pin, i ∈ (2, N-2), described N-1 output pin is connected with described N input pin, and described N output pin is only connected with the output terminal of described N selector switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420378744.2U CN204008991U (en) | 2014-07-09 | 2014-07-09 | The circuit of test chip pin connectedness |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420378744.2U CN204008991U (en) | 2014-07-09 | 2014-07-09 | The circuit of test chip pin connectedness |
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| Publication Number | Publication Date |
|---|---|
| CN204008991U true CN204008991U (en) | 2014-12-10 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201420378744.2U Expired - Fee Related CN204008991U (en) | 2014-07-09 | 2014-07-09 | The circuit of test chip pin connectedness |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104090225A (en) * | 2014-07-09 | 2014-10-08 | 四川和芯微电子股份有限公司 | Circuit for testing connectivity of chip pins |
-
2014
- 2014-07-09 CN CN201420378744.2U patent/CN204008991U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104090225A (en) * | 2014-07-09 | 2014-10-08 | 四川和芯微电子股份有限公司 | Circuit for testing connectivity of chip pins |
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| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20141210 Termination date: 20160709 |
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| CF01 | Termination of patent right due to non-payment of annual fee |