CN104090226B - Circuit for testing connectivity of chip pins - Google Patents
Circuit for testing connectivity of chip pins Download PDFInfo
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- CN104090226B CN104090226B CN201410326192.5A CN201410326192A CN104090226B CN 104090226 B CN104090226 B CN 104090226B CN 201410326192 A CN201410326192 A CN 201410326192A CN 104090226 B CN104090226 B CN 104090226B
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Abstract
The invention discloses a circuit for testing the connectivity of chip pins. The circuit for testing the connectivity of the chip pins comprises a logic gate sub-circuit, a selection sub-circuit, N input pins and M output pins, wherein N and M are natural numbers greater than or equal to two, and each input pin is connected with the logic gate sub-circuit. When external excitation is input to each input pin, each input pin inputs the external excitation to the logic gate sub-circuit. When the external excitation is changed, an output signal of the logic gate sub-circuit is changed correspondingly. The input end of the selection sub-circuit and the output end of the logic gate sub-circuit are connected with a chip body, the output end of the selection sub-circuit is connected with the output pins, and output signals of the selection sub-circuit are selected by the logic gate sub-circuit and output to the output pins. The circuit for testing the connectivity of the chip pins is simple in structure, the area and manufacturing cost of a chip are reduced, testing of the connectivity of the chip pins can be achieved rapidly, an external testing environment is simplified, and testing cost is reduced.
Description
Technical field
The present invention relates to chip testing field, relate more specifically to a kind of connective circuit of test chip pin.
Background technology
At present, the test mode of conventional chip pin continuity testing is increase jtag (joint test in chip
Action group, joint test working group) control.External testing environment passes through jtag interface and jtag controller communication, enters
And control the polarity of each chip pin, state.Thus, external devices only need to detect each pin status, you can determines chip pipe
The connection of foot whether there is problem.
But by above-mentioned test mode, the connectedness only for test chip pin is accomplished by increasing in the chips jtag
Interface and jtag controller, not only increase the area of chip and the manufacturing cost of chip, in addition, in order to test, external testing
Environment also must be equipped with jtag interface environment, and operation more bothers.
Therefore, it is necessary to provide a kind of connective circuit of improved test chip pin to overcome drawbacks described above.
Content of the invention
It is an object of the invention to provide a kind of connective circuit of test chip pin, structure is simple, saves chip face
Long-pending Manufacturing cost, can rapidly realize the test connective to chip pin, external testing environment is also simplified, and reduces
Testing cost.
For achieving the above object, the present invention provides a kind of test chip pin connective circuit, and it includes logic MENZI
Circuit, selection electronic circuit, n input pin and m output pin, n, m are the natural number more than or equal to 2, and each is described defeated
Enter pin to be all connected with described gate electronic circuit, when external drive inputs to input pin each described, each is described defeated
Enter pin to input external drive to described gate electronic circuit, when external drive changes, described gate electronic circuit
Output signal with respective change, the input of described selection electronic circuit respectively with the outfan of described gate electronic circuit and
Chip body connects, and the described outfan selecting electronic circuit is connected with output pin each described, and described selection electronic circuit selects
The output signal of described gate electronic circuit exports to output pin each described.
It is preferred that described selection electronic circuit includes m selector, the input of each described selector is patrolled with described respectively
Collect the outfan of MENZI circuit and chip body connects, the outfan of each described selector is connected with corresponding output pin.
It is preferred that described gate electronic circuit includes at least two logic gate device.
It is preferred that described gate electronic circuit includes n-1 XOR gate, described first input pin and second input
Pin is all connected with the input of described first XOR gate, the outfan of described first XOR gate and described 3rd input
Pin is all connected with the input of described second XOR gate, and the outfan of described i-th XOR gate and the i-th+2 input pipes
Foot is connected with the input of described i+1 XOR gate, i ∈ (2, n-2), the outfan of described the n-th -2 XOR gates and n-th
Input pin is connected with the input of described (n-1)th XOR gate, the outfan of described (n-1)th XOR gate and each described choosing
The input selecting device connects.
Compared with prior art, the connective circuit of the test chip pin of the present invention, because external drive changes
When, the output signal of described gate electronic circuit is with respective change, thus being believed by contrasting described gate electronic circuit output
Number whether identical with the change of external drive, you can to judge whether the connectedness of chip input pin is normal；And described select son
Circuit directly inputs the output signal of described gate electronic circuit to the output pin of chip, therefore, by patrolling described in contrast
Whether volume MENZI circuit output signal is consistent with each output pin output signal, you can the connectedness judging chip output pin is
No normal.Therefore, the connective circuit of the test chip pin of the present invention, structure is simple, saves chip area and is manufactured into
This, can rapidly realize the test connective to chip pin, external testing environment is also simplified, and reduces testing cost.
By description below and combine accompanying drawing, the present invention will become more fully apparent, and these accompanying drawings are used for explaining the present invention.
Brief description
Fig. 1 is the structured flowchart of the connective circuit of test chip pin of the present invention.
Fig. 2 is the connective one example structure block diagram of circuit of test chip pin of the present invention.
Specific embodiment
With reference now to Description of Drawings embodiments of the invention, in accompanying drawing, similar element numbers represent similar element.As
Upper described, the invention provides a kind of connective circuit of test chip pin, structure is simple, saves chip area and manufacture
Cost, external testing environment is also simplified, and reduces testing cost.
Refer to Fig. 1, Fig. 1 is the structured flowchart of the connective circuit of test chip pin of the present invention.As illustrated, this
The connective circuit of bright test chip pin include gate electronic circuit, select electronic circuit, n input pin (in1, in21,
In3 ... in (n)) and m output pin (out1, out2, out3 ... out (m)), and n, m are oneself more than or equal to 2
So count.Each described input pin (in1, in21, in3 ... in (n)) is all connected with described gate electronic circuit, swashs when outside
When encouraging input to input pin each described (in1, in21, in3 ... in (n)), each described input pin (in1, in21,
In3 ... in (n)) external drive is inputted to described gate electronic circuit；And set by the combination of specific gate electronic circuit
Meter makes the input signal of described gate electronic circuit and output signal synchronously change, thus, in the present invention, if described in each
When the connectedness of input pin (in1, in21, in3 ... in (n)) is normal, when external drive changes, described gate
The output signal of electronic circuit, with respective change, is therefore passed through to contrast output signal and the input stimulus of described gate electronic circuit
Change can determine whether whether the connectedness of each described input pin (in1, in21, in3 ... in (n)) normal；Described choosing
The input selecting electronic circuit connects with the outfan of described gate electronic circuit and chip body respectively, described selection electronic circuit
Outfan is connected with output pin each described (out1, out2, out3 ... out (m)), and described selection electronic circuit selects described
The output signal of gate electronic circuit exports to output pin each described (out1, out2, out3 ... out (m)), Ye Ji
In test process, described selection electronic circuit only selects the output signal of described gate electronic circuit to transmit to outlet tube each described
Foot (out1, out2, out3 ... out (m)), thus each described output pin (out1, out2, out3 ... out (m))
Output signal is only relevant with the output signal of described gate electronic circuit, unrelated with described chip body, therefore, when described in each
Output pin (out1, out2, out3 ... out (m)) connective normal when, each described output pin (out1, out2,
Out3 ... out (m)) signal that exports synchronously changed with the output of described gate electronic circuit, thus judging described gate
Whether the output signal of electronic circuit is same with the output signal of each described output pin (out1, out2, out3 ... out (m))
Step change can determine whether whether the connectedness of each described output pin (out1, out2, out3 ... out (m)) is normal.
Specifically, in the present invention, described selection electronic circuit includes m selector (ch1, ch21, ch3 ... ch (m)),
The input of each described selector connects with the outfan of described gate electronic circuit and chip body respectively, each described choosing
The outfan selecting device is connected with corresponding output pin, and that is, the outfan of selector ch1 and output pin out1 connect, selector
The outfan of ch2 and output pin out2 connect, and the outfan of selector ch (j) and output pin out (j) connect, j ∈ (1,
M), the outfan of selector ch (m) and output pin out (m) connect, thus described selector (ch1, ch21, ch3 ... ch
(m)) connect one to one with output pin (out1, out2, out3 ... out (m)), thus each described selector (ch1,
Ch21, ch3 ... ch (m)) signal of described gate electronic circuit output is corresponded and transmits to described output pin
(out1、out2、out3……out(m)).And in the present invention, described gate electronic circuit includes at least two gate devices
Part, in actual applications, the particular number of logic gate device can be according to described input pin (in1, in21, in3 ... in (n))
Particular number and the type of concrete logic gate device and determine the output signal reaction input so that described gate electronic circuit
The change of excitation.
Please in conjunction with reference to Fig. 2, a specific embodiment of the description present invention.In the present embodiment, described logic MENZI
Circuit includes n-1 XOR gate (xor1, xor2, xor3 ... xor (n-1)), described first input pin in1 and second
Input pin in2 is all connected with the input of described first XOR gate xor1, the outfan of described first XOR gate xor1
And described 3rd input pin in3 is all connected with the input of described second XOR gate xor2, and described i-th XOR gate
The input of the outfan of xor (i) and the i-th+2 input pin in (i+2) and described i+1 XOR gate xor (i+1) is even
Connect, the outfan of described the n-th -2 XOR gate xor (n-2) of i ∈ (2, n-2) and n-th input pin in (n) and described (n-1)th
Input connection, the outfan of described (n-1)th XOR gate xor (n-1) and each described selection of individual XOR gate xor (n-1)
The input of device (ch1, ch21, ch3 ... ch (m)) connects.For example, when n is 3, m value is any, external drive initial shape
When state is 111, described XOR gate xor2 is output as 1, and each described selector (ch1, ch21, ch3 ... ch (m)) selects institute
The output stating XOR gate xor2 corresponds to input to output pin each described (out1, out2, out3 ... out (m)), thus respectively
The output of individual described output pin (out1, out2, out3 ... out (m)) is 1；If each input pin of chip with defeated
Go out the connectedness of pin all normal when, turn to 011 when external drive becomes, described XOR gate xor2 is output as 0, each described output
The output of pin (out1, out2, out3 ... out (m)) is 0, if the connectedness of the input pin of chip and output pin
When abnormal, then now, the output of described XOR gate xor2 does not know, each described output pin (out1, out2, out3 ...
Out (m)) output be also not all 0；Therefore pass through to contrast external drive change and the one of the change of gate electronic circuit output signal
Whether cause the connectedness that can quickly judge described chip input pin whether normal, correspondingly, by contrasting logic MENZI electricity
The whether consistent connection that can determine whether described chip output pin that road output signal change is changed with output pin output signal
Whether property is normal.
Above in association with most preferred embodiment, invention has been described, but the invention is not limited in enforcement disclosed above
Example, and modification, the equivalent combinations that the various essence according to the present invention are carried out should be covered.
Claims (3)
1. a kind of connective circuit of test chip pin is it is characterised in that including gate electronic circuit, selecting electronic circuit, n
Input pin and m output pin, n, m are the natural number more than or equal to 2, each described input pin all with described logic
MENZI circuit connects, and when external drive inputs to input pin each described, each described input pin is defeated by external drive
Enter to described gate electronic circuit, when external drive changes, the output signal of described gate electronic circuit is with corresponding
Change, the described input selecting electronic circuit connects with the outfan of described gate electronic circuit and chip body respectively, described
The outfan selecting electronic circuit is connected with output pin each described, and described selection electronic circuit selects described gate electronic circuit
Output signal exports to output pin each described；Described selection electronic circuit include m selector, each described selector defeated
Enter end to connect with the outfan of described gate electronic circuit and chip body respectively, the outfan of each described selector with corresponding
Output pin connect.
2. the connective circuit of test chip pin as claimed in claim 1 is it is characterised in that described gate electronic circuit bag
Include at least two logic gate device.
3. the connective circuit of test chip pin as claimed in claim 2 is it is characterised in that described gate electronic circuit bag
Include n-1 XOR gate, the first described input pin and second input pin input all with first described XOR gate
Connection, the outfan of first described XOR gate and the 3rd input all with second described XOR gate for the described input pin
Connect, and the input of the outfan of XOR gate described in i-th and the i-th+2 input pins and the described XOR gate of i+1 is even
Connect, i ∈ (2, n-2), the outfan of the n-th -2 described XOR gates and n-th input pin are defeated with (n-1)th described XOR gate
Enter end to connect, the outfan of (n-1)th described XOR gate is connected with the input of selector each described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410326192.5A CN104090226B (en) | 2014-07-09 | 2014-07-09 | Circuit for testing connectivity of chip pins |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410326192.5A CN104090226B (en) | 2014-07-09 | 2014-07-09 | Circuit for testing connectivity of chip pins |
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| Publication Number | Publication Date |
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| CN104090226A CN104090226A (en) | 2014-10-08 |
| CN104090226B true CN104090226B (en) | 2017-01-18 |
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| CN201410326192.5A Active CN104090226B (en) | 2014-07-09 | 2014-07-09 | Circuit for testing connectivity of chip pins |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110118922B (en) * | 2018-02-07 | 2022-02-15 | 龙芯中科技术股份有限公司 | Integrated circuit output end testing device and integrated circuit |
| CN110118921B (en) * | 2018-02-07 | 2021-08-03 | 龙芯中科技术股份有限公司 | Integrated circuit input end testing device and integrated circuit |
| CN110736919A (en) * | 2019-10-25 | 2020-01-31 | 深圳忆联信息系统有限公司 | Method and test circuit for improving test coverage rate in SoC design |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20120324302A1 (en) * | 2011-06-17 | 2012-12-20 | Qualcomm Incorporated | Integrated circuit for testing using a high-speed input/output interface |
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Patent Citations (10)
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|---|---|---|---|---|
| US4875003A (en) * | 1989-02-21 | 1989-10-17 | Silicon Connections Corporation | Non-contact I/O signal pad scan testing of VLSI circuits |
| US6407613B1 (en) * | 1997-05-27 | 2002-06-18 | Hewlett-Packard Company | Multipurpose test chip input/output circuit |
| CN1693917A (en) * | 2004-05-06 | 2005-11-09 | 横河电机株式会社 | Semiconductor integrated circuit and testing system |
| CN101063700A (en) * | 2007-05-29 | 2007-10-31 | 北京中星微电子有限公司 | Method and arrangement for implementing chip test |
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| CN104090226A (en) | 2014-10-08 |
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