TWI609185B - Expansion circuit board for expanding jtag interface - Google Patents

Description

Provides an expansion board that expands the joint test workgroup interface

An expansion circuit board, in particular, a combination of a test data input pin, a test data output pin, a test clock pin, and a test mode selection pin through a line configuration, a multiplexer, and a buffer, providing expansion The joint test workgroup connection interface controls the extended joint test workgroup connection interface to provide an expansion board that expands the joint test workgroup interface.

The boundary scan test of a general circuit or the test of a slot using a boundary scan is usually performed by testing the access controller. However, the test access controller is generally only limited in number. Test access, if the boundary scan test of the circuit requires a large number of joint test workgroup interfaces, multiple test access controllers are required, but the test cost is higher, if a limited number of tests are used When the controller is taken, it takes extra test time, and it may cause problems in the test signal coverage.

In summary, it can be seen that in the prior art, there has been a long-standing problem that the existing test access controller provides a limited number of test accesses and cannot satisfy a large number of tests or meets a large number of tests but requires high test costs. An improved technical means is proposed to solve this problem.

In view of the prior art, there is a problem that the existing test access controller provides a limited number of test accesses to satisfy a large number of tests or a large number of tests but requires a high test cost, and the present invention discloses an extended joint test work group. Group interface expansion board, where:

The invention provides an expansion board for extending the joint test work group interface, which comprises: a Joint Test Action Group (JTAG) expansion circuit board, and a joint test work group expansion circuit board further includes: Test the workgroup connection interface and the eight extended joint test workgroup connection interfaces.

The joint test work group connection interface further includes a first test data input (TDI) pin, a first test data output (TDO) pin, and a first test clock (Test Clock, TCK). The pin and the first Test Mode Select (TMS) pin; the joint test work group connection interface is electrically connected to the test access port of the Test Access Port (TAP) controller.

The joint test work group connection interface is expanded, and each extended joint test work group connection interface further includes a second test data input pin, a second test data output pin, a second test clock pin, and a second test mode selection.

The first test data input pin is electrically connected to the second test data input pin of each extended joint test work group connection interface through the first multiplexer (Multiplexer); the first test data output pin is transmitted through the second The multiplexer is electrically connected to the second test data output pin of each extended joint test work group connection interface; the second test data output pin of each extended joint test work group connection interface is transmitted through the protection resistor and the other An extended joint test work group The second test data input pin of the interface is electrically connected, so that each extended joint test work group connection interface forms a serial connection; the first test clock pin is electrically connected to the expansion through the first buffer (Buffer) The second test clock pin of the joint test work group connection interface; and the first test mode selection pin is electrically connected to the second test mode selection pin of the extended joint test work group connection interface through the second buffer.

The circuit board disclosed in the present invention is different from the prior art in that the first test data input pin is electrically connected to the second test data of each extended joint test work group connection interface through the first multiplexer. The input pin position, the first test data output pin is electrically connected to the second test data output pin of each extended joint test work group connection interface through the second multiplexer, and each extended joint test work group connection The second test data output pin of the interface is electrically connected to the second test data input pin of the expansion joint test work group connection interface through the protection resistor, and the first test clock pin is electrically connected through the first buffer respectively. The second test clock pin for expanding the joint test work group connection interface, and the first test mode selection pin are respectively electrically connected to the second test mode selection pin of the extended joint test work group connection interface through the second buffer Bit, through which the first multiplexer, the second multiplexer, the first buffer, and the second buffer are accessed through the test access controller. The controller to select the need to control the expansion of the joint working group to test the connection interface for subsequent testing of all kinds of joint testing group.

Through the above technical means, the present invention can achieve the technical effect of providing an extended joint test work group connection interface to improve the joint test work group test requirements.

10‧‧‧Joint Test Workgroup Expansion Board

11‧‧‧Joint test workgroup connection interface

121‧‧‧First Expansion Joint Test Workgroup Connection Interface

122‧‧‧Second Extended Joint Test Workgroup Connection Interface

123‧‧‧The third extended joint test work group connection interface

124‧‧‧Fourth Expansion Joint Test Workgroup Connection Interface

125‧‧‧Fixed Extended Joint Test Workgroup Connection Interface

126‧‧‧ sixth expansion joint test work group connection interface

127‧‧‧ seventh expansion joint test work group connection interface

128‧‧‧8th expansion joint test work group connection interface

13‧‧‧First multiplexer

14‧‧‧Second multiplexer

151‧‧‧First protection resistor

152‧‧‧Second protective resistor

153‧‧‧ Third protective resistor

154‧‧‧4th protective resistor

155‧‧‧ Fifth protection resistor

156‧‧‧ sixth protection resistor

157‧‧‧ seventh protective resistor

16‧‧‧First buffer

171‧‧‧First matching resistor

172‧‧‧First matching resistor

173‧‧‧First matching resistor

174‧‧‧First matching resistor

175‧‧‧First matching resistor

176‧‧‧First matching resistor

177‧‧‧First matching resistor

178‧‧‧First matching resistor

181‧‧‧Second matching resistor

182‧‧‧Second matching resistor

183‧‧‧Second matching resistor

184‧‧‧Second matching resistor

185‧‧‧second matching resistor

186‧‧‧Second matching resistor

187‧‧‧Second matching resistor

188‧‧‧Second matching resistor

19‧‧‧Second buffer

20‧‧‧Test access controller

21‧‧‧Test access

22‧‧‧Control input and output pins

TDI‧‧‧ first test data input pin

TDO‧‧‧ first test data output pin

TCK‧‧‧ first test clock pin

TMS‧‧‧First test mode selection pin

TDI_1‧‧‧Second test data input pin

TDO_1‧‧‧Second test data output pin

TCK_1‧‧‧Second test clock pin

TMS_1‧‧‧Second test mode selection pin

TDI_2‧‧‧Second test data input pin

TDO_2‧‧‧Second test data output pin

TCK_2‧‧‧Second test clock pin

TMS_2‧‧‧Second test mode selection pin

TDI_3‧‧‧Second test data input pin

TDO_3‧‧‧Second test data output pin

TCK_3‧‧‧Second test clock pin

TMS_3‧‧‧Second test mode selection pin

TDI_4‧‧‧Second test data input pin

TDO_4‧‧‧Second test data output pin

TCK_4‧‧‧Second test clock pin

TMS_4‧‧‧Second test mode selection pin

TDI_5‧‧‧Second test data input pin

TDO_5‧‧‧Second test data output pin

TCK_5‧‧‧Second test clock pin

TMS_5‧‧‧Second test mode selection pin

TDI_6‧‧‧Second test data input pin

TDO_6‧‧‧Second test data output pin

TCK_6‧‧‧Second test clock pin

TMS_6‧‧‧Second test mode selection pin

TDI_7‧‧‧Second test data input pin

TDO_7‧‧‧Second test data output pin

TCK_7‧‧‧Second test clock pin

TMS_7‧‧‧Second test mode selection pin

TDI_8‧‧‧Second test data input pin

TDO_8‧‧‧Second test data output pin

TCK_8‧‧‧Second test clock pin

TMS_8‧‧‧Second test mode selection pin

FIG. 1 and FIG. 2 are schematic diagrams showing the connection between the test data input pin and the test data output pin circuit of the expansion circuit board of the extended joint test work group interface according to the present invention.

FIG. 3 is a schematic diagram showing the connection of the test clock pin circuit of the expansion circuit board of the extended joint test work group interface according to the present invention.

FIG. 4 is a schematic diagram showing the connection of the test mode selection pin circuit of the expansion circuit board of the extended joint test work group interface according to the present invention.

FIG. 5 is a schematic diagram showing the connection between the expansion circuit board and the test access controller of the expansion circuit board of the extended joint test work group interface according to the present invention.

The embodiments of the present invention will be described in detail below with reference to the drawings and embodiments, so that the application of the technical means to solve the technical problems and achieve the technical effects can be fully understood and implemented.

The following is an explanation of the extended circuit board of the present invention for providing an extended joint test working group interface.

The invention provides an expansion circuit board for extending the joint test work group interface, which comprises: a Joint Test Action Group (JTAG) expansion circuit board 10, and the joint test work group expansion circuit board 10 further includes The joint test work group connection interface 11 and the first extended joint test work group connection interface 121 to the eighth extended joint test work group connection interface 128.

The joint test work group connection interface 11 of the joint test work group expansion circuit board 10 further includes a first test data input pin TDI, a first test data output pin TDO, and a first test. The clock pin TCK and the first test mode selection pin TMS, the joint test work group connection interface 11 of the joint test work group expansion circuit board 10 is electrically connected to the Test Access Port (TAP). The test of the controller 20 is accessed 埠21.

The first extended joint test work group connection interface 121 further includes a second test data input pin TDI_1, a second test data output pin TDO_1, a second test clock pin TCK_1, and a second test mode selection TMS_1.

The second extended joint test work group connection interface 122 further includes a second test data input pin TDI_2, a second test data output pin TDO_2, a second test clock pin TCK_2, and a second test mode selection TMS_2.

The third extended joint test work group connection interface 123 further includes a second test data input pin TDI_3, a second test data output pin TDO_3, a second test clock pin TCK_3, and a second test mode selection TMS_3.

The fourth extended joint test work group connection interface 124 further includes a second test data input pin TDI_4, a second test data output pin TDO_4, a second test clock pin TCK_4, and a second test mode selection TMS_4.

The fifth extended joint test work group connection interface 125 further includes a second test data input pin TDI_5, a second test data output pin TDO_5, a second test clock pin TCK_5, and a second test mode selection TMS_5.

The sixth extended joint test work group connection interface 126 further includes a second test data input pin TDI_6, a second test data output pin TDO_6, a second test clock pin TCK_6, and a second test mode selection TMS_6.

The seventh extended joint test work group connection interface 127 further includes a second test data input pin TDI_7, a second test data output pin TDO_7, a second test clock pin TCK_7, and a second test mode selection TMS_7.

The eighth extended joint test work group connection interface 128 further includes a second test data input pin TDI_8, a second test data output pin TDO_8, a second test clock pin TCK_8, and a second test mode selection TMS_8.

Please refer to "Figure 1" and "Figure 2". "Figure 1" and "Figure 2" show the test data input pin of the expansion board provided with the extended joint test work group interface. Connected to the test data output pin circuit.

The first test data input pin TDI is electrically connected to the second test data input pin TDI_1 of the first extended joint test work group connection interface 121 through the first multiplexer (Multiplexer) 13; the first test data input pin position The TDI is electrically connected to the second test data input pin TDI_2 of the second extended joint test work group connection interface 122 through the first multiplexer 13; the first test data input pin TDI is electrically transmitted through the first multiplexer 13 Connected to the second test data input pin TDI_3 of the third extended joint test work group connection interface 123; the first test data input pin TDI is electrically connected to the fourth extended joint test work group through the first multiplexer 13 The second test data input pin TDI_4 of the connection interface 124; the first test data input pin TDI is electrically connected to the second test data input pin of the fifth extended joint test work group connection interface 125 through the first multiplexer 13 Bit TDI_5; the first test data input pin TDI is electrically connected to the second test data input pin TDI_6 of the sixth extended joint test work group connection interface 126 through the first multiplexer 13; The test data input pin TDI is electrically connected to the second test data of the seventh extended joint test work group connection interface 127 through the first multiplexer 13 The input data bit TDI_7; and the first test data input pin TDI are electrically connected to the second test data input pin TDI_8 of the eighth extended joint test work group connection interface 128 through the first multiplexer 13.

The first test data output pin TDO is electrically connected to the second test data output pin TDO_1 of the first extended joint test work group connection interface 121 through the second multiplexer 14; the first test data output pin TDO is transmitted through the first test data output pin TDO The second multiplexer 14 is electrically connected to the second test data output pin TDO_2 of the second extended joint test work group connection interface 122; the first test data output pin TDO is electrically connected to the second multiplexer 14 The third test data output pin TDO_3 of the joint test work group connection interface 123 is extended; the first test data output pin TDO is electrically connected to the fourth extended joint test work group connection interface 124 through the second multiplexer 14 The second test data output pin TDO_4; the first test data output pin TDO is electrically connected to the second test data output pin TDO_5 of the fifth extended joint test work group connection interface 125 through the second multiplexer 14; The first test data output pin TDO is electrically connected to the second test data output pin TDO_6 of the sixth extended joint test work group connection interface 126 through the second multiplexer 14; the first test data is input. The pin TDO is electrically connected to the second test data output pin TDO_7 of the seventh extended joint test work group connection interface 127 through the second multiplexer 14; and the first test data output pin TDO is transmitted through the second multiplexer 14 is electrically connected to the second test data output pin TDO_8 of the eighth extended joint test work group connection interface 128.

The second test data output pin TDO_1 of the first extended joint test work group connection interface 121 is electrically connected to the second test data input pin TDI_2 of the second extended joint test work group connection interface 122 through the first protection resistor 151. .

The second test data output pin TDO_2 of the second extended joint test work group connection interface 122 is electrically connected to the second test data input pin TDI_3 of the third extended joint test work group connection interface 123 through the second protection resistor 152. .

The second test data output pin TDO_3 of the third extended joint test work group connection interface 123 is electrically connected to the second test data input pin TDI_4 of the fourth extended joint test work group connection interface 124 through the third protection resistor 153. .

The second test data output pin TDO_4 of the fourth extended joint test work group connection interface 124 is electrically connected to the second test data input pin TDI_5 of the fifth extended joint test work group connection interface 125 through the fourth protection resistor 154. .

The second test data output pin TDO_5 of the fifth extended joint test work group connection interface 125 is electrically connected to the second test data input pin TDI_6 of the sixth extended joint test work group connection interface 126 through the fifth protection resistor 155. .

The second test data output pin TDO_6 of the sixth extended joint test work group connection interface 126 is electrically connected to the second test data input pin TDI_7 of the seventh extended joint test work group connection interface 127 through the sixth protection resistor 156. .

The second test data output pin TDO_7 of the seventh extended joint test work group connection interface 127 is electrically connected to the second test data input pin TDI_8 of the eighth extended joint test work group connection interface 128 through the seventh protection resistor 157. .

Therefore, the first extended joint test work group connection interface 121 to the eighth extended joint test work group connection interface 128 form a series connection, and the first protection resistance 151 to the seventh protection resistance 157 have a resistance value of 10 ohms to 100 ohms is for illustrative purposes only and is not intended to limit the scope of application of the present invention.

Next, please refer to FIG. 3, and FIG. 3 is a schematic diagram showing the connection of the test clock pin circuit of the expansion board provided with the extended joint test working group interface.

The first test clock pin TCK is electrically connected to the second test clock pin TCK_1 to the eighth extended joint test work group connection interface 128 of the first extended joint test working group connection interface 121 through the first buffer 16 respectively. The second test clock pin is TCK_8.

The first test clock pin TCK and the first buffer 16 respectively pass through the first matching resistor 171, the first matching resistor 172, the first matching resistor 173, the first matching resistor 174, the first matching resistor 175, and the first The matching resistor 176, the first matching resistor 177 and the first matching resistor 178 are electrically connected, the first matching resistor 171, the first matching resistor 172, the first matching resistor 173, the first matching resistor 174, the first matching resistor 175, The first matching resistor 176, the first matching resistor 177, and the first matching resistor 178 have a resistance value of 50 ohms.

The first buffer 16 and the second test clock pin TCK_1 of the first extended joint test working group connection interface 121 are respectively electrically connected through the second matching resistor 181; the first buffer 16 and the second expansion joint test work The second test clock pin TCK_2 of the group connection interface 122 is electrically connected through the second matching resistor 182; the second buffer 16 and the third extended joint test work group connection interface 123 are connected to the second test clock pin. The TCK_3 is electrically connected to the second matching resistor 183 through the second matching resistor 183. The second buffer 16 is electrically connected to the second test resistor pin TCK_4 of the fourth extended joint test working group connection interface 124. The first buffer 16 is electrically connected to the second test clock pin TCK_5 of the fifth extended joint test working group connection interface 125 through the second matching resistor 185; the first buffer 16 is combined with the sixth expansion. The second test clock pin TCK_6 of the test work group connection interface 126 is electrically connected through the second matching resistor 186 respectively; the first buffer 16 and the seventh extended joint test work group A second interface 127 connected to the test clock The pins TCK_7 are respectively electrically connected through the second matching resistor 187; and the second matching resistor is respectively passed between the first buffer 16 and the second test clock pin TCK_8 of the eighth extended joint test working group connection interface 128. 188 is electrically connected, the second matching resistor 181, the second matching resistor 182, the second matching resistor 183, the second matching resistor 184, the second matching resistor 185, the second matching resistor 186, the second matching resistor 187, and the second The resistance of the matching resistor 188 is 100 ohms.

The first matching resistor 171, the first matching resistor 172, the first matching resistor 173, the first matching resistor 174, the first matching resistor 175, the first matching resistor 176, the first matching resistor 177, and the first matching resistor 178 are The second matching resistor 181, the second matching resistor 182, the second matching resistor 183, the second matching resistor 184, the second matching resistor 185, the second matching resistor 186, the second matching resistor 187, and the second matching resistor 188 can be improved. The stability of the signal transmission.

The first buffer 16 further has a second test clock pin TCK_1 to the eighth expansion joint test work for simultaneously, selecting or single enabling and disabling the first extended joint test work group connection interface 121. The control function of the second test clock pin TCK_8 of the group connection interface 128.

Specifically, the first buffer 16 can only enable the second test clock pin TCK_1 of the first extended joint test work group connection interface 121, and the first buffer 16 can simultaneously disable the second extended joint test work group. The second test clock pin TCK_2 of the group connection interface 122 to the second test clock pin TCK_8 of the eighth extension joint test working group connection interface 128 is merely illustrative, and the application of the present invention is not limited thereto. category.

Specifically, the first buffer 16 can select the second test clock pin TCK_1 that enables the first extended joint test work group connection interface 121 and the second test clock pin of the third extended joint test work group connection interface 123. Bit TCK_3, and the first buffer 16 can simultaneously disable the second Expanding the second test clock pin TCK_2 of the joint test work group connection interface 122, the second test clock pin TCK_4 of the fourth extended joint test work group connection interface 124 to the eighth extended joint test work group connection interface 128 The second test clock pin TCK_8 is merely illustrative here and is not intended to limit the scope of application of the present invention.

Next, please refer to FIG. 4, and FIG. 4 is a schematic diagram showing the connection of the test mode selection pin circuit of the expansion circuit board of the extended joint test work group interface.

The first test mode selection pin TMS is electrically connected to the second test mode selection pin TMS_1 of the first extended joint test work group connection interface 121 through the second buffer 19; the first test mode selection pin TMS is transmitted through the second The buffer 19 is electrically connected to the second test mode selection pin TMS_2 of the second extended joint test working group connection interface 122; the first test mode selection pin TMS is electrically connected to the third extended joint through the second buffer 19 Testing the second test mode selection pin TMS_3 of the work group connection interface 123; the first test mode selection pin TMS is electrically connected to the second test of the fourth extended joint test work group connection interface 124 through the second buffer 19 The mode selection pin TMS_4; the first test mode selection pin TMS is electrically connected to the second test mode selection pin TMS_5 of the fifth extended joint test work group connection interface 125 through the second buffer 19; the first test mode selection The pin TMS is electrically connected to the second test mode selection pin TMS_6 of the sixth extended joint test working group connection interface 126 through the second buffer 19; the first test mode is selected. The pin TMS is electrically connected to the second test mode selection pin TMS_7 of the seventh extended joint test working group connection interface 127 through the second buffer 19; and the first test mode selection pin TMS is electrically transmitted through the second buffer 19. The second test mode selection pin TMS_8 is connected to the eighth extended joint test work group connection interface 128.

Next, please refer to FIG. 5, which is a schematic diagram showing the connection between the expansion board and the test access controller of the expansion board of the extended joint test work group interface according to the present invention.

The first test data input pin TDI, the first test data output pin TDO, the first test clock pin TCK, and the first test in the joint test work group connection interface 11 of the joint test work group expansion board 10 The second test data input pin TDI_1, the second test data output pin TDO_1, the second test clock pin TCK_1, and the second test mode selection TMS_1 in the mode selection pin TMS and the first extended joint test work group connection interface 121 The electrical connection configuration of the second test data input pin TDI_8, the second test data output pin TDO_8, the second test clock pin TCK_8, and the second test mode selection TMS_8 in the eighth extended joint test work group connection interface 128 .

The input of the control signal can be performed through the control input/output pin 22 of the test access controller 20, and the test access port 21 of the controller 20 is accessed through the test to the first multiplexer 13 and the second multiplexer. The first buffer 16 and the second buffer 19 are respectively controlled to select the first extended joint test work group connection interface 121 to the eighth extended joint test work group connection interface 128 to be controlled. Various tests for the joint test work group.

In summary, it can be seen that the difference between the present invention and the prior art is that the first test data input pin is electrically connected to the second test data input of each extended joint test work group connection interface through the first multiplexer. The first test data output pin is electrically connected to the second test data output pin of each extended joint test work group connection interface through the second multiplexer, and each extended joint test work group connection interface The second test data output pin is electrically connected to the second test data input pin of the expansion joint test work group connection interface through the protection resistor The first test clock pin is electrically connected to the second test clock pin of the extended joint test work group connection interface through the first buffer, and the first test mode select pin is electrically transmitted through the second buffer. a second test mode selection pin connected to the expansion joint test work group connection interface, for performing the first multiplexer, the second multiplexer, the first buffer, and the second buffer through the test access controller Controls to select the extended joint test workgroup connection interface that needs to be controlled for subsequent testing of the joint test workgroup.

By means of this technical means, the existing test access controller provided by the prior art can provide a limited number of test accesses and cannot satisfy a large number of tests or meet a large number of tests but requires high test costs, thereby providing Extend the joint test workgroup connection interface to improve the technical effectiveness of the joint test workgroup testing needs.

While the embodiments of the present invention have been described above, the above description is not intended to limit the scope of the invention. Any changes in the form and details of the embodiments may be made without departing from the spirit and scope of the invention. The scope of the invention is to be determined by the scope of the appended claims.

10‧‧‧Joint Test Workgroup Expansion Board

11‧‧‧Joint test workgroup connection interface

20‧‧‧Test access controller

21‧‧‧Test access

22‧‧‧Control input and output pins

Claims (9)

An expansion circuit board providing an extended joint test work group interface, comprising: a Joint Test Action Group (JTAG) expansion circuit board, the joint test work group expansion circuit board further comprises: a joint The test group connection interface is electrically connected to a test access port of a test access port (TAP) controller, and the joint test work group connection interface further includes a first test data Input (Test Data Input, TDI) pin, a first Test Data Output (TDO) pin, a first Test Clock (TCK) pin, and a first test mode selection (Test Mode) Select, TMS) pin; and eight extended joint test work group connection interface, each extended joint test work group connection interface further includes a second test data input pin, a second test data output pin, a first a second test clock pin and a second test mode selection; wherein the first test data input pin is respectively transmitted through a first multiplexer (Multiplexer) Electrically connecting to the second test data input pin of each extended joint test work group connection interface; the first test data output pin is electrically connected to each expansion joint through a second multiplexer Testing the second test data output pin of the work group connection interface; the second test data output pin of each extended joint test work group connection interface is coupled to another extended joint test work group through a protection resistor The second test data input pin of the connection interface is electrically connected, so that each extended joint test work group connection interface forms a serial connection; the first test clock pin is respectively transmitted through a first buffer (Buffer) Electrically connecting to the second test clock pin of the extended joint test work group connection interface; and the first test mode selection pin is electrically connected to the extended joint test through a second buffer The second test mode selection pin of the work group connection interface. An expansion board for providing an extended joint test working group interface according to claim 1, wherein the first buffer and the first test clock pin are electrically connected through a first matching resistor. . An expansion circuit board providing an extended joint test working group interface as described in claim 2, wherein the first matching resistor has a resistance value of 50 ohms. An expansion board for providing an extended joint test working group interface according to claim 1, wherein the first buffer and the second test clock pin are electrically connected through a second matching resistor. . An expansion board providing an extended joint test work group interface as described in claim 4, wherein the second matching resistor has a resistance value of 100 ohms. An expansion circuit board for providing an extended joint test work group interface according to claim 1, wherein the first buffer is provided with simultaneous, selective or single enable and disable. The second test clock pin control function. An expansion board for providing an extended joint test work group interface as described in claim 1, wherein the protection resistor has a resistance value of 10 ohms to 100 ohms. An expansion board for providing an extended joint test work group interface as described in claim 1, wherein the test access controller further includes a control input/output pin. An expansion circuit board for providing an extended joint test working group interface according to claim 8, wherein the control input/output pin is used to control the first multiplexer, the second multiplexer, The first buffer and the second buffer are selected to select the extended joint test work group connection interface that needs to be controlled.