CN112019404A - Method and device for automatically testing FC-AE-1553 communication protocol chip - Google Patents
Method and device for automatically testing FC-AE-1553 communication protocol chip Download PDFInfo
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- CN112019404A CN112019404A CN202010878613.0A CN202010878613A CN112019404A CN 112019404 A CN112019404 A CN 112019404A CN 202010878613 A CN202010878613 A CN 202010878613A CN 112019404 A CN112019404 A CN 112019404A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/50—Testing arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
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Abstract
The embodiment of the disclosure discloses a method and a device for automatically testing an FC-AE-1553 communication protocol chip, relating to the field of testing; wherein the method comprises the following steps: setting a board card role and generating configuration information; selecting a partition, and generating a task file in a designated folder; screening the task file according to the received keyword; loading the task files obtained through screening into a queue to construct a test scene; and sending the test scene and the configuration information to an automatic service module, and automatically generating a test report and a log report.
Description
Technical Field
The disclosure relates to the field of testing, in particular to a method and a device for automatically testing an FC-AE-1553 communication protocol chip.
Background
In the prior art, an optical fiber communication protocol chip is a monolithic digital integrated circuit, is suitable for all Network topologies, has multiple working modes, can be configured as a Network Controller (hereinafter referred to as NC node, Network Controller), a Network Terminal (hereinafter referred to as NT node, Network Terminal), a Network Monitor (hereinafter referred to as NM node, Network Monitor), a Network Terminal and Monitor integrated body (NT + NM), a Matching Terminal (hereinafter referred to as TM node, Matching Terminal) and a Serdes mode according to an internal register, and realizes a high-reliability strong real-time data transmission function.
Generally, for testing a specific chip such as an optical fiber communication protocol chip, corresponding test adaptation equipment or a test environment needs to be developed, and the defects of single purpose (non-universal), long development period and high cost exist; moreover, the test adapting device generally tests only a certain single performance (such as stability) of the chip, and the chip with multiple working modes and/or roles cannot be comprehensively tested, so that the accuracy is not high; meanwhile, in the prior art, a large amount of manual work is needed for carrying out relatively complex test operation on the chip, time and labor are wasted, and error risks exist in manual instrument debugging and operation, so that the test accuracy and efficiency are low, and the test quality and results are influenced.
Disclosure of Invention
Aiming at the technical problems in the prior art, the embodiment of the disclosure provides an automatic testing method and device for an FC-AE-1553 communication protocol chip, so as to solve the problems that the chip cannot be tested in all directions, manual operation is required, time and labor are wasted, and the testing accuracy and efficiency are low in the prior art.
The first aspect of the embodiment of the present disclosure provides a method for automatically testing an FC-AE-1553 communication protocol chip, including:
setting a board card role and generating configuration information;
selecting a partition, and generating a task file in a designated folder;
screening the task file according to the received keyword;
loading the task files obtained through screening into a queue to construct a test scene;
and sending the test scene and the configuration information to an automatic service module, and automatically generating a test report and a log report.
In some embodiments, the board role is specifically NC or NT.
In some embodiments, the method further comprises: and manually adding and/or deleting the task file in the queue.
In some embodiments, the method further comprises: and generating the task files in batches in a specified folder.
In some embodiments, the method further comprises: and storing the test result and the log report to a specified folder, and managing.
In some embodiments, the method further comprises: and displaying the progress and the state of the test in real time.
A second aspect of the embodiments of the present disclosure provides an apparatus for automatically testing an FC-AE-1553 communication protocol chip, including:
the board card role configuration module is used for setting board card roles and generating configuration information;
the task file generation module is used for selecting the partitions and generating task files in the designated folders;
the screening module is used for screening the task file according to the received keyword;
the loading module is used for loading the task files obtained through screening into a queue and constructing a test scene;
and the test result generation module is used for issuing the test scene and the configuration information to the automatic service module and automatically generating a test result and a log report.
In some embodiments, the load module is further to: and manually adding and/or deleting the task file in the queue.
In some embodiments, the apparatus further comprises: and the log management module is used for storing the test result and the log report to a specified folder and managing the test result and the log report.
In some embodiments, the apparatus further comprises: and the state display module is used for displaying the test progress and state in real time.
A third aspect of the embodiments of the present disclosure provides an electronic device, including:
a memory and one or more processors;
wherein the memory is communicatively coupled to the one or more processors, and the memory stores instructions executable by the one or more processors, and when the instructions are executed by the one or more processors, the electronic device is configured to implement the method according to the foregoing embodiments.
A fourth aspect of the embodiments of the present disclosure provides a computer-readable storage medium having stored thereon computer-executable instructions, which, when executed by a computing device, may be used to implement the method according to the foregoing embodiments.
A fifth aspect of embodiments of the present disclosure provides a computer program product comprising a computer program stored on a computer readable storage medium, the computer program comprising program instructions which, when executed by a computer, are operable to implement a method as in the preceding embodiments.
In the embodiment of the disclosure, by setting the board card roles, the method and the device can be suitable for each role of the FC-AE-1553 communication protocol system, can construct different test environments, can perform corresponding tests for different characteristics, reduce manual operations on software and instruments, improve the reliability of test results, reduce the error rate caused by manual operations, and automatically generate test reports and log reports, thereby realizing automatic all-function tests of chips, having high test efficiency, and reducing the workload of testers.
Drawings
The features and advantages of the present disclosure will be more clearly understood by reference to the accompanying drawings, which are illustrative and not to be construed as limiting the disclosure in any way, and in which:
FIG. 1 is a system diagram illustrating an example of an FC-AE-1553 communication protocol chip automation test, according to some embodiments of the present disclosure;
FIG. 2 is a flow diagram of a method for automated testing of an FC-AE-1553 communication protocol chip, according to some embodiments of the present disclosure;
FIG. 3 is a test software interface design schematic shown in accordance with some embodiments of the present disclosure;
FIGS. 4 and 5 are exemplary diagrams of automated test reports shown in accordance with some embodiments of the present disclosure;
FIG. 6 is a schematic diagram of an apparatus for automated testing of a FC-AE-1553 communication protocol chip, according to some embodiments of the present disclosure;
fig. 7 is a schematic structural diagram of an electronic device according to some embodiments of the present disclosure.
Detailed Description
In the following detailed description, numerous specific details of the disclosure are set forth by way of examples in order to provide a thorough understanding of the relevant disclosure. However, it will be apparent to one of ordinary skill in the art that the present disclosure may be practiced without these specific details. It should be understood that the use of the terms "system," "apparatus," "unit" and/or "module" in this disclosure is a method for distinguishing between different components, elements, portions or assemblies at different levels of sequence. However, these terms may be replaced by other expressions if they can achieve the same purpose.
It will be understood that when a device, unit or module is referred to as being "on" … … "," connected to "or" coupled to "another device, unit or module, it can be directly on, connected or coupled to or in communication with the other device, unit or module, or intervening devices, units or modules may be present, unless the context clearly dictates otherwise. For example, as used in this disclosure, the term "and/or" includes any and all combinations of one or more of the associated listed items.
The terminology used in the present disclosure is for the purpose of describing particular embodiments only and is not intended to limit the scope of the present disclosure. As used in the specification and claims of this disclosure, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are inclusive in the plural, unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" are intended to cover only the explicitly identified features, integers, steps, operations, elements, and/or components, but not to constitute an exclusive list of such features, integers, steps, operations, elements, and/or components.
These and other features and characteristics of the present disclosure, as well as the methods of operation and functions of the related elements of structure and the combination of parts and economies of manufacture, will be better understood by reference to the following description and drawings, which form a part of this specification. It is to be expressly understood, however, that the drawings are for the purpose of illustration and description only and are not intended as a definition of the limits of the disclosure. It will be understood that the figures are not drawn to scale.
Various block diagrams are used in this disclosure to illustrate various variations of embodiments according to the disclosure. It should be understood that the foregoing and following structures are not intended to limit the present disclosure. The protection scope of the present disclosure is subject to the claims.
In the prior art, an optical fiber communication protocol chip is a monolithic digital integrated circuit, is suitable for all Network topologies, has multiple working modes, can be configured as a Network Controller (hereinafter referred to as NC node, Network Controller), a Network Terminal (hereinafter referred to as NT node, Network Terminal), a Network Monitor (hereinafter referred to as NM node, Network Monitor), a Network Terminal and Monitor integrated body (NT + NM), a Matching Terminal (hereinafter referred to as TM node, Matching Terminal) and a Serdes mode according to an internal register, and realizes a high-reliability strong real-time data transmission function.
Generally, for testing a specific chip such as an optical fiber communication protocol chip, corresponding test adaptation equipment or a test environment needs to be developed, and the defects of single purpose (non-universal), long development period and high cost exist; moreover, the test adapting device generally tests only a certain single performance (such as stability) of the chip, and the chip with multiple working modes and/or roles cannot be comprehensively tested, so that the accuracy is not high; meanwhile, in the prior art, a large amount of manual work is needed for carrying out relatively complex test operation on the chip, time and labor are wasted, and error risks exist in manual instrument debugging and operation, so that the test accuracy and efficiency are low, and the test quality and results are influenced.
In order to solve the problems existing in the prior art, the embodiment of the disclosure discloses a system for automatically testing an FC-AE-1553 communication protocol chip, as shown in fig. 1; specifically, after receiving an instruction started by a user, the application program starts role configuration, generates corresponding configuration information and sends the configuration information to the application module; the application module constructs a test scene and sends the constructed test scene and the configuration information to the service module; the service module generates an analysis result and sends the analysis result to the application module, and the application module generates a log and sends the log to an application program to display application information for a user.
The automatic testing system is adaptive to each role in the FC-AE-1553 system, a task file is simply, conveniently and rapidly generated in batches, a high-efficiency filtering system is adopted, various testing environments can be easily constructed, a start-stop mechanism with rapid response is realized, service data can be rapidly analyzed, the total number of protocol frames and error information in the testing process can be counted, and a detailed log report can be generated; meanwhile, comprehensive stability test can be carried out by simulating a real use scene, and the comprehensive performance of the chip during long-time operation is verified, which is different from the condition that the general stability test can only test the single performance of the chip.
The embodiment of the disclosure also discloses a method for automatically testing an FC-AE-1553 communication protocol chip, as shown in fig. 2, specifically comprising:
s101, setting a board card role, and generating configuration information;
s102, selecting a partition, and generating a task file in a designated folder;
s103, screening the task file according to the received keywords;
s104, loading the task files obtained through screening into a queue to construct a test scene;
and S105, issuing the test scene and the configuration information to an automatic service module, and automatically generating a test report and a log report.
In some embodiments, the board role is specifically NC or NT.
In some embodiments, the method further comprises: and manually adding and/or deleting the task file in the queue.
In some embodiments, the method further comprises: and generating the task files in batches in a specified folder.
In some embodiments, the method further comprises: and storing the test result and the log report to a specified folder, and managing.
In some embodiments, the method further comprises: and displaying the progress and the state of the test in real time.
The method can be applied to software for automatic testing, the interface design schematic diagram of the software is shown in fig. 3, and the specific operation flow comprises the following steps: the method comprises six processes of board card role configuration, task file batch generation, task file screening, start-stop script, log management and state display.
a) Configuring board roles
Aiming at different roles in the FC-AE-1553 system, software provides a role configuration function, clicks 'role', pops up a configuration role dialog box, configures the board role as NC or NT, clicks 'confirm and start', completes role configuration and generates role configuration information.
b) Generating task files
The software configuration interface is displayed as a plurality of partition modules, different task files can be generated in a designated folder by checking or filling different options in each partition and then clicking a 'generation' button.
Some of the partitions can be provided with batch generation task files, the batch generation task files are filled in a positive integer form of x-xx, and the batch generation task files in a designated folder can be generated by clicking a 'generation' button.
Specifically, the batch generation task file format is as follows:
c) screening task files
When a test scene is constructed, an interface screening button is clicked, a screening dialog box is popped up, a keyword is input by a user, the file name in a specified folder can be searched according to the keyword, a task file is placed in a loading queue, and the task file can be manually added and deleted. The built test scenario may be exported for later continued use. Meanwhile, the constructed test scene can be loaded for testing. And if all task files in the specified folder need to be loaded, checking the full selection at the loading queue.
d) Start-stop script
Clicking a 'sending down' button on a software interface, and sending the constructed test scene to an automatic operation software service module; and after receiving the message, the service module automatically loads the message and displays the operation progress in the status bar. And clicking a stop button to stop the automatic operation software service module.
e) Log management
And the software issues test scene configuration and starting information, after the processing is finished, a result analysis and log report is automatically generated and stored in a specified folder, a log button on a software interface is clicked, the specified folder is opened, and the automatic test information can be read. The format of the automated test report is shown in fig. 4 and 5, wherein the message operation result only lists the messages with errors.
f) Status display
The software interface state display column can display: software information, board card role information, start and stop information, running schedule and the like.
The embodiment of the present disclosure further discloses an apparatus 600 for automatically testing an FC-AE-1553 communication protocol chip, as shown in fig. 6, specifically including:
the board role configuration module 601 is used for setting board roles and generating configuration information;
a task file generation module 602, configured to select a partition and generate a task file in a specified folder;
a screening module 603, configured to screen the task file according to the received keyword;
a loading module 604, configured to load the task file obtained through screening into a queue, and construct a test scenario;
and the test result generating module 605 is configured to issue the test scenario and the configuration information to the automation service module, and automatically generate a test result and a log report.
In some embodiments, the load module is further to: and manually adding and/or deleting the task file in the queue.
In some embodiments, the apparatus further comprises: and the log management module is used for storing the test result and the log report to a specified folder and managing the test result and the log report.
In some embodiments, the apparatus further comprises: and the state display module is used for displaying the test progress and state in real time.
According to the method and the device for automatically testing the FC-AE-1553 communication protocol chip, disclosed by the embodiment of the disclosure, multiple devices can be adapted through high-integration software, different testing environments can be constructed, corresponding tests can be carried out aiming at different characteristics, the manual operation on software and instruments is reduced, the reliability of a testing result is improved, and the error rate caused by the manual operation is reduced; meanwhile, the scheme can adapt to various devices and various working modes, so that the efficiency of test work is improved, and the development time of the whole project is reduced.
In the embodiment of the present disclosure, a schematic diagram of an electronic device is also disclosed, as shown in fig. 7. Wherein, this electronic equipment 700 includes:
wherein the memory 730 is communicatively coupled to the one or more processors 710, and instructions 732 that are executable by the one or more processors are stored in the memory 730, and the instructions 732 are executable by the one or more processors 710 to cause the one or more processors 710 to perform the methods of the embodiments of the present application.
In particular, processor 710 and memory 730 may be connected by a bus or other means, such as bus 740 in FIG. 7. Processor 710 may be a Central Processing Unit (CPU). The Processor 710 may also be other general purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components, or any combination thereof.
The memory 730, as a non-transitory computer readable storage medium, may be used for storing non-transitory software programs, non-transitory computer executable programs, and modules, such as the cascaded progressive network in the embodiments of the present application. The processor 710 performs various functional applications of the processor and data processing by executing non-transitory software programs, instructions, and modules 732 stored in the memory 730.
The memory 730 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created by the processor 710, and the like. Further, the memory 730 may include high speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device. In some embodiments, memory 730 optionally includes memory located remotely from processor 710, and such remote memory may be connected to processor 710 via a network, such as through communications interface 720. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
An embodiment of the present application further provides a computer-readable storage medium, in which computer-executable instructions are stored, and the computer-executable instructions are executed to perform the method in the foregoing embodiment of the present application.
The foregoing computer-readable storage media include physical volatile and nonvolatile, removable and non-removable media implemented in any manner or technology for storage of information such as computer-readable instructions, data structures, program modules or other data. The computer-readable storage medium specifically includes, but is not limited to, a USB flash drive, a removable hard drive, a Read-Only Memory (ROM), a Random Access Memory (RAM), an erasable programmable Read-Only Memory (EPROM), an electrically erasable programmable Read-Only Memory (EEPROM), flash Memory or other solid state Memory technology, a CD-ROM, a Digital Versatile Disk (DVD), an HD-DVD, a Blue-Ray or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer.
While the subject matter described herein is provided in the general context of execution in conjunction with the execution of an operating system and application programs on a computer system, those skilled in the art will recognize that other implementations may also be performed in combination with other types of program modules. Generally, program modules include routines, programs, components, data structures, and other types of structures that perform particular tasks or implement particular abstract data types. Those skilled in the art will appreciate that the subject matter described herein may be practiced with other computer system configurations, including hand-held devices, multiprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers, and the like, as well as distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote memory storage devices.
Those of ordinary skill in the art will appreciate that the various illustrative elements and method steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to perform all or part of the steps of the method according to the embodiments of the present application.
In summary, the present disclosure provides a method and an apparatus for automatically testing a FC-AE-1553 communication protocol chip, an electronic device and a computer-readable storage medium thereof. By setting the board card roles, the method is suitable for all roles of an FC-AE-1553 communication protocol system, and can automatically generate a test report and a log report while easily constructing various test environments, thereby realizing automatic all function tests of the chip, having high test efficiency and reducing the workload of testers.
It is to be understood that the above-described specific embodiments of the present disclosure are merely illustrative of or illustrative of the principles of the present disclosure and are not to be construed as limiting the present disclosure. Accordingly, any modification, equivalent replacement, improvement or the like made without departing from the spirit and scope of the present disclosure should be included in the protection scope of the present disclosure. Further, it is intended that the following claims cover all such variations and modifications that fall within the scope and bounds of the appended claims, or equivalents of such scope and bounds.
Claims (10)
1. A method for automatically testing FC-AE-1553 communication protocol chips is characterized by comprising the following steps:
setting a board card role and generating configuration information;
selecting a partition, and generating a task file in a designated folder;
screening the task file according to the received keyword;
loading the task files obtained through screening into a queue to construct a test scene;
and sending the test scene and the configuration information to an automatic service module, and automatically generating a test report and a log report.
2. The method of claim 1, wherein the board role is specifically NC or NT.
3. The method of claim 1, further comprising: and manually adding and/or deleting the task file in the queue.
4. The method of claim 1, further comprising: and generating the task files in batches in a specified folder.
5. The method of claim 1, further comprising: and storing the test result and the log report to a specified folder, and managing.
6. The method of claim 1, further comprising: and displaying the progress and the state of the test in real time.
7. An automatic test device for FC-AE-1553 communication protocol chips is characterized by comprising the following components:
the board card role configuration module is used for setting board card roles and generating configuration information;
the task file generation module is used for selecting the partitions and generating task files in the designated folders;
the screening module is used for screening the task file according to the received keyword;
the loading module is used for loading the task files obtained through screening into a queue and constructing a test scene;
and the test result generation module is used for issuing the test scene and the configuration information to the automatic service module and automatically generating a test result and a log report.
8. The apparatus of claim 7, wherein the loading module is further configured to: and manually adding and/or deleting the task file in the queue.
9. The apparatus of claim 7, further comprising: and the log management module is used for storing the test result and the log report to a specified folder and managing the test result and the log report.
10. The apparatus of claim 7, further comprising: and the state display module is used for displaying the test progress and state in real time.
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