CN111596203A - Chip testing device, platform and method - Google Patents
Chip testing device, platform and method Download PDFInfo
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- G—PHYSICS
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31704—Design for test; Design verification
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318307—Generation of test inputs, e.g. test vectors, patterns or sequences computer-aided, e.g. automatic test program generator [ATPG], program translations, test program debugging
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
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Abstract
The invention discloses a chip testing device, a platform and a method. Wherein, the platform includes: the device comprises a control unit, an equipment unit, a switching unit, a burning unit and a report unit; according to the chip test evaluation method, a large number of real machine test services of various chips are summarized, a universal list command is extracted and established, the universal list command is analyzed into a test function through a control unit of the system, an operation instruction is sent to other units to schedule a test action, and a report is generated in the synchronization of system operation, so that the whole automation of chip test is realized, the labor cost is saved, the operation pressure of testers is reduced, and the efficiency and the quality of chip test are improved.
Description
Technical Field
The invention relates to the field of chip testing, in particular to a chip testing device, a chip testing platform and a chip testing method.
Background
The functional and performance test evaluation of chip hardware refers to the test of functional correctness and performance index aiming at the designed hardware function after tape-out due to individual difference and design imperfection. The test needs to be performed on a plurality of chips for a plurality of times to ensure the accuracy of the test.
The software test of the chip means that after the driver software and the system software matched with the chip are developed, the correctness of each function needs to be tested. With the continuous modification and upgrade of software versions, repeated tests are required to ensure the accuracy of the software versions.
At present, in the process of universal chip testing, because the operation of a testing and compiling tool, the configuration and connection of equipment, the establishment of an environment, the comparison of data and the judgment of a result all need manual participation, and moreover, the requirements of chip testing evaluation work on the instrument use and debugging capability of practitioners are higher, the chip testing time is long, the efficiency is low, the result is unstable, and the progress and the quality of the whole chip research and development work are influenced.
Disclosure of Invention
The invention provides a chip testing device, a platform and a method, which aim to overcome the technical problems.
The chip testing device of the invention comprises:
a control unit and an interface unit; the interface unit includes: the device comprises a switching module, a debugging module and an equipment unit instruction module;
the control unit is used for calling a test item name, a test function and a test item flow corresponding to the name of the tested chip in a test case list according to the name of the tested chip, wherein the test function comprises a plurality of functions of an equipment unit, and the plurality of functions of the equipment unit correspond to a plurality of models of the equipment unit;
sending a connection instruction to the interface unit according to the test item flow of the case list, and sending a connection establishment instruction to a report unit; sending a test instruction to the interface unit according to the name of the test item of the case list; sending parameter configuration and opening/closing instructions of an equipment unit to the interface unit according to the test equipment and the test function corresponding to the test item of the case list, and sending the parameter configuration and the opening/closing instructions to a report unit; reading the measurement reading of the equipment unit according to the test function in the case list, and sending the reading of the equipment unit to a report unit; judging whether the chip passes the test or not according to the reading of the equipment unit, and sending test judgment result information to a report unit;
the switching module receives the connection instruction sent by the control unit, and the switching module of the interface unit establishes connection with the equipment unit according to the connection instruction;
the debugging module is used for burning the test content corresponding to the test instruction to the tested chip according to the test instruction and sending the burning instruction to the report unit;
the equipment unit instruction module is used for receiving the equipment unit parameter configuration and opening/closing instructions sent by the control unit, controlling the equipment unit to be opened/closed, sending the parameter configuration and opening/closing instructions to the equipment unit, and sending the parameter configuration and opening/closing instructions to the report unit.
Further, the control unit is further specifically configured to:
determining a plurality of equipment units according to the test requirements, and determining equipment models corresponding to the equipment units according to the system environment configuration requirements;
determining an interface function according to a plurality of bottom layer functions corresponding to a certain model of any equipment unit;
determining a standard function of the equipment unit in a case list according to a plurality of interface functions corresponding to a plurality of models of the equipment unit;
establishing a case list according to the test content and the standard function;
the interface unit is further specifically configured to:
the interface unit splits the test function according to the test function to obtain a standard function corresponding to the equipment unit/the chip to be tested;
the interface unit splits the standard function according to the test equipment to obtain an interface function corresponding to the equipment unit/the chip to be tested;
and the interface unit sends the interface function to the equipment unit/chip to be tested.
Further, still include:
and the report unit is used for receiving the test content and the test result of the tested chip sent by the control unit in the test execution process and synchronously generating a report.
Further, the interface unit further includes:
and the cloud network interface module is used for providing hardware support and a network communication protocol required by network connection.
The invention also provides a chip test evaluation platform, which comprises:
the chip testing device and the equipment unit;
the equipment unit comprises a plurality of test equipment and power supply equipment, wherein the test equipment is used for testing parameters of a chip to be tested, the test equipment is used for receiving a test instruction sent by the control unit and measuring an output signal of the chip to be tested according to the test instruction, and the power supply equipment is used for receiving an opening/closing instruction sent by the control unit and opening/closing according to the opening/closing instruction.
The invention also provides a chip test evaluation method, which comprises the following steps:
the control unit calls a test item name, a test function and a test item flow corresponding to the name of the chip to be tested in a test case list according to the test item name, wherein the test function corresponds to a plurality of equipment units, the test function corresponds to a plurality of standard functions, and the standard functions correspond to interface functions of the equipment units;
the control unit sends a connection instruction to the interface unit according to the test item flow of the case list and sends a connection establishment instruction to a report unit;
the interface unit receives the connection instruction sent by the control unit, and a switching module of the interface unit establishes connection with the equipment unit according to the connection instruction;
the control unit sends a test instruction to the interface unit according to the name of the test item in the case list, and a debugging module of the interface unit burns test contents corresponding to the test instruction to a chip to be tested according to the test instruction and sends the burning instruction to a report unit;
the control unit sends the parameter configuration and opening/closing instruction of the equipment unit to the interface unit according to the test equipment and the test function corresponding to the test item of the case list, and sends the parameter configuration and opening/closing instruction to the report unit;
the equipment instruction module of the interface unit receives the parameter configuration and opening/closing instructions, sends the parameter configuration and opening/closing instructions to the equipment unit, and sends the parameter configuration and opening/closing instructions to the report unit;
the equipment unit receives the parameter configuration and the opening/closing instruction of the interface unit, performs parameter configuration and opening/closing according to the parameter configuration and the opening/closing instruction, and sends the parameter configuration and the opening/closing instruction to the report unit;
the control unit reads the measurement reading of the equipment unit according to the test function in the case list and sends the reading of the equipment unit to a report unit;
and the control unit judges whether the chip passes the test or not according to the reading of the equipment unit and sends the test judgment result information to the report unit.
Further, before the controlling unit calls the test item name, the test function, the test item flow and the test device corresponding to the test item corresponding to the name of the tested chip in the test case list according to the name of the tested chip, the method further includes:
determining a plurality of equipment units according to the test requirements, and determining equipment models corresponding to the equipment units according to the system environment configuration requirements;
determining an interface function according to a plurality of bottom layer functions corresponding to a certain model of any equipment unit;
determining a standard function of the equipment unit in a case list according to a plurality of interface functions corresponding to a plurality of models of the equipment unit;
establishing a case list according to the test content and the standard function;
further, the control unit sends a parameter configuration and an open/close instruction of the device unit to the interface unit according to the test device and the test function corresponding to the test item of the case list, and sends the parameter configuration and the open/close instruction to the report unit, including:
the interface unit splits the test function according to the test function to obtain a standard function corresponding to the equipment unit/the chip to be tested;
the interface unit splits the standard function according to the test equipment to obtain an interface function corresponding to the equipment unit/the chip to be tested;
and the interface unit sends the interface function to the equipment unit/chip to be tested.
Further, after the control unit judges whether the chip passes the test according to the reading of the device unit, the method further includes:
and the report unit synchronously generates a test report according to the test judgment result and the log information sent by the control unit.
According to the chip test evaluation method, a large number of real machine test services of various chips are summarized, a universal list command is extracted and established, the universal list command is analyzed into a test function through a control unit of the system, an operation instruction is sent to other units to schedule a test action, and a report is generated in the synchronization of system operation, so that the whole automation of chip test is realized, the labor cost is saved, the operation pressure of testers is reduced, and the efficiency and the quality of chip test are improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a chip testing apparatus according to the present invention;
FIG. 2 is a schematic view of another structure of the chip testing device of the present invention;
FIG. 3 is a diagram of the chip test platform architecture of the present invention;
FIG. 4 is a schematic diagram of a simulated mouse click event in the implementation of automatic burning according to the present invention;
FIG. 5 is a flow chart of a chip test evaluation method of the present invention;
FIG. 6 is a flowchart illustrating the execution of the chip test evaluation platform program according to the present invention;
FIG. 7 is a schematic illustration of a report of the present invention;
FIG. 8 is a diagram of the generalized interface action package for the basic operation of the pulse function arbitrary waveform generator test according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Firstly, a system unit realizes:
fig. 1 is a schematic structural diagram of a chip testing apparatus according to the present invention, and as shown in fig. 1, the apparatus of the present embodiment includes:
a control unit 101 and an interface unit 102; the interface unit includes: a switching module 103, a debugging module 104 and an equipment unit instruction module 105;
the control unit is used for calling a test item name, a test function, a test item flow and test equipment corresponding to the test item corresponding to the name of the tested chip in a test case list according to the name of the tested chip, wherein the test function comprises a plurality of functions of an equipment unit, and the plurality of functions of the equipment unit correspond to a plurality of models of the equipment unit; sending a connection instruction to the interface unit according to the test item flow of the case list, and sending a connection establishment instruction to a report unit; sending a test instruction to the interface unit according to the name of the test item of the case list; sending parameter configuration and opening/closing instructions of an equipment unit to the interface unit according to the test equipment and the test function corresponding to the test item of the case list, and sending the parameter configuration and the opening/closing instructions to a report unit; reading the measurement reading of the equipment unit according to the test function in the case list, and sending the reading of the equipment unit to a report unit; judging whether the chip passes the test or not according to the reading of the equipment unit, and sending test judgment result information to a report unit;
the switching module receives the connection instruction sent by the control unit, and the switching module of the interface unit establishes connection with the equipment unit according to the connection instruction;
the debugging module is used for burning the test content corresponding to the test instruction to the tested chip according to the test instruction and sending the burning instruction to the report unit;
the equipment unit instruction module is used for receiving the equipment unit parameter configuration and opening/closing instructions sent by the control unit, controlling the equipment unit to be opened/closed, sending the parameter configuration and opening/closing instructions to the equipment unit, and sending the parameter configuration and opening/closing instructions to the report unit.
Specifically, the chip testing device of the present embodiment includes a control unit and an interface unit, where the interface unit includes: the system interface, the middle layer conversion interface and the bottom layer interface;
the system interface is a software interface among the control unit, the switching module, the debugging module, the equipment unit instruction module, the communication module and the cloud network interface module;
the middle layer conversion interface is a software interface and a hardware interface among the interface unit, the equipment unit, the chip to be tested and the cloud network;
the bottom layer interface is an equipment unit instruction module, and bottom layer data connection between the interface unit and the equipment unit is realized.
Before the start of the test item, the control unit is further specifically configured to:
determining a plurality of equipment units according to the test requirements;
determining an interface function according to a plurality of bottom layer functions corresponding to a certain model of any equipment unit;
determining a standard function of the equipment unit in a case list according to a plurality of interface functions corresponding to a plurality of models of the equipment unit;
establishing a case list according to the test content and the standard function;
the concrete process of establishing the case list is as follows:
the chip has various types, complex working environment and large number of operating devices. It is difficult to extract a general control method from a large number of test items. The invention summarizes the general test item lists of various chips in different environments, thereby realizing the test evaluation items in various environments by the control method. As shown in table 1, the chip integrity test item table.
TABLE 1
The overall test evaluation items for different models of chips generally include: functional evaluation, input-output characteristic evaluation, ADC, MOSC, SOSC, PLL, HOCO, consumption current, DAC, TSN, VDC, VBAT, and Table 1 shows the overall test contents of chip functional evaluation, including: security, TIMER, RTC, DMA function evaluation.
Aiming at the test items, by analyzing the operation methods in manual test, task summary and hierarchy promotion are carried out, and a universal interface control instruction is extracted and established. This embodiment only takes the pulse function arbitrary waveform generator as an example to describe the method of raising the command.
As shown in fig. 8, according to the test requirements, several equipment units in the oscilloscope, the adjustable power supply, the multimeter and the waveform generator required for the test evaluation are selected. Fig. 8 lists basic operations when a waveform generator is used for testing, including 23 operation actions, and the 23 operation actions are packaged into 5 universal interface functions, and by calling the 5 interface functions, corresponding universal operation actions can be implemented by using multi-model device units. Interface functions which can correspond to a plurality of types of equipment units to execute specific test actions, such as: outputting the destination type sine wave, and lifting to the standard function of more upper computer executable operation, such as: OSCP _ inquiry _ OUTPUT _ TYPE query OUTPUT TYPE.
Through the steps, the case list can be established according to the test content and the standard function. Table 2 is a table of examples tested using case lists. The cycle number of this example is 100.
TABLE 2
As shown in table 2 and fig. 6, the control unit sends the parameter configuration and on/off instruction of the device unit to the interface unit according to the test device and the test function corresponding to the flows (4) to (6) in the test item 001 of the case list, and sends the parameter configuration and on/off instruction to the report unit;
the device command module of the interface unit receives parameter configuration (SRC1,10.00,50,3,1,0), (SRC1,10.00,50,3,1,0) commands, and sends the parameter configuration and on/off commands to the device unit and the report unit; the equipment unit receives the parameter configuration and the opening/closing instruction, performs parameter configuration and opening/closing according to the parameter configuration and the opening/closing instruction, and sends the parameter configuration and the opening/closing instruction to the report unit; the control unit reads the measurement reading of the equipment unit according to the test function in the case list and sends the reading of the equipment unit to the report unit; the control unit judges whether the chip passes the test or not according to the reading of the equipment unit and sends the test judgment result information to the report unit. Controlling the equipment unit to be started, reading the test items one by one, and if the content of the test items is not empty, continuing to execute the following steps; if the content of the test item is empty, the test procedure terminates.
The interface unit is further specifically configured to: the interface unit splits the test function according to the test function to obtain a standard function corresponding to the equipment unit/the chip to be tested; the interface unit splits the standard function according to the test equipment to obtain an interface function corresponding to the equipment unit/the chip to be tested; and the interface unit sends the interface function to the equipment unit/chip to be tested.
In addition to the above functions, as shown in fig. 2, the interface unit of the apparatus of this embodiment further includes: and the cloud network interface module 106 is configured to provide hardware support and a network communication protocol required by network connection. The cloud network interface module can realize the remote control of the storage and test functions of the tested report.
Particularly, the cloud network interface module is arranged, so that the man-machine interactivity and the easy-to-detect performance in the test process can be improved, files and data are downloaded and uploaded according to test requirements, and the test working efficiency is improved.
As shown in fig. 3, a chip testing and evaluating platform includes: a chip testing device and an equipment unit; the equipment unit comprises a plurality of test equipment and power supply equipment, wherein the test equipment is used for testing parameters of the chip to be tested, the test equipment is used for receiving the test instruction sent by the control unit and measuring an output signal of the chip to be tested according to the test instruction, and the power supply equipment is used for receiving the opening/closing instruction sent by the control unit and opening/closing according to the opening/closing instruction.
The specific process of implementing the case list by the control unit is as follows:
the first step is as follows: and analyzing the test case list file.
The control unit reads the test case list file and analyzes the list contents in sequence to generate a control flow.
The second step is that: and connecting the equipment units.
And the equipment units are mounted according to the sequence required by the test environment, and the hardware interfaces of the equipment units are connected through the adapter plate.
The third step: and configuring the parameters of the equipment units to realize the required environment.
1. And according to the configuration parameters, automatically connecting the channel 1 interface of the digital oscilloscope to an interface of a pin of the chip PC1 through a command control adapter board.
2. According to the configuration parameters, the oscilloscope is controlled by commands to set the time resolution of the horizontal main time base to 50ms, the oscilloscope channel 1 is opened, the vertical voltage resolution of the channel 1 is set to be 1V, and the trigger level value is set to be 2.7V.
3. And controlling the output voltage value of the programmable high-precision direct-current stabilized power supply to be 3.3V through commands according to the configuration parameters.
The fourth step: burning the appointed test program.
The burning software is controlled through commands to compile the test program code of '001' in the table 2, and the test program is burned into the test chip after the compilation is successful.
The fifth step: and controlling the peripheral equipment to add excitation and measuring the actual semaphore.
1. And the programmable high-precision direct-current stabilized power supply is controlled to cut off the power supply through commands. And enabling the test object to be in a state of waiting for power-on restart.
2. The oscilloscope mode is commanded to be in "SINGLE" mode, ready to wait for the generation of a waveform.
3. And controlling the programmable high-precision direct-current stabilized power supply to start power supply through commands. And the test object is electrified and restarted to start executing the test program.
4. If the oscilloscope receives the waveform within 5 seconds and measures the waveform period value, the oscilloscope transmits the measured value to the PC; otherwise, the system transmits the failure information to the PC.
5. And controlling the oscilloscope through the command, and intercepting and saving the display picture of the oscilloscope to a specified file path.
And a sixth step: and analyzing the test signal quantity and the expected parameter range, and making a result judgment.
The PC machine processes and compares the semaphore of the period value sent by the receiving equipment unit with a 20 millisecond expected value parameter from-5% of the command transmission, and generates a judgment result.
The seventh step: and saving the log of the test items and generating a report.
The specific implementation method of the second step to the seventh step is as follows:
in the second step, the method for realizing the automatic connection of the equipment units comprises the following steps:
the control unit sends a connection instruction with the oscilloscope to the interface unit according to the test item of the case list and sends the connection establishment instruction to the report unit; after the interface unit receives a connection instruction with the oscilloscope, which is sent by the control unit, the switching module of the interface unit is connected with the oscilloscope; the switching module of the embodiment is a switching board embedded with an MCU chip, and the MCU chip carries an 8-to-1 special channel selector, so that 64-channel selective communication can be realized. The switching module realizes the relay function between the control unit and the equipment unit. When the control unit sends a command data packet to the MCU chip of the switching module through the UART data, the MCU chip analyzes the data packet and opens a corresponding channel, and interfaces at two ends of the switching module are respectively connected with the pin interface of the test chip and each interface of the equipment unit, so that the test chip is connected with external equipment.
In the third step, the specific method for the control unit to control the equipment unit is as follows:
the control unit encapsulates the SCPI command required by the control of the external equipment, and realizes the control of the equipment unit by sending the test action instruction appointed in the test function and matching the SCPI command. The operation required by the test equipment during manual test is packaged and generalized, the operation is set as a control instruction of the interface of the middle layer, and the equipment unit can be controlled to carry out parameter configuration, opening/closing and corresponding test actions by issuing the instruction to the corresponding interface. Different test devices can be selected according to different test contents. The control unit encapsulates a generalized standard interface for different devices. Different device models, device interface formats, and device interface instructions may differ.
The invention encapsulates the interface functions of different equipment units into standard functions, realizes the equipment interface generalization, and solves the problem that the equipment information needs to be reconfigured or the interface needs to be redeveloped when the equipment is replaced each time. The compatibility of chip test is realized.
Specifically, the method comprises the following steps: the specific operation of the selection device in the device unit of this embodiment: necessary configuration information such as the model of the oscilloscope, the model of the power supply, the model of the wave filter, the name and the version of the burning unit and the like can be input into the config.ini file of the control unit, so that the system can quickly find a matching item when the parameters of the equipment unit are configured according to the test function.
And extracting and recording each row of data of the configuration file, and confirming the configuration.
Specifically, the method comprises the following steps: according to the oscilloscope configuration information OSCP _ config obtained from config.ini, when the platform runs to the relevant operation of the oscilloscope, the corresponding program is selected according to the information of OSCP _ config to run, and the following details are as follows:
taking the selection of oscilloscope DS2102 series as an example:
when OSCP _ config is equal to "DS 2102
The above procedure corresponding to OSCP _ Choose was selected as a class object of the DS2102 series oscilloscope. And the instrument selection can be completed. "DS 2102 ()" is a corresponding oscilloscope instruction library.
Oscilloscope function called after system configuration environment equipment
OSCP_Choose.OSCP_H_PULSE_WID_MEASURE(chanl1,0.5)。
In the fourth step, the specific implementation method of automatic burning is as follows:
in the embodiment, the python is used for encapsulating the keyboard operation and the mouse operation of the relevant keys of the burning software required by the user, so that the burning of the test file can be automatically controlled; the method for automatically controlling the keyboard to operate the burning software is to use a shortcut key mode of the software or a self-contained interface of the software to carry out operation instruction encapsulation; the method for automatically controlling the mouse to operate the burning software is to simulate the movement of the mouse and click an event, obtain the position and the coordinates of each key after the tool window is maximized under the condition of specifying the screen resolution, package coordinate point information and call a function to perform simulated mouse operation.
This embodiment is illustrated by using IAR programming software: the automatic burning can be realized by adopting the following two modes:
mode 1: and performing operation instruction encapsulation by using a shortcut key mode control of the software or a self-contained interface of the software.
Pressing the 'maximize' key and then pressing the 'F7' key on the simulated keyboard to realize the case burning instruction of the shortcut key software as follows:
the function is encapsulated as follows:
mode 2: and simulating mouse movement and clicking events to control the compiling function of the IAR.
IAR software 16: 9, the position and the coordinates of each key after the window is maximized under 1920 × 1080 resolution:
after each coordinate point is obtained, packaging can be carried out, and specific codes are as follows:
batch _ build 668,60 # compiled key coordinates
Download key coordinates of 720,60 #
And calling a function to perform simulated mouse operation, moving to a compiling button and clicking to execute.
def key_rebuild(self,t):
pyautogui.moveTo(self.soft.rebuild,duration＝t)
pyautogui.click(button＝self.soft.button_l)
At different resolutions, the coordinate conversion method is as follows:
as shown in fig. 4, for example, if the compiling button has coordinates (668,60) at 1920 × 1080 resolution, the compiling button can be scaled, and if the screen resolution is 1366 × 768, the compiling button has coordinates (1366/1920 × 668,768/1080 × 60), so that the actual coordinates at the current resolution can be obtained.
Before the system is started, the configuration information of the equipment unit is input, and the control unit analyzes and records the configuration information into a test function.
In the fifth step, the specific implementation method for controlling the peripheral to add excitation and measuring the actual semaphore is as follows, and table 3 is a case list of oscilloscope actions.
TABLE 3
As shown in table 3, taking an oscilloscope test as an example, in the test, operations such as setting the precision of the master time base, setting the trigger type, querying the period, detecting the pulse width, etc. need to be performed on the oscilloscope, and for the test content, the case list defines the test action and the action command of the oscilloscope. Taking the query of the positive pulse width time of the waveform as an example, when the control unit realizes the test action by sending the action command, the calling method of the test function is as follows:
1. a standard function is called. And after capturing the command and the parameter corresponding to the positive pulse width time of the query waveform in the test case list, the control unit calls the standard function with the same name. (the standard function of the corresponding query positive PULSE width time is OSCP _ H _ PULSE _ WID _ MEASURE, and the parameters are the time for channel oscilloscope channel n selection and waittime to wait).
2. And (4) realizing an interface function. And calling the bottom function, opening the positive pulse width measurement function of the channel, and returning the measurement result returned by the bottom function method.
3. And (4) implementing the bottom layer function. The interface unit sends the positive pulse width measurement function of the bottom layer function opening channel to the oscilloscope, the bottom layer function encapsulates the method for inquiring the positive pulse width time of the waveform, the specific execution of the oscilloscope for inquiring the positive pulse width time of the waveform is realized through the bottom layer function, and an inquiry value is returned.
Example (c): method for realizing standard function OSCP _ H _ PULSE _ WID _ MEASURE
def OSCP _ H _ PULSE _ WID _ MEASURE (self, channel, waittime) # Inquiries Positive PULSE Width time
# Positive pulse Width measurement function of open channel, and returning measurement results
return_value＝oscp.oscp_h_pulse_wid(channel)
time.sleep(waittime)
return(return_value)
Wherein, the interface function "def oscp _ h _ pulse _ wid (self, channel): query positive pulse width time":
the bottom function pulse _ wid function is a packaged command, and has the following specific structure:
def pulse_wid(self,channel):
h_pulse_wid＝":MEASure:PWIDth？"+channel
return(h_pulse_wid)
using pulse _ wid (self, channel) to put the SCPI command ": MEASURE: PWIDth? And packaging is carried out, the positive pulse width time of the oscilloscope is inquired, a value is returned to the pulse _ time of the upper layer, and the command can acquire the positive pulse width time grabbed by the current oscilloscope.
The same method is adopted for other equipment units or tool selection, and the detailed description is omitted here.
And a sixth step: and analyzing the test signal quantity and the expected parameter range, and judging the test result.
The actual signal quantity measured in the fifth step is compared with the expected value and the expected error range. If the actual semaphore is within the expected range, the determination is correct, otherwise the determination is wrong. The determination result and the actual signal value, and the expected value interval information are transmitted to a report section.
Seventhly, storing the log of the test item, and generating a specific result of the report as shown in fig. 7, wherein the report implementing unit synchronously generates the report according to the test content and the test result sent in the test process of the control unit. The feedback information is gathered to generate a total result report, a Log file and the like, the current test condition is displayed in a test result column in the report in real time, and information such as chip environment conditions and test execution steps can be synchronously mastered through a report unit, so that problems can be conveniently traced and analyzed.
Secondly, the system method is realized:
the chip test evaluation method and flow shown in fig. 5 includes the following steps:
in step 509, the control unit determines whether the chip passes the test according to the reading of the device unit, and sends the test determination result information to the report unit.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (9)
1. A chip testing apparatus, comprising:
a control unit and an interface unit; the interface unit includes: the device comprises a switching module, a debugging module and an equipment unit instruction module;
the control unit is used for calling a test item name, a test function and a test item flow corresponding to the name of the tested chip in a test case list according to the name of the tested chip, wherein the test function comprises a plurality of functions of an equipment unit, and the plurality of functions of the equipment unit correspond to a plurality of models of the equipment unit;
sending a connection instruction to the interface unit according to the test item flow of the case list, and sending a connection establishment instruction to a report unit; sending a test instruction to the interface unit according to the name of the test item of the case list; sending parameter configuration and opening/closing instructions of an equipment unit to the interface unit according to the test equipment and the test function corresponding to the test item of the case list, and sending the parameter configuration and the opening/closing instructions to a report unit; reading the measurement reading of the equipment unit according to the test function in the case list, and sending the reading of the equipment unit to a report unit; judging whether the chip passes the test or not according to the reading of the equipment unit, and sending test judgment result information to a report unit;
the switching module receives the connection instruction sent by the control unit, and the switching module of the interface unit establishes connection with the equipment unit according to the connection instruction;
the debugging module is used for burning the test content corresponding to the test instruction to the tested chip according to the test instruction and sending the burning instruction to the report unit;
and the equipment unit instruction module is used for receiving the equipment unit parameter configuration and opening/closing instruction sent by the control unit and controlling the equipment unit according to the parameter configuration and opening/closing instruction.
2. The chip testing device according to claim 1, wherein the control unit is further specifically configured to:
determining a plurality of equipment units according to the test requirements, and determining equipment models corresponding to the equipment units according to the system environment configuration requirements;
determining an interface function according to a plurality of bottom layer functions corresponding to a certain model of any equipment unit;
determining a standard function of the equipment unit in a case list according to a plurality of interface functions corresponding to a plurality of models of the equipment unit;
establishing a case list according to the test content and the standard function;
the interface unit is further specifically configured to:
the interface unit splits the test function according to the test function to obtain a standard function corresponding to the equipment unit/the chip to be tested;
the interface unit splits the standard function according to the test equipment to obtain an interface function corresponding to the equipment unit/the chip to be tested;
and the interface unit sends the interface function to the equipment unit/chip to be tested.
3. The chip testing apparatus according to claim 1 or 2, further comprising:
and the report unit is used for receiving the test content and the test result of the tested chip sent by the control unit in the test execution process and synchronously generating a report.
4. The chip testing apparatus according to claim 3, wherein the interface unit further comprises:
and the cloud network interface module is used for providing hardware support and a network communication protocol required by network connection.
5. A chip testing and evaluation platform, comprising:
the chip testing device and the equipment unit;
the equipment unit comprises a plurality of test equipment and power supply equipment, wherein the test equipment is used for testing parameters of a chip to be tested, the test equipment is used for receiving a test instruction sent by the control unit and measuring an output signal of the chip to be tested according to the test instruction, and the power supply equipment is used for receiving an opening/closing instruction sent by the control unit and opening/closing according to the opening/closing instruction.
6. A chip test evaluation method is characterized by comprising the following steps:
the control unit calls a test item name, a test function and a test item flow corresponding to the name of the chip to be tested in a test case list according to the test item name, wherein the test function corresponds to a plurality of equipment units, the test function corresponds to a plurality of standard functions, and the standard functions correspond to interface functions of the equipment units;
the control unit sends a connection instruction to the interface unit according to the test item flow of the case list and sends a connection establishment instruction to a report unit;
the interface unit receives the connection instruction sent by the control unit, and a switching module of the interface unit establishes connection with the equipment unit according to the connection instruction;
the control unit sends a test instruction to the interface unit according to the name of the test item in the case list, and a debugging module of the interface unit burns test contents corresponding to the test instruction to a chip to be tested according to the test instruction and sends the burning instruction to a report unit;
the control unit sends the parameter configuration and opening/closing instruction of the equipment unit to the interface unit according to the test equipment and the test function corresponding to the test item of the case list, and sends the parameter configuration and opening/closing instruction to the report unit;
the equipment instruction module of the interface unit receives the parameter configuration and opening/closing instructions, sends the parameter configuration and opening/closing instructions to the equipment unit, and sends the parameter configuration and opening/closing instructions to the report unit;
the equipment unit receives the parameter configuration and the opening/closing instruction of the interface unit, performs parameter configuration and opening/closing according to the parameter configuration and the opening/closing instruction, and sends the parameter configuration and the opening/closing instruction to the report unit;
the control unit reads the measurement reading of the equipment unit according to the test function in the case list and sends the reading of the equipment unit to a report unit;
and the control unit judges whether the chip passes the test or not according to the reading of the equipment unit and sends the test judgment result information to the report unit.
7. The method according to claim 6, wherein before the controlling unit calls the test item name, the test function, the test item flow and the test device corresponding to the test item corresponding to the name of the tested chip in the test case list according to the name of the tested chip, the method further comprises:
determining a plurality of equipment units according to the test requirements, and determining equipment models corresponding to the equipment units according to the system environment configuration requirements;
determining an interface function according to a plurality of bottom layer functions corresponding to a certain model of any equipment unit;
determining a standard function of the equipment unit in a case list according to a plurality of interface functions corresponding to a plurality of models of the equipment unit;
and establishing a case list according to the test content and the standard function.
8. The method according to claim 7, wherein the controlling unit sends the parameter configuration and the on/off instruction of the device unit to the interface unit according to the test device and the test function corresponding to the test item in the case list, and sends the parameter configuration and the on/off instruction to the report unit, and the method includes:
the interface unit splits the test function according to the test function to obtain a standard function corresponding to the equipment unit/the chip to be tested;
the interface unit splits the standard function according to the test equipment to obtain an interface function corresponding to the equipment unit/the chip to be tested;
and the interface unit sends the interface function to the equipment unit/chip to be tested.
9. The method as claimed in claim 6, wherein the step of determining whether the chip passes the test according to the reading of the equipment unit further comprises:
and the report unit synchronously generates a test report according to the test judgment result and the log information sent by the control unit.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112100015A (en) * | 2020-11-19 | 2020-12-18 | 北京智芯微电子科技有限公司 | Chip testing device and chip testing method |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103760394A (en) * | 2014-01-15 | 2014-04-30 | 广东威创视讯科技股份有限公司 | Automatic processing method and device for measured data of oscilloscope |
| CN105004984A (en) * | 2015-06-25 | 2015-10-28 | 深圳市芯海科技有限公司 | Automatic chip testing method |
| CN105988903A (en) * | 2015-02-03 | 2016-10-05 | 合肥联鑫智能科技有限公司 | Laptop mainboard tester |
| CN107783873A (en) * | 2017-11-23 | 2018-03-09 | 芯海科技（深圳）股份有限公司 | A kind of implementation method of cd-rom recorder automatic test platform |
| WO2018218954A1 (en) * | 2017-05-27 | 2018-12-06 | 深圳市中兴微电子技术有限公司 | Verification platform and verification method, and computer storage medium |
| CN109633413A (en) * | 2018-12-28 | 2019-04-16 | 芯海科技（深圳）股份有限公司 | 32 MCU core chip test systems of one kind and its test method |
| CN109802864A (en) * | 2017-11-16 | 2019-05-24 | 中兴通讯股份有限公司 | Chip design and verification method, device and chip tester |
| CN109979520A (en) * | 2019-03-26 | 2019-07-05 | 深圳忆联信息系统有限公司 | Chip functions automated testing method, device and computer equipment |
-
2020
- 2020-05-29 CN CN202010479801.6A patent/CN111596203B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103760394A (en) * | 2014-01-15 | 2014-04-30 | 广东威创视讯科技股份有限公司 | Automatic processing method and device for measured data of oscilloscope |
| CN105988903A (en) * | 2015-02-03 | 2016-10-05 | 合肥联鑫智能科技有限公司 | Laptop mainboard tester |
| CN105004984A (en) * | 2015-06-25 | 2015-10-28 | 深圳市芯海科技有限公司 | Automatic chip testing method |
| WO2018218954A1 (en) * | 2017-05-27 | 2018-12-06 | 深圳市中兴微电子技术有限公司 | Verification platform and verification method, and computer storage medium |
| CN109802864A (en) * | 2017-11-16 | 2019-05-24 | 中兴通讯股份有限公司 | Chip design and verification method, device and chip tester |
| CN107783873A (en) * | 2017-11-23 | 2018-03-09 | 芯海科技（深圳）股份有限公司 | A kind of implementation method of cd-rom recorder automatic test platform |
| CN109633413A (en) * | 2018-12-28 | 2019-04-16 | 芯海科技（深圳）股份有限公司 | 32 MCU core chip test systems of one kind and its test method |
| CN109979520A (en) * | 2019-03-26 | 2019-07-05 | 深圳忆联信息系统有限公司 | Chip functions automated testing method, device and computer equipment |
Non-Patent Citations (3)
| Title |
|---|
| R.BHATTACHARYA等: "《FPGA based chip emulation system for test development of analog and mixed signal circuits: A case study of DC–DC buck converter》", 《MEASUREMENT》 * |
| 张李静等: "《智能卡COS芯片层模块设计与测试方案研究》", 《现代电子技术》 * |
| 谷荧柯等: "《基于IEC61508标准的功能安全芯片设计方法探讨》", 《铁路通信信号工程技术》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112100015A (en) * | 2020-11-19 | 2020-12-18 | 北京智芯微电子科技有限公司 | Chip testing device and chip testing method |
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|---|---|
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