TWI676040B - Semiconductor integrated circuit test system and semiconductor integrated circuit test device thereof - Google Patents

Abstract

This case discloses a semiconductor integrated circuit testing device including a testing machine and a data transmission module. The tester is provided with a test single board including a processing module and a test interface, wherein the processing module is electrically connected to the test interface, the test interface is used to electrically connect a test object, and the processing module is used for A test data is obtained from the DUT through the test interface. The data transmission module includes a first communication interface and a second communication interface, the first communication interface is electrically connected to the test interface, and the second communication interface is used to electrically connect an external electronic device for the processing. The module provides the test data to the external electronic device through the data transmission module. This case also discloses that a semiconductor integrated circuit test system includes the aforementioned integrated circuit test device and a communication device.

Description

Semiconductor integrated circuit test system and semiconductor integrated circuit test device

The invention relates to a circuit test system and a circuit test device thereof, and in particular to a semiconductor integrated circuit test system and a semiconductor integrated circuit test device for a semiconductor integrated circuit.

Generally speaking, semiconductor integrated circuit test equipment is designed to test the electrical properties of integrated circuits (ICs) to determine whether the integrated circuits manufactured by the manufacturers functionally meet the specifications in the specifications. In addition, integrated circuit products are further classified according to their electrical functions, and the industry often calls them Bin. General semiconductor integrated circuit test equipment includes, for example, a integrated circuit tester (Tester), an integrated circuit test classifier (Handler), a wafer prober (Prober), a test computer host, and a set of semiconductor integrated circuits. Circuit test operation software. These devices constitute a series of integrated circuit test procedures, and each device is composed of different components. Among them, the core device: the integrated circuit tester is equipped with a system test board for various special purposes or customized functional purposes ( Generally referred to as the system board), such as: Device Power Supply system board, Universal Voltage / Current Source system board, Precision Measurement Unit system board , Sequence Controller system board ... and so on.

With the development of science and technology, the functions of integrated circuits are becoming more and more complex and cover various digital logic and analog functions, mixed signals and system on a chip (SOC), thereby greatly increasing the difficulty of testing. On the other hand, the booming development of photosensitive element integrated circuits in recent years has also driven related testing fields. The characteristic of the integrated circuit test of the photosensitive element is the capture and comparison of a large amount of image data. In view of this, the adequacy of memory and the speed of data transmission will obviously affect the performance of the test.

Traditional integrated circuit test equipment takes a lot of time when accessing a large amount of data, so a new external load circuit (load board) needs to be designed separately. However, designing external hardware circuits also requires design, layout, assembly, and verification processes, which consumes time and labor. In addition, when testing integrated circuits with different functions or different specifications, external hardware circuits must be redesigned, which greatly reduces the feasibility of this solution. In another approach, users can also use the module tools provided by the manufacturer to change the test solution. However, in this method, the user must control the related operation of all tests, increase the difficulty of the test, and the final test results are more difficult to analyze.

The invention is to provide a semiconductor integrated circuit test system and a semiconductor integrated circuit test device thereof, so as to improve the test data transmission speed and improve the flexibility of the test architecture.

The invention discloses a semiconductor integrated circuit test device. The semiconductor integrated circuit test device includes a tester and a data transmission module. The testing machine includes a processing module and a testing interface. The processing module is electrically connected to the test interface. A first sub-channel in the test interface is used to electrically connect a DUT, and the processing module is used to obtain a test data from the DUT through the first sub-channel. The data transmission module includes a first communication interface and a second communication interface. The first communication interface is electrically connected to a second sub-channel in the test interface, and the data transmission module is used to selectively electrically connect an external electronic device through the second communication interface. The processing module is used to provide the test data to the external electronic device through the data transmission module.

The invention discloses a semiconductor integrated circuit test system. The semiconductor integrated circuit test system includes a tester, a data transmission module, and a communication device. The tester is provided with a test board, and the test board includes a first processing module and a test interface. The first processing module is electrically connected to the test interface, a first sub-channel in the test interface is used to electrically connect a test object, and the first processing module is used to pass from the test channel through the first sub-channel. The test object obtains a test data. The data transmission module includes a first communication interface and a second communication interface, and the first communication interface is electrically connected to a second sub-channel in the test interface. The communication device includes a third communication interface and a fourth communication interface. The data transmission module is selectively electrically connected to the second communication interface of the data transmission module via the third communication interface. The communication device is used for electrically connecting a second processing module of an external electronic device through the fourth communication interface. The first processing module is configured to provide the test data to the second processing module via the data transmission module and the communication device.

The above description of the contents of this disclosure and the description of the following embodiments are used to demonstrate and explain the spirit and principle of the present invention, and provide a further explanation of the scope of the patent application of the present invention.

The detailed features and advantages of the present invention are described in detail in the following embodiments. The content is sufficient for any person skilled in the art to understand and implement the technical contents of the present invention. Anyone skilled in the relevant art can easily understand the related objects and advantages of the present invention. The following examples further illustrate the viewpoints of the present invention in detail, but do not limit the scope of the present invention in any way.

Please refer to FIG. 1 to illustrate a test architecture. FIG. 1 is a functional block diagram of a semiconductor integrated circuit test device according to an embodiment of the present invention. The semiconductor integrated circuit test device A includes a tester 1 and a data transmission module 2. The tester 1 is used to electrically connect the object to be tested B, and the data transmission module 2 is used to electrically connect to an external electronic device C. Please continue to refer to the following description for details.

Please refer to FIG. 2, which is a functional block diagram of a semiconductor integrated circuit test device according to another embodiment of the present invention. As shown in FIG. 2, the semiconductor integrated circuit test device A includes a tester 1 and a data transmission module 2. The testing machine 1 is provided with a test board 11. In one embodiment, the test board 11 is detachably disposed in the body of the test machine 1. The test board 11 includes a processing module 111 and a test interface 112. The processing module 111 is electrically connected to the test interface 112.

The testing machine 1 is used to perform electrical test and classify the object B to be tested. The test board 11 is any type of system board and is associated with one or more measurement items. The processing module 111 of the test board 11 is, for example, a field programmable gate array (FPGA) circuit or an application specific integrated circuit (ASIC). The test board 11 is electrically connected to the main body of the testing machine 1 through the test interface 112, so as to be electrically connected to the test object B. The test interface 112 includes a first sub-channel 1121 and a second sub-channel 1122. The first sub-channel 1121 and the second sub-channel 1122 may be different channels among a plurality of associated channels. In an embodiment, the first sub-channel 1121 and the second sub-channel 1122 may be different pins among a plurality of pins on the same interface. In such an embodiment, the user can transmit through the existing test interface 112, which avoids the trouble of having to modify other hardware designs due to changing the test interface 112. In another method, the first sub-channel 1121 and the second sub-channel 1122 may also be two independent interfaces. The specifications of the test interface 112 can be matched with the connection interface provided by the tester 1, and are not limited herein.

The data transmission module 2 includes a first communication interface 21 and a second communication interface 22. The first communication interface 21 is, for example, a spring connector (POGO PIN) or a connector fitted to the spring connector. The second communication interface 22 has a higher transmission rate than the first communication interface 21, and can support various types of networks or communication standards such as PCIE, for example. In one embodiment, the second communication interface 22 can support a transmission rate of 1 GHz (giga Hertz).

Please refer to FIG. 3 again, which is a functional block diagram of a semiconductor integrated circuit test device according to another embodiment of the present invention. In this embodiment, for example, the data transmission module 2 further has a relay circuit 23 connected between the first communication interface 21 and the second communication interface 22. The relay circuit 23 is used to implement a first in first out (FIFO) function to coordinate the input (first communication interface 21) and output (second communication interface) of the data transmission module 2 with different transmission rates. twenty two). The relay circuit 23 may be a field programmable logic gate circuit, and the implementation of the relay circuit 23 is not limited herein.

In practice, the data transmission module 2 is, for example, a field programmable logic gate array circuit, or a transfer card or a transfer circuit implemented based on a printed circuit board (PCB) and other electronic components. In one embodiment, the data transmission module 2 is independent of the testing machine 1 and is an independent component connected to the testing machine 1 by itself. In another embodiment, the data transmission module 2 is integrated in the test board 11. In a further embodiment, the data transmission module 2 is integrated in the testing machine 1. The above is only an example and is not limited thereto.

The first sub-channel 1121 in the test interface 112 is used to electrically connect the object B to be tested. The test object B is, for example, an integrated circuit to be tested. The first communication interface 21 of the data transmission module 2 is electrically connected to the second sub-channel 1122 of the test interface 112. The data transmission module 2 is used for selectively and electrically connecting the external electronic device C through the second communication interface 22. The external electronic device C is, for example, an electronic device having a computing function, such as a computer or a server.

Based on the above-mentioned structure, the processing module 111 is configured to obtain a test data from the test object B through the first sub-channel 1121. The processing module 111 is used to provide test data to the external electronic device C through the second sub-channel 1122 and the data transmission module 2.

In one embodiment, the processing module 111 is configured to obtain a test-related instruction from the external electronic device C through a control channel (as shown by a center line connecting the processing module 111 and the external electronic device C in FIG. 2) data. In practice, the control channel marked by the centerline can be used to transmit test data in addition to transmitting instructions. In one embodiment, the control channel is, for example, an interface supporting the RS232 standard. However, this control channel is basically designed for instruction transmission and does not support high-speed transmission. In other words, the transmission rate of this control channel is not sufficient to support the transmission of test data. Therefore, transmission of test data through the control channel often causes delay or even congestion in the control channel. As mentioned above, if the relevant specifications of this control channel are directly changed to increase the transmission rate, it may affect the whole body at once, affecting the test board or other related hardware designs.

In view of this, in this embodiment, after the processing module 111 tests the test object B via the testing machine 1 according to the instruction of the external electronic device C, the test object B provides the association with The relevant test data of the test results are provided to the processing module 111. The processing module 111 selectively processes the test data. In one embodiment, the processing module 111 is used to convert the format of the test data. In another embodiment, the processing module 111 is configured to perform preliminary data processing on the test data. In a further embodiment, the processing module 111 does not process the test data. Then, the processing module 111 provides the unprocessed or processed test data to the data transmission module 2 through the second sub-channel 1122, so that the second communication interface 22 of the data transmission module 2 can send the test data to the data transmission module 2. The test data is provided to the external electronic device C. As described above, since the transmission rate of the second communication interface 22 of the data transmission module 2 is higher than that of the aforementioned control channel (shown by a dotted line), the semiconductor integrated circuit test device A can use a relatively high transmission rate. The test data is provided to the external electronic device C for subsequent analysis and processing.

Please refer to FIG. 4A and FIG. 4B again. FIG. 4A is a functional block diagram of a semiconductor integrated circuit test device according to another embodiment of the present invention. FIG. Relative position diagram. Compared with the embodiment shown in FIG. 1, in the embodiments shown in FIGS. 4A and 4B, the data transmission module 2 is independent of the test machine 1 ′ and is an independent electrical connection with the test machine 1 ′. element. The testing machine 1 'further has a loading board 12 and a body 13 (shown in FIG. 4B). The main body 13 is electrically connected to the carrier board 12. The test board 11 is disposed in the body 13. The loading board 12 includes a first connection port 121 and a second connection port 122. The first port 121 is electrically connected to the first sub-channel 1121, and the second port 122 is electrically connected to the second sub-channel 1122. The first connection port 121 is detachably connected to the object B to be tested. The second connection port 122 is detachably connected to the data transmission module 2. The first connection port 121 and the second connection port 122 may be different pins among multiple pins in the same interface; or, the first connection port 121 and the second connection port 122 may also be two independent interfaces.

Referring to FIG. 4B, in terms of the physical architecture, the body 123 of the carrier board 12 is disposed on the body 13 of the testing machine 1 '. The first connection port 121 and the second connection port 122 are respectively electrically connected to the test object B and the data transmission module 2, and the test object B and the data transmission module 2 are carried on the carrier board 12. Under such a structure, since the data transmission module 2 is a component that is physically independent of the test board, it is not necessary to significantly modify the test board 11 when changing the hardware configuration of the data transmission module 2. In an embodiment, the processing module 111 is a field programmable logic gate circuit. Therefore, by adjusting the processing module 111 and the data transmission module 2, the semiconductor integrated circuit test device A 'can be used without changing other hardware. In the case of the architecture, the test data related to the object to be tested B is provided to the external electronic device C at a transmission rate required by the user.

Please refer to FIG. 5, which is a functional block diagram of a semiconductor integrated circuit test device according to another embodiment of the present invention. Compared with the embodiment shown in FIG. 1, in the embodiment shown in FIG. 5, the test board 11 ″ has a memory module 115. The memory module 115 is electrically connected to the processing module 111. The memory module 115 is, for example, It is volatile memory or non-volatile memory. In this embodiment, the processing module 111 converts the test data from a first format to a second format, so that the conversion The later test data is suitable to be stored in the memory module 115. The second format is associated with a storage format of the memory module 115. In one embodiment, the storage format means that the memory module 115 can be stored in one access. The unit of data transmitted. The processing module 111 stores the converted test data in the memory module 115, and the processing module 111 provides the converted test data to the data transmission module 2. In practice, the external electronic device C Should have the ability (such as having a corresponding function library) to process converted test data or untransformed test data. Therefore, according to the planned signal path, the processing module 111 can convert the converted test data The test data is provided to the external electronic device C or the unconverted test data is provided to the external electronic device C.

It should be noted that after reading this specification, those with ordinary knowledge in the technical field can combine or adjust related components according to the foregoing embodiments to adjust the structure or function of the semiconductor integrated circuit test device according to actual needs. In other words, the structure and related operations of the semiconductor integrated circuit test device are not limited to the single embodiment described above.

In addition to the semiconductor integrated circuit test apparatus described above, the present invention further provides a semiconductor integrated circuit test system. Please refer to FIG. 6, which is a functional block diagram of a semiconductor integrated circuit test system according to yet another embodiment of the present invention. The semiconductor integrated circuit test system D includes a communication device 3 in addition to the tester 1 and the data transmission module 2 described above. It should be noted that the testing machine 1 in FIG. 2 is taken as an example here, and the testing machine of the semiconductor integrated circuit test system D can be adjusted according to the combination of the foregoing embodiments, without being limited thereto.

Continuing from the foregoing, the communication device 3 includes a third communication interface 31, a fourth communication interface 32, a second processing module 33, and a second memory module 34. The second processing module 33 is electrically connected to the third communication interface 31 and the fourth communication interface 32, and the second memory module 34 is electrically connected to the second processing module 33. The third communication interface 31 is selectively electrically connected to the second communication interface 22 of the data transmission module 2, and the fourth communication interface 32 is used to selectively electrically connect the third processing module 41 of the external electronic device C.

The communication device 3 is, for example, a field programmable logic gate array circuit, or a function expansion card or a function expansion circuit implemented based on a printed circuit board (PCB) and other electronic components. The third communication interface 31 is adapted to the specifications of the aforementioned second communication interface 22 and can support, for example, various types of networks or communication standards such as PCIE. In terms of hardware specifications, the third communication interface 31 can support corresponding optical fiber cables. Or a bus. The specifications of the fourth communication interface 32 are adapted to the transmission interface of the external electronic device C. In an embodiment, the external electronic device C is, for example, a computer, and the third processing module 41 and the third memory module 42 are a chipset and a random access memory (random access memory) respectively disposed on the motherboard. memory, RAM), and the fourth communication interface 32 can support the PCIE transmission protocol.

Under such a structure, the first processing module 111 is used to provide test data to the third processing module 41 via the data transmission module 2 and the communication device 3. In the foregoing embodiment (the third processing module 41 and the third memory module 42 are a chipset and a random access memory respectively disposed on a computer motherboard), the third processing module 41 may receive and issue The computer instruction of the third processing module 41 moves the test data in the second memory module 34 to the third memory module of the external electronic device C in a direct memory access (DMA) manner. 42 in. This facilitates data transmission between the testing machine 1 and the external electronic device C, and facilitates subsequent software calculations.

In summary, the present invention provides a semiconductor integrated circuit test system and a semiconductor integrated circuit test device thereof. The semiconductor integrated circuit test device is used to provide test data through a data transmission module. In practice, the transmission rate of the external transmission interface of the data transmission module is greater than the transmission rate of the channel used by the test machine to transmit control instructions. In one embodiment, the data transmission module is an independent single board. In another embodiment, the data transmission module is integrated on the test machine. Therefore, the semiconductor integrated circuit test system and the semiconductor integrated circuit test device can provide test data at a relatively fast transmission speed. Moreover, the semiconductor integrated circuit test system and the semiconductor integrated circuit test device also have a more flexible test structure, and the semiconductor integrated circuit test system and the semiconductor integrated circuit test device can be based on different test requirements. Changing the method of transmitting data does not need to change the hardware design because of different test architectures or DUTs, which is quite practical.

Although the present invention is disclosed in the foregoing embodiments, it is not intended to limit the present invention. Changes and modifications made without departing from the spirit and scope of the present invention belong to the patent protection scope of the present invention. For the protection scope defined by the present invention, please refer to the attached patent application scope.

1,1 ’, 1” ‧‧‧‧testing machine

11‧‧‧test board

111‧‧‧Processing Module

112‧‧‧test interface

1121‧‧‧The first sub-channel

1122‧‧‧Second sub-channel

12‧‧‧ on board

121‧‧‧First port

122‧‧‧Second Port

123‧‧‧The body of the carrier board

13‧‧‧The body of the test machine

115‧‧‧Memory module

2‧‧‧Data Transmission Module

21‧‧‧First communication interface

22‧‧‧Second communication interface

3‧‧‧ communication device

31‧‧‧Third communication interface

32‧‧‧ Fourth communication interface

33‧‧‧Second Processing Module

34‧‧‧Second Memory Module

41‧‧‧Third Processing Module

42‧‧‧Third Memory Module

A, A ’, A” ‧‧‧Semiconductor integrated circuit test device

B‧‧‧DUT

C‧‧‧External electronics

D‧‧‧Semiconductor Integrated Circuit Test System

FIG. 1 is a functional block diagram of a semiconductor integrated circuit test device according to an embodiment of the present invention. FIG. 2 is a functional block diagram of a semiconductor integrated circuit test device according to another embodiment of the present invention. FIG. 3 is a functional block diagram of a semiconductor integrated circuit test device according to another embodiment of the present invention. FIG. 4A is a functional block diagram of a semiconductor integrated circuit test device according to another embodiment of the present invention. FIG. 4B is a schematic diagram of the relative positions of the testing machine and the object to be tested in the embodiment of FIG. 4A. FIG. 5 is a functional block diagram of a semiconductor integrated circuit test device according to another embodiment of the present invention. FIG. 6 is a functional block diagram of a semiconductor integrated circuit test system according to yet another embodiment of the present invention.

Claims (10)

A semiconductor integrated circuit test device includes a test machine provided with a test board. The test board includes a processing module and a test interface. The processing module is electrically connected to the test interface. A first sub-channel is used to electrically connect a DUT, the processing module is used to obtain a test data from the DUT through the first sub-channel; and a data transmission module including a first communication interface And a second communication interface, the first communication interface is electrically connected to a second sub-channel in the test interface, and the data transmission module is used to selectively electrically connect an external electronic device through the second communication interface ; Wherein the processing module is used to provide the test data to the external electronic device through the data transmission module, and the test machine further includes a body and a load carrying board, and the body is electrically connected to the load carrying board The test board is disposed on the body. The load board includes a first port and a second port. The first port is electrically connected to the first sub-channel, and the second port is electrically connected.该 第 The first Sub-channel, the first connection port for detachably connected to the DUT, the second connection port is detachably connected to the data transmission module. The semiconductor integrated circuit test device according to claim 1, wherein the processing module further converts the test data from a first format to a second format, and provides the converted test data to the data transmission module. group. The semiconductor integrated circuit testing device according to claim 2, wherein the testing machine further includes a memory module, and the processing module stores the converted test data in the memory module, wherein the second format is associated A storage format in the memory module. The semiconductor integrated circuit test device according to claim 1, wherein the data transmission module is integrated in the processing module. A semiconductor integrated circuit test system includes a test machine provided with a test board. The test board includes a first processing module and a test interface. The first processing module is electrically connected to the test interface. A first sub-channel in the test interface is used to electrically connect a DUT, and the first processing module is used to obtain a test data from the DUT through the first sub-channel; a data transmission module includes A first communication interface and a second communication interface, the first communication interface is electrically connected to a second sub-channel in the test interface; and a communication device including a third communication interface and a fourth communication interface, the A third communication interface selectively electrically connects the second communication interface of the data transmission module, and the communication device is used to electrically connect a third processing module of an external electronic device through the fourth communication interface; wherein, The first processing module is configured to provide the test data to the third processing module via the data transmission module and the communication device. The semiconductor integrated circuit test system according to claim 5, wherein the first processing module further converts the test data from a first format to a second format, and provides the converted test data to the data Transmission module. The semiconductor integrated circuit test system according to claim 6, wherein the testing machine further includes a memory module, and the first processing module stores the converted test data in the memory module, wherein the second The format is associated with a storage format of the memory module. The semiconductor integrated circuit test system according to claim 5, wherein the test machine further includes a body and a load board, the body is electrically connected to the load board, and the test board is disposed on the body, The loading board includes a first connection port and a second connection port, the first connection port is electrically connected to the first sub-channel, the second connection port is electrically connected to the second sub-channel, and the first connection The port is detachably connected to the DUT, and the second port is detachably connected to the adapter board. The semiconductor integrated circuit test system according to claim 5, wherein the data transmission module is integrated in the processing module. The semiconductor integrated circuit test system according to claim 5, wherein the communication device further includes a second processing module and a second memory module, and the third processing module is electrically connected to the second memory module The third communication interface and the fourth communication interface, the second memory module stores the test data received by the third processing module through the third communication interface, and the third processing module is used to receive a An instruction to move the test data in the second memory module to the third memory module of the external electronic device in a DMA manner.