CN115237094A - Testing device and testing equipment - Google Patents

Abstract

The embodiment of the application discloses a testing device and testing equipment, which can simplify testing operation and improve testing efficiency. The specific scheme is as follows: a test apparatus is provided that includes an interface circuit, a test circuit, and a test interface, the interface circuit, the test circuit, and the test interface being coupled. The test interface is used for connecting a device to be tested. The test interface is used for receiving a test signal from the device to be tested, the test circuit is used for determining a test result of the device to be tested according to the test signal, and the interface circuit is used for sending the test result.

Description

Testing device and testing equipment

Technical Field

The embodiment of the application relates to the technical field of electronics, in particular to a testing device and testing equipment.

Background

With the development of high-speed signal technology, many types of high-speed signals are present, such as a high-speed serial computer expansion bus (PCIE) signal, a serial attached small computer system interface (SAS) signal, a Serial Advanced Technology Attachment (SATA) signal, and the like. With the continuous development of high-speed signals, the link design of the high-speed signals becomes more and more challenging, and the testing of the high-speed signals becomes more and more important.

For example, a processor and a high-speed serial computer expansion bus slot are coupled to each other on a motherboard of a server, and a link between the processor and the high-speed serial computer expansion bus slot is used for transmitting a high-speed signal, which needs to be tested for an eye diagram and a bit error rate. However, the current testing method is complex in operation and low in testing efficiency.

Disclosure of Invention

The embodiment of the application provides a testing device and testing equipment, which can simplify testing operation and improve testing efficiency.

In order to achieve the above purpose, the embodiment of the present application adopts the following technical solutions:

in a first aspect of the embodiments of the present application, a testing apparatus is provided, where the testing apparatus includes: the interface circuit, the test circuit and the test interface are coupled. The test interface is used for connecting a device to be tested. The test interface is used for receiving a test signal from a device to be tested, the test circuit is used for determining a test result of the device to be tested according to the test signal, and the interface circuit is used for sending the test result.

The test device provided by the embodiment of the application comprises a test circuit and a test interface, wherein the test interface is used for being butted with a device to be tested, a test signal from the device to be tested is received through the test interface, and the test circuit is used for generating a test result according to the test signal. Meanwhile, compared with the test by adopting an oscilloscope or an error code meter, the test device of the embodiment is directly connected with the device to be tested, does not need to be connected with the oscilloscope or the error code meter through a coaxial cable connector, and does not need to change the connection position of the coaxial cable connector for many times, so the test operation can be simplified, and the test efficiency can be improved.

With reference to the first aspect, in a possible implementation manner, the test signal is a first test pattern, the test result includes eye diagram data and/or an eye diagram test conclusion, and the eye diagram test conclusion is used to indicate whether the eye diagram data meets a preset eye diagram test index.

Compared with the test device adopting an oscilloscope, the test device provided by the embodiment of the application is directly connected with the device to be tested, does not need to be connected with the oscilloscope through a coaxial cable connector, does not need to change the connection position of the coaxial cable connector for many times, can simplify the test operation, can improve the test efficiency, and can reduce the test cost.

With reference to the first aspect, in a possible implementation manner, when the test result is the eye pattern data, the test circuit is specifically configured to acquire the synchronous clock signal according to the first test pattern, determine waveform data of a plurality of clock cycles according to the first test pattern and the synchronous clock signal, and determine the eye pattern data according to the waveform data of the plurality of clock cycles. Or when the test result is the eye pattern test conclusion, the test circuit is further used for determining the eye pattern test conclusion according to the eye pattern data and the preset eye pattern test index.

Compared with the test by adopting an oscilloscope, the test device provided by the embodiment of the application is directly connected with the device to be tested, does not need to be connected with the oscilloscope through a coaxial cable connector, does not need to change the connection position of the coaxial cable connector for many times, can simplify the test operation, can improve the test efficiency, and can reduce the test cost.

With reference to the first aspect, in a possible implementation manner, the test signal is a second test pattern, and the test result is error code information. The interface circuit is further used for receiving the control signal, the test circuit is further used for generating a third test code pattern according to the control signal, the test interface is further used for sending the third test code pattern to the device to be tested, and the second test code pattern is obtained by converting the device to be tested according to the third test code pattern.

The test device provided by the embodiment of the application receives the second test code pattern from the device to be tested through the test interface, and generates error code information according to the second test code pattern and the third test code pattern through the test circuit.

With reference to the first aspect, in a possible implementation manner, the test circuit is specifically configured to compare the second test pattern with the third test pattern bit by bit, determine the bit number of the error code of the second test pattern, and determine the error code information according to a ratio of the bit number of the error code to the total bit number of the third test pattern.

The test device provided by the embodiment of the application receives the second test code pattern from the device to be tested through the test interface, and generates error code information according to the second test code pattern and the third test code pattern through the test circuit.

With reference to the first aspect, in a possible implementation manner, the test circuit includes a test chip, one end of the test chip is coupled to the test interface, and the other end of the test chip is coupled to the interface circuit.

The test device provided by the embodiment of the application generates the test result according to the test signal through the test chip without adopting an oscilloscope and an error code meter which are expensive to generate the test result, so that the test cost can be reduced. Meanwhile, compared with the test by adopting an oscilloscope or an error code meter, the test device of the embodiment is directly connected with the device to be tested, does not need to be connected with the oscilloscope or the error code meter through a coaxial cable connector, does not need to change the connection position of the coaxial cable connector for many times, can simplify the test operation, and can improve the test efficiency.

With reference to the first aspect, in a possible implementation manner, the test chip includes a high-speed clock data recovery chip, a signal driver chip, or a selection chip.

With reference to the first aspect, in a possible implementation manner, the test circuit further includes a clock circuit and a reset circuit, and the clock circuit and the reset circuit are respectively coupled to the test chip.

The test device provided by the embodiment of the application provides a clock for the test chip through the clock circuit, and the test chip is restored to the initial state when the test of each channel in the device to be tested is completed through the reset circuit, so that the test device can complete the test of all channels in the device to be tested, and an expensive oscilloscope and an error code tester are not required to be adopted to generate a test result, thereby reducing the test cost. Meanwhile, compared with the test by adopting an oscilloscope or an error code meter, the test device of the embodiment is directly connected with the device to be tested, does not need to be connected with the oscilloscope or the error code meter through a coaxial cable connector, does not need to change the connection position of the coaxial cable connector for many times, can simplify the test operation, and can improve the test efficiency.

With reference to the first aspect, in a possible implementation manner, the test apparatus further includes a power supply circuit, an input end of the power supply circuit is coupled to the test interface, and an output end of the power supply circuit is coupled to the interface circuit and the test circuit.

The test device provided by the embodiment of the application processes the power supply voltage received by the test interface through the power supply circuit, so that stable power supply voltage can be provided for the interface circuit and the test circuit.

With reference to the first aspect, in a possible implementation manner, the test interface includes a high-speed serial computer expansion bus interface, a serial connection small computer system interface, a serial advanced technology attachment interface, a card machine electrical interface, a non-volatile memory standard interface, or an open core protocol interface.

According to the test device provided by the embodiment of the application, different types of test interfaces are arranged according to the types of the slots in the device to be tested, so that the test device can be supported to test high-speed signals such as high-speed serial computer expansion bus signals, serial connection small computer system interface signals, serial advanced technology attachment signals and universal serial bus signals.

With reference to the first aspect, in a possible implementation manner, the interface circuit includes an ethernet interface circuit, a serial communication interface circuit, a universal serial bus interface circuit, or a wireless interface circuit.

According to the test device provided by the embodiment of the application, the interface circuit is set to be the interface circuit of a plurality of types, so that different types of control devices can be supported, for example, the control device can be a personal computer, a tablet computer, a mobile phone and the like.

In a second aspect of the embodiments of the present application, a testing apparatus is provided, where the testing apparatus is used to test a device to be tested, the testing apparatus includes a control device and a testing device, one end of the control device is coupled to the testing device, and the other end of the control device is used to connect the device to be tested, and a structure of the testing device is the structure of the testing device as described in the first aspect or any possible implementation manner of the first aspect. The control device is used for sending a control signal to the device to be tested, the test device is used for receiving a test signal sent by the device to be tested according to the control signal, and a test result of the device to be tested is determined according to the test signal. The control device is also used for receiving the test result.

For the description of the second aspect in the present application, reference may be made to the detailed description of the first aspect; in addition, the beneficial effects of the second aspect may refer to the beneficial effect analysis of the first aspect, and are not described herein again.

Drawings

FIG. 1 is a schematic structural view of a test fixture;

FIG. 2 is a schematic view of an eye diagram;

FIG. 3 is a schematic diagram of an eye test circuit;

FIG. 4 is a schematic diagram of an error code test circuit;

fig. 5 is a schematic diagram of an application scenario of a testing apparatus according to an embodiment of the present application;

FIG. 6 is a schematic diagram of another application scenario of a testing apparatus according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of a testing apparatus according to an embodiment of the present disclosure;

fig. 8 is a schematic diagram of an application scenario of a testing device according to an embodiment of the present disclosure;

fig. 9 is a schematic structural diagram of a testing apparatus according to an embodiment of the present application.

Detailed Description

The making and using of the various embodiments are discussed in detail below. It should be appreciated that many of the applicable inventive concepts provided herein may be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the specification and techniques, and do not limit the scope of the application.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art.

Circuits or other components may be described or referred to as "used" to perform one or more tasks. In this case, "for" is used to connote structure by indicating that the circuit/component includes structure (e.g., circuitry) that performs one or more tasks during operation. Thus, a given circuit/component may be said to be performing that task even when the circuit/component is not currently operational (e.g., not open). Circuits/components used with the term "for" include hardware, such as circuits that perform operations, and the like.

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. In the present application, "at least one" means one or more, "a plurality" means two or more. "and/or" describes the association relationship of the associated object, indicating that there may be three relationships, for example, a and/or B, which may indicate: a exists alone, A and B exist simultaneously, and B exists alone, wherein A and B can be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, a and b, a and c, b and c or a, b and c, wherein a, b and c can be single or multiple. In addition, in the embodiments of the present application, the words "first", "second", and the like do not limit the number and order.

It is noted that, in the present application, words such as "exemplary" or "for example" are used to mean exemplary, illustrative, or descriptive. Any embodiment or design described herein as "exemplary" or "such as" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.

Before describing embodiments of the present application, a description will be given of background art to which the present application relates.

With the continuous development of high-speed signals, the link design of the high-speed signals becomes more and more challenging, and the testing of the high-speed signals becomes more and more important. Currently, an oscilloscope, an error code detector and a test fixture are generally used to perform corresponding tests on high-speed signals, such as an eye diagram test, an error code test and the like.

The test fixture is used for providing a test interface when a measuring instrument (an oscilloscope or an error code meter) cannot be directly coupled with a device to be tested so as to test a high-speed signal.

For example, as shown in FIG. 1, a test fixture 100 is shown, the test fixture 100 including a plurality of test interfaces 110 and a high speed serial computer expansion bus interface 120. The high-speed serial computer expansion bus interface 120 may also be referred to as a gold finger, the high-speed serial computer expansion bus interface 120 is configured to couple with a high-speed serial computer expansion bus slot in a device under test, and the plurality of test interfaces 110 correspond to a plurality of channels in the high-speed serial computer expansion bus slot and are configured to provide test interfaces for an oscilloscope or an error code detector.

Specifically, the eye pattern test circuit may include an oscilloscope and a test fixture, and the oscilloscope may receive the high-speed signal from the device to be tested through the test fixture to generate the eye pattern shown in fig. 2, which may be used to analyze the duty cycle, noise and jitter conditions of the high-speed signal. The error code testing circuit can comprise an error code instrument and a testing clamp, the error code instrument can send or receive high-speed signals from the device to be tested to the device to be tested through the testing clamp, and the error rate can be obtained according to errors of the sent and received high-speed signals. In order to perform a stable and repeatable test, the above-mentioned eye pattern test or error code test is generally performed using a test pattern as a high-speed signal.

For example, as shown in fig. 3, a block diagram of an eye pattern test circuit 300 is shown, the eye pattern test circuit 300 includes a main board 310, a test fixture 320, an oscilloscope 330, and a Personal Computer (PC) 340. The motherboard 310 is a device to be tested, the motherboard 310 is provided with a processor 311 and a high-speed serial computer expansion bus socket 312, which are coupled to each other, and the test fixture 320 includes a plurality of test interfaces 321 and a plurality of high-speed serial computer expansion bus interfaces 322. The personal computer 340 may be coupled to the processor 311 in the motherboard 310 through a network cable, the personal computer 340 may also be coupled to the oscilloscope 330 through a network cable, the oscilloscope 330 is coupled to one of the test interfaces 321 in the test fixture 320 through a coaxial cable connector 350 (or SMP connector), and the high-speed serial computer expansion bus interface 322 is coupled to the high-speed serial computer expansion bus socket 312. The personal computer 340 is configured to generate a control signal, the processor 311 generates a test pattern according to the control signal, the oscilloscope 330 receives the test pattern through the coaxial cable connector 350, and generates an eye pattern according to the test pattern, so that the personal computer 340 can analyze the duty cycle, noise, and jitter of the high-speed signal according to the eye pattern, and determine the quality of a Transmission (TX) link between the processor 311 and the oscilloscope 330.

For another example, the oscilloscope 330 in fig. 3 is replaced with the error detector 360 to construct a structure diagram of the error test circuit 400 shown in fig. 4. The personal computer 340 may be coupled to an error detector 360, and the error detector 360 is coupled to 2 test interfaces 321 in the test fixture 320 through a coaxial cable connector 350 and a coaxial cable connector 370. The personal computer 340 is configured to generate a control signal, the error detector 360 is configured to generate a first test pattern according to the control signal, the first test pattern is transmitted to the processor 311 through the coaxial cable connector 350, the processor 311 generates a second test pattern according to the first test pattern, the second test pattern is transmitted to the error detector 360 through the coaxial cable connector 370, the error detector 360 determines an error rate when a loop between the error detector 360 and the processor 311 transmits a high-speed signal according to the first test pattern and the second test pattern, and the personal computer 340 may determine a quality of a Receive X (RX) link between the error detector 360 and the processor 311 according to the error rate.

However, since the link between the processor 311 and the high-speed serial computer expansion bus slot 312 includes a plurality of channels, and the number of channels of the oscilloscope 330 and the error detector 360 is limited, it is necessary to connect different test interfaces 321 in the test fixture 320 by changing the connection position of the coaxial cable connector to complete the eye test or error test of the plurality of channels, which is complicated in operation and low in test efficiency. Moreover, as can be understood from fig. 3 and fig. 4, different test circuits need to be constructed for the eye pattern test and the error code test, and when the eye pattern test and the error code test need to be performed on multiple channels between the processor 311 and the high-speed serial computer expansion bus slot 312 at the same time, the structure of the test circuit needs to be changed, so that the operation is relatively complex, the test efficiency is low, and the requirement on the skills of test operators is high. Meanwhile, the oscilloscope 330, the error code meter 360 and the test fixture 320 for high-speed signal test are expensive, and the test cost is high.

In summary, the test circuit shown in fig. 3 or fig. 4 is relatively complex in operation, relatively low in test efficiency, relatively high in requirement for skills of a tester, and relatively high in test cost when testing a high-speed signal. Therefore, the embodiment of the application provides a testing device, which can improve the testing efficiency of the test and is convenient to operate.

Fig. 5 is a schematic diagram of an application scenario of a testing apparatus 500 according to an embodiment of the present application, where the testing apparatus 500 is used for testing signals in a device under test 600, and the testing apparatus 500 may include an interface circuit 510, a testing circuit 520, and a testing interface 530, and the interface circuit 510, the testing circuit 520, and the testing interface 530 are coupled.

In one possible embodiment, as shown in FIG. 5, the test apparatus 500 may include an interface circuit 510, a test circuit 520, and a test interface 530 coupled in sequence. In other embodiments, interface circuit 510, test circuit 520, and test interface 530 may be coupled to each other.

The structure of the testing device 500 in fig. 5 is an exemplary illustration, and is not limited to the embodiment of the present application.

Wherein the test interface 530 is used for receiving a test signal from the device under test 600. The test circuit 520 is used for determining a test result of the device under test 600 according to the test signal. The interface circuit 510 is used to send test results.

Optionally, the device under test 600 may include a server or a storage device, and the embodiment of the present application is not limited to a specific type of the device under test 600. For example, the device under test 600 may be a solid state disk.

The test device 500 provided by the embodiment of the application has a simple structure, and comprises the test circuit 520 and the test interface 530, wherein the test interface 530 is used for being butted with the device 600 to be tested, the test interface 530 receives a test signal from the device 600 to be tested, and the test circuit 520 is used for generating a test result according to the test signal. Meanwhile, compared with the test by adopting an oscilloscope or an error code meter, the test device of the embodiment is directly connected with the device to be tested, does not need to be connected with the oscilloscope or the error code meter through a coaxial cable connector, and does not need to change the connection position of the coaxial cable connector for many times, so the test operation can be simplified, and the test efficiency can be improved.

Optionally, the testing apparatus 500 provided in this embodiment of the present application may be used for high-speed signal testing, or may be used for low-speed signal testing, and whether the testing apparatus 500 specifically uses high-speed signal testing or low-speed signal testing is not limited in this embodiment of the present application, and the following embodiments exemplify that the testing apparatus 500 is used for high-speed signal testing.

Illustratively, when the testing apparatus 500 is used for high-speed signal testing, the device under test 600 may include a socket 610 and a processor 620 coupled to each other, the socket 610 is coupled to the testing interface 530, and the testing apparatus 500 is used for high-speed signal testing of a link between the socket 610 and the processor 620. The socket 610 is a high-speed signal socket.

Optionally, the test signal may be a test pattern, and a stable and repeatable test can be performed by using the test pattern, where the test pattern may include one of: pseudo-random binary sequence (PRBS) 31, PRBS7, PRBS9, PRBS11, PRBS15, PRBS20, and PRBS23.

Optionally, the testing apparatus 500 provided in this embodiment of the present application may be used for an eye pattern test, and generate an eye pattern and/or an eye pattern test conclusion to determine whether the quality of the transmission link between the processor 620 and the testing circuit 520 is qualified. Alternatively, test apparatus 500 may be used for error testing to determine the bit error rate to determine whether the quality of the receive link between processor 620 and test circuit 520 is acceptable.

In one possible embodiment, as shown in fig. 5, when the testing apparatus 500 is used for the eye pattern test, the test signal may be a first test pattern, and the test result includes eye pattern data (or may be referred to as an electronic eye pattern) and/or an eye pattern test conclusion, and the eye pattern test conclusion is used to indicate whether the eye pattern data meets a preset eye pattern test index.

Optionally, when the test result is the eye pattern data, the test circuit 520 is specifically configured to obtain the synchronous clock signal according to the first test pattern, determine the waveform data of multiple clock cycles according to the first test pattern and the synchronous clock signal, and determine the eye pattern data according to the waveform data of multiple clock cycles. When the test result is the eye pattern test conclusion, the test circuit 520 is further configured to determine the eye pattern test conclusion according to the eye pattern data and the preset eye pattern test index.

It is understood that, when the test result is eye pattern data, the control device 700 may receive the eye pattern data sent by the test device 500, perform analysis processing on the eye pattern data to generate an eye pattern test conclusion, and display the eye pattern test conclusion. When the test result is the eye pattern test conclusion, the control device 700 may receive the eye pattern test conclusion, and may directly display the eye pattern test conclusion without performing analysis processing.

For example, the link between socket 610 and processor 620 may include multiple channels, and socket 610 and test interface 530 may include the same number of multiple channels. When the test result is the eye pattern data, the processor 620 in the dut 600 may receive the first control signal, generate the first test pattern according to the first control signal, and send the first test pattern through any one of the channels of the socket 610. The test circuit 520 may receive a first test pattern via a corresponding channel in the test interface 530, determine eye pattern data according to the first test pattern, and send the eye pattern data via the interface circuit 510. It is understood that the processor 620 may perform the eye pattern test of all channels between the socket 610 and the test interface 530 by receiving different control signals multiple times to generate corresponding test patterns.

When the test result is the eye pattern test conclusion, the test circuit 520 may store a preset eye pattern test index, and the test circuit 520 may determine the eye pattern test conclusion according to the eye pattern data and the preset eye pattern test index, and send the eye pattern data and/or the eye pattern test conclusion through the interface circuit 510.

It is understood that the test device 500 provided in the embodiment of the present application receives the test signal generated by the processor 620 through the test interface 530 when performing the eye diagram test, where the test interface 530 includes a plurality of channels corresponding to the sockets 610. Therefore, in the process of performing the eye pattern test, the processor 620 can receive the test code patterns sent by different channels through corresponding channels in the test interface 530, so that the eye pattern test of all the channels between the socket 610 and the processor 620 can be completed without changing the connection position of the coaxial cable connector for many times, the operation is simple, the test efficiency can be improved, and the cost can be reduced without adopting the expensive oscilloscope 330 and the test fixture 320.

In another possible embodiment, as shown in fig. 6, when the testing apparatus 500 is used for error code testing, the testing signal is a second testing pattern, the testing result is error code information (or referred to as error rate), the interface circuit 510 is further configured to receive a second control signal, the testing circuit 520 is configured to generate a third testing pattern according to the second control signal, the testing interface 530 is further configured to send the third testing pattern to the apparatus to be tested 600, and the second testing pattern is sent by the apparatus to be tested 600 according to the received third testing pattern.

When the test result is error code information, the test circuit 520 is specifically configured to compare the second test pattern with the third test pattern bit by bit, determine the bit number of the error code of the second test pattern, and determine the error code information according to a ratio of the bit number of the error code to the total bit number of the third test pattern, thereby determining whether the quality of the receiving link between the processor 620 and the test circuit 520 is qualified.

For example, the link between the socket 610 and the processor 620 may include a plurality of channels, the socket 610 and the test interface 530 may include the same number of channels, and the test circuit 520 in the test apparatus 500 may receive the second control signal, generate a third test pattern according to the second control signal, and transmit the third test pattern through any one of the channels in the test interface 530. The processor 620 in the device under test 600 may receive the third test pattern through the corresponding channel in the socket 610, generate a second test pattern according to the third test pattern, and send the second test pattern through another channel in the socket 610. The test circuit 520 may receive the second test pattern through a corresponding channel in the test interface 530, compare the second test pattern with the third test pattern bit by bit, determine the bit number of the error code of the second test pattern, determine error code information according to a ratio of the bit number of the error code to the total bit number of the third test pattern, and send the error code information through the interface circuit 510. The test circuit 520 may receive different control signals for multiple times to generate corresponding test patterns, so as to complete error code testing of all channels between the socket 610 and the test interface 530.

It can be understood that, when the test apparatus 500 provided in the embodiment of the present application performs error test, the test circuit 520 sends the third test pattern through the test interface 530, and receives the second test pattern generated by the processor 620 through the test interface 530, where the test interface 530 includes a plurality of channels corresponding to the slots 610. Therefore, in the process of performing error code testing, the testing circuit 520 may send the testing code pattern to the processor 620 through different channels in the testing interface 530, or receive the testing code pattern generated by the processor 620, so that error code testing of all channels between the socket 610 and the processor 620 can be completed without changing the connection position of the coaxial cable connector many times, and therefore, the operation is simple, the testing efficiency can be improved, and meanwhile, the use of the expensive error code tester 360 and the testing fixture 320 is not required, and the cost can be reduced.

Alternatively, as shown in fig. 5 and 6, the first control signal and the second control signal may be generated by the control device 700. The control device 700 may be further configured to receive the eye pattern data and/or the eye pattern test result, generate and display an eye pattern and/or an eye pattern test result, or receive the error data and display an error rate. The control device may be an electronic device, such as a personal computer, a tablet computer, a mobile phone, etc.

Illustratively, when the testing apparatus 500 is used for performing an eye diagram test on a high-speed signal in the device under test 600, the control apparatus 700 may be coupled to the processor 620 and the interface circuit 510 in the device under test 600, the control apparatus 700 may be configured to generate the first control signal, and may be further configured to receive the eye diagram data to generate and display an eye diagram, further, a preset eye diagram test index may be stored in the control apparatus 700, and the control apparatus 700 may determine an eye diagram test conclusion according to the eye diagram and the preset eye diagram test index; alternatively, the control device 700 may be configured to receive the eye test result and display the eye test result; alternatively, the control device 700 may be configured to receive the eye pattern data and the eye pattern test conclusion, and generate and display the eye pattern and the eye pattern test conclusion. When the testing apparatus 500 is used to perform an error test on a high-speed signal in the apparatus to be tested 600, the control apparatus 700 may be coupled to the interface circuit 510 of the testing apparatus 500, and the control apparatus 700 may be configured to generate the second control signal and may be further configured to receive the error code information to display an error rate.

Optionally, the control device 700 may include control software for starting, suspending, stopping the test, collecting, analyzing the test data, and outputting the test report, for example, the control software may be used for generating the control signals such as the first control signal and the second control signal. Specifically, the method comprises the following steps. The test operator may select a test to be performed by clicking a virtual key in the control software, for example, the operator may select an eye test, or may select an error code test to control the testing apparatus 500 and the apparatus to be tested 600 to execute a corresponding instruction, so as to complete test contents such as the eye test or the error code test, receive a test result sent by the testing apparatus 500, analyze the test result, and generate a test report, thereby completing the test on the apparatus to be tested 600. Furthermore, the tester can also perform parameter bias and parameter optimization according to the test report generated by the control software, so that the test efficiency is improved.

Optionally, the interface circuit 510 may be an ethernet interface circuit, a serial communication interface circuit, a Universal Serial Bus (USB) interface circuit, or a wireless interface circuit, and the embodiment of the present application is not limited to a specific type of the interface circuit 510.

It can be understood that when the interface circuit 510 is a wireless interface circuit, the interface circuit 510 and the control device 700 do not need to be connected wirelessly through a wire, and compared with the wire connection, the positions of the control device 700 and the testing device 500 are not limited by a cable, so that the communication between the control device 700 and the testing device 500 is more conveniently established.

For example, when the interface circuit 510 is an ethernet interface circuit, the interface circuit 510 may include an ethernet interface and an ethernet interface chip; when the interface circuit 510 is a serial communication interface circuit, the interface circuit 510 may include a serial communication interface and a serial communication interface chip; when the interface circuit 510 is a universal serial bus interface circuit, the interface circuit 510 may include a universal serial bus interface and a universal serial bus interface chip; when the interface circuit is a wireless interface circuit, the interface circuit 510 may include a wireless chip.

For example, when the interface circuit 510 includes an ethernet interface and an ethernet interface chip, the ethernet interface may be a crystal header 45 (registered jack 45, rj-45) interface or a crystal header 11 (registered jack 11, rj-11) interface, and the ethernet interface chip may be a physical layer (PHY) chip. When the interface circuit 510 includes a serial communication interface and a serial communication chip, the serial communication interface may be an american electronic industry alliance 232 (RS 232) serial port chip, wherein the serial communication interface may be simply referred to as a serial port. When the interface circuit 510 includes a USB interface and a USB interface chip, the USB interface may be a USB2.0 interface or a USB3.0 interface, and the USB interface chip may be a USB2.0 interface chip or a USB3.0 interface chip. When the interface circuit 510 includes a wireless interface chip, the wireless interface chip may be a bluetooth (bluetooth) chip, a wireless fidelity (WIFi) chip, or a Zigbee (Zigbee) chip. In fig. 5 and 6, the interface circuit 510 is exemplified as a serial communication interface circuit, which includes a serial port 511 and an RS232 serial port chip 512.

Optionally, as shown in fig. 5 and fig. 6, the test circuit 520 may include a test chip 521, one end of the test chip 521 is coupled to the interface circuit 510, the other end of the test chip 521 is coupled to a test interface 530, and the test chip 521 is configured to determine a test result of the device under test 600 according to the test signal.

Optionally, the test chip 521 includes one of the following components: a high speed Clock and Data Recovery (CDR) chip, a signal driver (timer) chip, and a select (switch) chip, and the specific type of the test chip 521 is not limited in the embodiments of the present application.

Optionally, as shown in fig. 5 and fig. 6, the test circuit 520 may further include a clock circuit 522 and a reset circuit 523, where the clock circuit 522 and the reset circuit 523 are respectively coupled to the test chip 521. The clock circuit 522 is used for providing a clock for the test chip 521, and the reset circuit 523 is used for restoring the test chip 521 to an initial state when the test of each channel in the device under test is completed, so that the test device 500 can complete the test of all channels in the device under test 600.

Optionally, the test interface 530 (or referred to as a gold finger) is related to the type of the socket 610 in the device under test 600, and the test interface 530 may be designed as different types of interfaces according to the type of the socket 610. Test interface 530 may include one of: a high-speed serial computer expansion bus interface, a serial attached small computer system interface, a serial advanced technology attachment (sata) interface, a Card Electronics (CEM) interface, a non-volatile memory (NVME) interface, and an Open Core Protocol (OCP) interface. Thus, the test apparatus 500 can be supported to test high-speed signals such as a high-speed serial computer expansion bus signal, a serial attached small computer system interface signal, a serial advanced technology attachment signal, and a universal serial bus signal.

Illustratively, when the socket 610 is a high-speed serial computer expansion bus socket, the test interface 530 may be a high-speed serial computer expansion bus interface.

Optionally, when the test interface 530 is a high-speed serial computer expansion bus interface, the high-speed serial computer expansion bus interface may include 16 channels, 8 channels, 4 channels, or 1 channel, or may include more channels, and the specific number of channels included in the high-speed serial computer expansion bus interface is not limited in the embodiments of the present application.

Optionally, the testing apparatus 500 provided in this embodiment of the application may be configured to be in different forms according to the type of the testing interface, so as to be more conveniently used for testing the device under test 600, where the form of the testing apparatus 500 may include one of the following: the system comprises a high-speed serial computer expansion bus board card, an interface, an open core protocol board card, a 2.5-inch hard disk, a 3.5-inch hard disk or a U disk and the like.

In the testing apparatus 500 provided in the embodiment of the application, the testing interface 530 receives the testing signal sent by the apparatus to be tested 600, or the testing interface 530 receives the testing signal sent by the apparatus to be tested 600, where the testing interface 530 includes a plurality of channels corresponding to the slots 610 in the apparatus to be tested 600, so that in the testing process, the structure of the testing circuit does not need to be changed many times, the testing circuit 520 can receive the testing signal sent by any of the plurality of channels, and the testing result of the apparatus to be tested 600 can be determined according to the testing signal. Therefore, the operation is simple in the test process, the test efficiency can be improved, and meanwhile, the oscilloscope 330, the error code meter 360 and the test fixture 320 which are expensive are not needed, so that the cost can be reduced.

In one possible embodiment, as shown in FIG. 7, the test apparatus 500 may further include a power circuit 540, wherein an input of the power circuit 540 is coupled to the test interface 530, and an output of the power circuit 540 is coupled to the interface circuit 510 and the test interface 530.

The structure of the testing device 500 in fig. 7 is an exemplary illustration, and is not limited to the embodiment of the present application.

The power circuit 540 is used to power the interface circuit 510 and the test circuit 520.

Specifically, the power circuit 540 is configured to receive a supply voltage from the test interface 530, and when the supply voltage is different from the supply voltages required by the interface circuit 510 and the test circuit 520, the received supply voltage may be voltage-converted to generate the supply voltages required by the interface circuit 510 and the test circuit 520.

Alternatively, the required supply voltages of the interface circuit 510 and the test circuit 520 may be the same, or the required supply voltages may be different, which is not limited in this embodiment of the application, and the following embodiments exemplify that the required supply voltages of the interface circuit 510 and the test circuit 520 are different supply voltages.

For example, referring to fig. 7, when the supply voltages required by the interface circuit 510 and the test circuit 520 are different, the first output terminal of the power supply circuit 540 is coupled to the RS232 serial port chip in the interface circuit 510, and the second output terminal of the power supply circuit 540 is coupled to the test chip 521. For example, the power supply circuit 540 receives a 12V power supply voltage provided by the device to be tested 600 through the test interface 530, the RS232 serial port chip in the interface circuit 510 needs a 1.8V power supply voltage, and the test chip 521 needs a 3.3V power supply voltage, and the power supply circuit 540 can generate the 1.8V power supply voltage needed by the RS232 serial port chip in the interface circuit 510 and also generate the 3.3V power supply voltage needed by the test chip 521 according to the 12V power supply voltage.

In the test apparatus 500 provided in the embodiment of the present application, the power supply circuit 540 processes the power supply voltage received by the test interface 530, so that a stable power supply voltage can be provided for the interface circuit 510 and the test circuit 520.

In other embodiments, the power circuit 540 may be coupled to the interface circuit 510, and the interface circuit 510 may receive a supply voltage from the control device 700, and when the supply voltage is different from the supply voltages required by the interface circuit 510 and the test circuit 520, the received supply voltage may be voltage converted to generate the supply voltages required by the interface circuit 510 and the test circuit 520.

In other embodiments, the power circuit 540 may provide only a steady supply voltage to the interface circuit 510, or the power circuit 540 may provide only a steady supply voltage to the test circuit 520. Based on this, as shown in fig. 8, an embodiment of the present application further provides a testing apparatus 800, where the testing apparatus 800 is used for testing a device under test 900, and the testing apparatus 800 includes a control device 810 and a testing device 820 coupled to each other. Wherein the control device 810 and the test device 820 are respectively coupled with the device under test 900. The test apparatus 820 may have a structure as the test apparatus 500 shown in fig. 5, 6 and 7.

It should be noted that the structure of the test apparatus 800 in fig. 8 is an exemplary illustration, and does not limit the embodiments of the present application.

The control device 810 is configured to send a control signal, the device under test 900 is configured to send a test signal according to the control signal, the test device 820 is configured to determine a test result of the device under test 900 according to the test signal, and the control device 810 is further configured to receive the test result.

Optionally, the test apparatus 800 provided in this embodiment of the present application may be used for high-speed signal testing, or may be used for low-speed signal testing, and this embodiment of the present application is not limited to whether the test apparatus 800 specifically uses high-speed signal testing or low-speed signal testing.

Optionally, the test apparatus 800 provided in this embodiment of the present application may be used for an eye diagram test, and generate an eye diagram and/or an eye diagram test conclusion to determine the quality of a transmission link of the device under test 900, where the test result is the eye diagram and/or the eye diagram test conclusion; alternatively, it can be used for error testing to determine the error information (bit error rate) to determine the quality of the link received by the dut 900, and the test result is the error information.

Optionally, the control device 810 may include control software for starting, suspending, stopping the test, collecting, analyzing the test data, and outputting the test report, for example, the control software may be used for generating the control signals such as the first control signal and the second control signal. Specifically, the method comprises the following steps. The test operator may select a test to be performed by clicking a virtual key in the control software, for example, the operator may select an eye test, or may select an error code test to control the testing device 820 and the device to be tested 900 to execute a corresponding instruction, so as to complete test contents such as the eye test or the error code test, receive a test result sent by the testing device 820, analyze the test result, generate a test report, and complete the test on the device to be tested 900. Furthermore, the tester can also perform parameter bias and parameter optimization according to the test report generated by the control software, so that the test efficiency is improved.

Illustratively, the control device 810 can adjust the pre-emphasis according to the eye pattern and/or the eye pattern test conclusion, and the bit error rate, so as to improve the quality of the high-speed signal transmitted by the device under test 900. The pre-emphasis is a signal processing mode for compensating the high-frequency component of the high-speed signal when the high-speed signal is sent, and the loss of the high-speed signal in the transmission process can be compensated by adjusting the pre-emphasis, so that the quality of the high-speed signal can be improved.

Optionally, the control device 810 is an electronic device. For example, the electronic device may be a personal computer, a tablet computer, a mobile phone, and the like.

Optionally, the device under test 900 may include a motherboard 910, and the motherboard 910 may be provided with a processor 911 and a socket 912.

The testing device 820 includes a testing interface 821, and the testing interface 821 is used for coupling with a socket 912 in the device under test 900.

Optionally, the test interface 821 may include one of: the system comprises a high-speed serial computer expansion bus interface, a serial connection small computer system interface, a serial advanced technology attachment interface, a card machine electrical interface, a nonvolatile memory standard interface and an open core protocol interface. Thereby, the test equipment 900 can be supported to test high-speed signals such as high-speed serial computer expansion bus signals, serial connection small computer system interface signals, serial advanced technology attachment signals, universal serial bus signals and the like.

Optionally, the test signal is a test pattern, and a stable and repeatable test can be performed by using the test pattern, where the test pattern may include one of: PRBS31, PRBS7, PRBS9, PRBS11, PRBS15, PRBS20, and PRBS23.

In a possible embodiment, as shown in fig. 9, the control device 810 may be integrated in the testing device 820, the testing apparatus 800 may further include a human-machine interface 830, the human-machine interface 830 is coupled with the control device 810, a testing operator may control the testing apparatus to test the device to be tested 900 by clicking a virtual key in the human-machine interface 830, and the human-machine interface 830 may also be used to display a testing result.

In the test apparatus 800 provided in this embodiment of the application, the test device 820 determines the test result of the device to be tested 900 according to the test signal, the test device 820 is coupled to the device to be tested 900 through the test interface 821 and the socket 912, the test interface 821 includes a plurality of channels corresponding to the socket 912, so that in the test process, the structure of the test circuit does not need to be changed many times, the test device 820 can receive the test signal in the device to be tested 900, the test result can be determined according to the test signal, and the control device 810 can display the test result eye diagram and/or the eye diagram test conclusion according to the test result, or display the error rate, so that the quality of the transmission link and the reception link of the device to be tested 900 can be determined. Compared with the prior art, the connection position of the coaxial cable connector does not need to be changed for many times in the test process, so the operation is simple, the test efficiency can be improved, and meanwhile, the cost can be reduced without adopting the expensive oscilloscope 330, error code meter 360 and test fixture 320. It should be noted that, the descriptions related to the testing apparatus 500 in the above embodiments of the apparatus can be correspondingly incorporated into the embodiment of the testing device 800, and the embodiments of the present application are not repeated herein.

The above description is only an embodiment of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions within the technical scope disclosed in the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. A test device, comprising: interface circuit, test circuit and test interface, interface circuit, test circuit and the test interface coupling, wherein:

the test interface is used for connecting a device to be tested;

the test interface is used for receiving a test signal from the device to be tested;

the test circuit is used for determining a test result of the device to be tested according to the test signal;

the interface circuit is used for sending the test result.

2. The test device according to claim 1, wherein the test signal is a first test pattern, the test result includes eye pattern data and/or an eye pattern test conclusion, and the eye pattern test conclusion is used to indicate whether the eye pattern data meets a preset eye pattern test index.

3. The testing apparatus of claim 2, wherein when the test result is the eye pattern data, the testing circuit is specifically configured to obtain a synchronous clock signal according to the first test pattern, determine waveform data of a plurality of clock cycles according to the first test pattern and the synchronous clock signal, and determine the eye pattern data according to the waveform data of the plurality of clock cycles;

or when the test result is the eye pattern test conclusion, the test circuit is further configured to determine the eye pattern test conclusion according to the eye pattern data and the preset eye pattern test index.

4. The test apparatus of claim 1, wherein the test signal is a second test pattern, and the test result is error code information;

the interface circuit is also used for receiving a control signal;

the test circuit is also used for generating a third test code pattern according to the control signal;

the test interface is further configured to send the third test pattern to the device to be tested, where the second test pattern is obtained by converting the third test pattern by the device to be tested.

5. The test apparatus of claim 4, wherein the test circuit is specifically configured to compare the second test pattern and the third test pattern bit by bit, determine the number of bit errors of the second test pattern, and determine the error code information according to a ratio of the number of bit errors to a total number of bit errors of the third test pattern.

6. The test device of any one of claims 1-5, wherein the test circuit comprises a test chip having one end coupled to the test interface and another end coupled to the interface circuit.

7. The test device of claim 6, wherein the test chip comprises a high speed clock data recovery chip, a signal driver chip, or a selection chip.

8. The test apparatus of claim 6 or 7, wherein the test circuit further comprises a clock circuit and a reset circuit, the clock circuit and the reset circuit being respectively coupled to the test chip.

9. The test device of any one of claims 1-8, further comprising a power supply circuit;

the input end of the power supply circuit is coupled with the test interface, and the output end of the power supply circuit is coupled with the interface circuit and the test circuit.

10. A test apparatus for testing a device under test, the test apparatus comprising a control device and a test device coupled to each other, the test device being a test device according to any one of claims 1-9;

the control device is used for sending a control signal to the device to be tested;

the testing device is used for receiving a testing signal sent by the device to be tested according to the control signal and determining a testing result of the device to be tested according to the testing signal;

the control device is also used for receiving the test result.

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