CN115237094A - A test device and test equipment - Google Patents

Abstract

The embodiments of the present application disclose a testing device and testing equipment, which can simplify testing operations and improve testing efficiency. The specific scheme is: to provide a test device, the test device includes an interface circuit, a test circuit and a test interface, and the interface circuit, the test circuit and the test interface are coupled. The test interface is used to connect the device to be tested. The test interface is used for receiving the test signal from the device to be tested, the test circuit is used for determining the test result of the device to be tested according to the test signal, and the interface circuit is used for sending the test result.

Description

A test device and test equipment

technical field

The embodiments of the present application relate to the field of electronic technologies, and in particular, to a testing device and testing equipment.

Background technique

With the development of high-speed signal technology, many types of high-speed signals have appeared, such as high-speed serial computer expansion bus (peripheral component interconnect express, PCIE) signals, serial attached small computer system interface (serial attached small computer system interface, SAS) ) signal, serial advanced technology attachment (serial advanced technology attachment, SATA) signal and other high-speed signals. With the continuous development of high-speed signals, the challenges of link design of high-speed signals are increasing, and the testing of high-speed signals is becoming more and more important.

For example, a processor and a high-speed serial computer expansion bus slot are coupled to each other on the motherboard of the server, and the link between the processor and the high-speed serial computer expansion bus slot is used to transmit high-speed signals. The signal is tested for eye diagram and bit error rate. However, the current testing method is complicated to operate and has low testing efficiency.

SUMMARY OF THE INVENTION

Embodiments of the present application provide a testing device and testing equipment, which can simplify testing operations and improve testing efficiency.

In order to achieve the above purpose, the embodiment of the present application adopts the following technical solutions:

In a first aspect of the embodiments of the present application, a test device is provided. The test device includes: an interface circuit, a test circuit, and a test interface, and the interface circuit, the test circuit, and the test interface are coupled. The test interface is used to connect the device to be tested. The test interface is used for receiving the test signal from the device to be tested, the test circuit is used for determining the test result of the device to be tested according to the test signal, and the interface circuit is used for sending the test result.

The test device provided by the embodiment of the present application includes a test circuit and a test interface, the test interface is used for docking with the device to be tested, and a test signal from the device to be tested is received through the test interface, and the test circuit is used to generate a test result according to the test signal. The structure of the device is simple and the test method is simple, and the test cost is reduced compared with the use of an expensive oscilloscope or a bit error tester for testing to generate test results. At the same time, compared with using an oscilloscope or a bit error tester for testing, the test device in this embodiment is directly connected to the device to be tested, and does not need to be connected to the oscilloscope or the bit error tester through a coaxial cable connector, nor does it need to change the same The connection position of the coaxial cable connector can simplify the test operation and improve the test efficiency.

With reference to the first aspect, in a possible implementation manner, the test signal is a first test pattern, the test result includes eye pattern data and/or an eye pattern test conclusion, and the eye pattern test conclusion is used to indicate whether the eye pattern data is Meet the preset eye diagram test specifications.

The test device provided by the embodiment of the present application receives the test signal from the device to be tested through the test interface, and generates eye diagram data and/or eye diagram test conclusion through the test circuit. It is directly connected to the device to be tested, and does not need to be connected to the oscilloscope through the coaxial cable connector, nor does it need to change the connection position of the coaxial cable connector many times, so it can simplify the test operation, improve the test efficiency, and reduce the test cost. .

In combination with the first aspect, in a possible implementation manner, when the test result is eye diagram data, the test circuit is specifically configured to obtain a synchronization clock signal according to the first test pattern, and determine the synchronization clock signal according to the first test pattern and the synchronization clock signal. Waveform data of multiple clock cycles, and eye diagram data is determined according to waveform data of multiple clock cycles. Alternatively, when the test result is an eye-diagram test conclusion, the test circuit is further configured to determine the eye-diagram test conclusion according to the eye-diagram data and the preset eye-diagram test index.

The test device provided by the embodiment of the present application receives the first test pattern from the device to be tested through the test interface, and generates eye diagram data and/or eye diagram test conclusion through the test circuit. The test device is directly connected to the device to be tested, and does not need to be connected to the oscilloscope through the coaxial cable connector, nor does it need to change the connection position of the coaxial cable connector many times, which can simplify the test operation, improve the test efficiency, and reduce the cost of testing.

With reference to the first aspect, in a possible implementation manner, the above-mentioned test signal is a second test pattern, and the above-mentioned test result is bit error information. The interface circuit is also used to receive the control signal, the test circuit is also used to generate a third test pattern according to the control signal, the test interface is also used to send the third test pattern to the device to be tested, and the second test pattern is the basis of the device to be tested. The third test pattern is converted and obtained.

The test device provided by the embodiment of the present application receives the second test pattern from the device to be tested through the test interface, generates bit error information according to the second test pattern and the third test pattern through the test circuit, and performs the test by using the bit error meter. Compared with the test, the test device of this embodiment is directly connected to the device to be tested, and does not need to be connected to the BERT through the coaxial cable connector, nor does it need to change the connection position of the coaxial cable connector many times, which can simplify the test operation. , can improve the test efficiency, and can reduce the test cost.

In combination with the first aspect, in a possible implementation manner, the above-mentioned test circuit is specifically used to compare the second test pattern and the third test pattern bit by bit to determine the number of error bits of the second test pattern, according to The ratio of the number of error bits to the total number of bits of the third test pattern determines error information.

The test device provided by the embodiment of the present application receives the second test pattern from the device to be tested through the test interface, generates bit error information according to the second test pattern and the third test pattern through the test circuit, and performs the test by using the bit error meter. Compared with the test, the test device of this embodiment is directly connected to the device to be tested, and does not need to be connected to the BERT through the coaxial cable connector, nor does it need to change the connection position of the coaxial cable connector many times, which can simplify the test operation. , can improve the test efficiency, and can reduce the test cost.

With reference to the first aspect, in a possible implementation manner, the test circuit includes a test chip, one end of the test chip is coupled to the test interface, and the other end of the test chip is coupled to the interface circuit.

In the test device provided by the embodiments of the present application, the test chip generates test results according to the test signal, and does not need to use an expensive oscilloscope and a bit error tester to generate the test results, so the test cost can be reduced. At the same time, compared with using an oscilloscope or a bit error tester for testing, the test device in this embodiment is directly connected to the device to be tested, and does not need to be connected to the oscilloscope or the bit error tester through a coaxial cable connector, nor does it need to change the same The connection position of the axial cable connector can simplify the test operation and improve the test efficiency.

With reference to the first aspect, in a possible implementation manner, the above-mentioned test chip includes a high-speed clock data recovery chip, a signal driver chip or a selection chip.

With reference to the first aspect, in a possible implementation manner, the test circuit further includes a clock circuit and a reset circuit, and the clock circuit and the reset circuit are respectively coupled to the test chip.

In the test device provided by the embodiment of the present application, the clock circuit is used to provide a clock for the test chip, and the reset circuit restores the test chip to the initial state when the test of each channel in the device to be tested is completed, so that the test device can complete all channels in the device to be tested. test without the need for expensive oscilloscopes and bit error meters to generate test results, thus reducing test costs. At the same time, compared with using an oscilloscope or a bit error tester for testing, the test device in this embodiment is directly connected to the device to be tested, and does not need to be connected to the oscilloscope or the bit error tester through a coaxial cable connector, nor does it need to change the same The connection position of the axial cable connector can simplify the test operation and improve the test efficiency.

With reference to the first aspect, in a possible implementation manner, the test device further includes a power supply circuit, an input end of the power supply circuit is coupled to the test interface, and an output end of the power supply circuit is coupled to the interface circuit and the test circuit.

The test device provided by the embodiment of the present application processes the power supply voltage received by the test interface through the power supply circuit, so that a stable power supply voltage can be provided for the interface circuit and the test circuit.

In combination with the first aspect, in a possible implementation, the above-mentioned test interface includes a high-speed serial computer expansion bus interface, a serial connection to a small computer system interface, a serial advanced technology accessory interface, a card electromechanical interface, and a non-volatile memory. Standard interface or open core protocol interface.

The test device provided by the embodiment of the present application can support the test device to expand the bus signal of the high-speed serial computer, serially connect the interface signal of the small computer system, serial High-speed signals such as advanced technology accessory signals and universal serial bus signals are tested.

With reference to the first aspect, in a possible implementation manner, the above-mentioned interface circuit includes an Ethernet interface circuit, a serial communication interface circuit, a universal serial bus interface circuit, or a wireless interface circuit.

The test device provided by the embodiment of the present application can support different types of control devices by setting the interface circuit into multiple types of interface circuits. For example, the control device can be a personal computer, a tablet computer, a mobile phone, and the like.

In a second aspect of the embodiments of the present application, a test equipment is provided. The test equipment is used to test a device to be tested. The test equipment includes a control device and a test device. One end of the control device is coupled to the test device, and the other end of the control device is used for The device to be tested is connected, and the structure of the test device is the structure of the test device described in the first aspect or any possible implementation manner of the first aspect. The control device is used to send a control signal to the device to be tested, and the test device is used to receive the test signal sent by the device to be tested according to the control signal, and to determine the test result of the device to be tested according to the test signal. The control device is also used to receive test results.

For the description of the second aspect in this application, reference may be made to the detailed description of the first aspect; and, for the beneficial effects of the second aspect, reference may be made to the analysis of the beneficial effects of the first aspect, which will not be repeated here.

Description of drawings

Fig. 1 is the structural representation of a kind of test fixture;

FIG. 2 is a schematic diagram of an eye diagram curve;

3 is a schematic structural diagram of an eye-diagram test circuit;

4 is a schematic structural diagram of a bit error test circuit;

5 is a schematic diagram of an application scenario of a test device provided by an embodiment of the present application;

FIG. 6 is a schematic diagram of another test device application scenario provided by an embodiment of the present application;

7 is a schematic structural diagram of a testing device provided by an embodiment of the present application;

FIG. 8 is a schematic diagram of an application scenario of a test equipment provided by an embodiment of the present application;

FIG. 9 is a schematic structural diagram of a testing device provided by an embodiment of the present application.

Detailed ways

The making and using of the various embodiments are discussed in detail below. It should be appreciated, however, that many of the applicable inventive concepts provided herein can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the description and the technology, and do not limit the scope of the application.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art.

Various circuits or other components may be described or referred to as "for" performing one or more tasks. In this context, "for" is used to connote structure by indicating that the circuit/component includes structure (eg, circuitry) that performs one or more tasks during operation. Thus, the specified circuit/component may be said to be used to perform the task even when the specified circuit/component is not currently operational (eg, not turned on). Circuits/components used with the phrase "for" include hardware, such as circuits that perform operations, and the like.

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. In this application, "at least one" means one or more, and "plurality" means two or more. "And/or", which describes the association relationship of the associated objects, indicates that there can be three kinds of relationships, for example, A and/or B, which can indicate: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A, B can be singular or plural. The character "/" generally indicates that the associated objects are an "or" relationship. "At least one item(s) below" or similar expressions thereof refer to any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (a) of a, b or c may represent: a, b, c, a and b, a and c, b and c or a, b and c, where a, b and c can be It can be single or multiple. In addition, in the embodiments of the present application, words such as "first" and "second" do not limit the quantity and order.

It should be noted that, in this application, words such as "exemplary" or "for example" are used to represent examples, illustrations or illustrations. Any embodiment or design described in this application as "exemplary" or "such as" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present the related concepts in a specific manner.

Before introducing the embodiments of the present application, the background technology involved in the present application is first introduced and explained.

With the continuous development of high-speed signals, the challenges of link design of high-speed signals are increasing, and the testing of high-speed signals is becoming more and more important. At present, high-speed signals are generally tested by oscilloscope, bit error tester and test fixture, such as eye diagram test and bit error test.

Among them, the test fixture is used to provide a test interface when the measuring instrument (oscilloscope or bit error tester) cannot be directly coupled with the device to be tested, so as to complete the test of the high-speed signal.

For example, as shown in FIG. 1 , a test fixture 100 includes a plurality of test interfaces 110 and a high-speed serial computer expansion bus interface 120 . The high-speed serial computer expansion bus interface 120 may also be called a golden finger, and the high-speed serial computer expansion bus interface 120 is used for coupling with the high-speed serial computer expansion bus slot in the device to be tested. The multiple test interfaces 110 are connected to Multiple channels in the high-speed serial computer expansion bus slot correspond to provide a test interface for an oscilloscope or BERT.

Specifically, the eye diagram test circuit may include an oscilloscope and a test fixture. The oscilloscope may receive a high-speed signal from the device to be tested through the test fixture to generate an eye diagram as shown in Figure 2, which can be used to analyze the duty cycle of the high-speed signal. , noise and jitter conditions. The bit error test circuit can include a bit error tester and a test fixture. The bit error tester can send or receive high-speed signals from the device to be tested through the test fixture. According to the error of the transmitted and received high-speed signals, the bit error rate can be obtained. . In order to perform stable and repeatable testing, the test pattern is generally used as a high-speed signal to perform the above-mentioned eye diagram test or bit error test.

For example, as shown in FIG. 3 , a structural diagram of an eye-diagram test circuit 300 includes a main board 310 , a test fixture 320 , an oscilloscope 330 and a personal computer (PC) 340 . The mainboard 310 is the device to be tested. The mainboard 310 is provided with a mutually coupled processor 311 and a high-speed serial computer expansion bus slot 312 . The test fixture 320 includes multiple test interfaces 321 and high-speed serial computer expansion bus interfaces 322 . The personal computer 340 can be coupled with the processor 311 in the main board 310 through a network cable, the personal computer 340 can also be coupled with the oscilloscope 330 through a network cable, and the oscilloscope 330 can be connected to the test fixture 320 through a coaxial cable connector 350 (or SMP connector). A test interface 321 of the high-speed serial computer expansion bus interface 322 is coupled with the high-speed serial computer expansion bus slot 312. The personal computer 340 is used to generate a control signal, the processor 311 generates a test pattern according to the control signal, the oscilloscope 330 receives the test pattern through the coaxial cable connector 350, and generates an eye diagram according to the test pattern, so that the personal computer 340 can The eye diagram analyzes the duty cycle, noise and jitter of the high-speed signal, and determines the quality of the transmit (transport x, TX) link between the processor 311 and the oscilloscope 330 .

For another example, the oscilloscope 330 in the above-mentioned FIG. 3 is replaced with the bit error meter 360 to construct the structure diagram of the bit error test circuit 400 as shown in FIG. 4 . The personal computer 340 can be coupled with the bit error tester 360, and the bit error tester 360 is coupled to the two test interfaces 321 in the test fixture 320 through the coaxial cable connector 350 and the coaxial cable connector 370, respectively. The personal computer 340 is used to generate a control signal, and the bit error detector 360 is used to generate a first test pattern according to the control signal, and the first test pattern is transmitted to the processor 311 through the coaxial cable connector 350, and the processor 311 according to the The first test pattern generates a second test pattern, and the second test pattern is transmitted to the bit error tester 360 through the coaxial cable connector 370, and the bit error tester 360 determines according to the first test pattern and the second test pattern. The bit error rate between the BER 360 and the processor 311 when the high-speed signal is transmitted in a loop, the personal computer 340 can judge the receive (RX, RX) link between the BER 360 and the processor 311 according to the bit error rate the quality of.

However, since the link between the processor 311 and the high-speed serial computer expansion bus slot 312 includes multiple channels, while the number of channels of the oscilloscope 330 and the BERT 360 is limited, it is necessary to change the connection position of the coaxial cable connector , so as to connect different test interfaces 321 in the test fixture 320 to complete the eye diagram test or bit error test of the above-mentioned multiple channels, which is complicated in operation and low in test efficiency. Moreover, it can be understood from the above-mentioned FIG. 3 and FIG. 4 that different test circuits need to be constructed for the eye diagram test and the bit error test. When multiple channels between the processor 311 and the high-speed serial computer expansion bus slot 312 are required to When performing eye diagram test and bit error test, the structure of the test circuit needs to be changed, the operation is complicated, the test efficiency is low, and the skills of test operators are high. At the same time, the oscilloscope 330, the bit error tester 360 and the test fixture 320 used for high-speed signal testing are expensive and the testing cost is high.

To sum up, when the test circuit shown in FIG. 3 or FIG. 4 is used to test high-speed signals, the operation is relatively complicated, the test efficiency is low, the skill requirements of testers are high, and the test cost is high. Therefore, the embodiment of the present application provides a test device, which can improve the test efficiency of the test and is convenient to operate.

FIG. 5 is a schematic diagram of an application scenario of a test device 500 provided by an embodiment of the application. The test device 500 is used to test signals in the device to be tested 600. The test device 500 may include an interface circuit 510, a test circuit 520 and a test The interface 530, the interface circuit 510, the test circuit 520 and the test interface 530 are coupled.

In a possible embodiment, as shown in FIG. 5 , the test device 500 may include an interface circuit 510 , a test circuit 520 and a test interface 530 coupled in sequence. In other embodiments, the interface circuit 510 , the test circuit 520 and the test interface 530 may also be coupled in pairs.

It should be noted that the structure of the testing device 500 in FIG. 5 above is illustrative, and does not constitute a limitation to the embodiments of the present application.

The test interface 530 is used for receiving test signals from the device under test 600 . The test circuit 520 is used to determine the test result of the device under test 600 according to the test signal. The interface circuit 510 is used for sending test results.

Optionally, the device to be tested 600 may include a server or a storage device, and the embodiment of the present application does not limit the specific type of the device to be tested 600 . For example, the device to be tested 600 may be a solid state drive.

The test device 500 provided by the embodiment of the present application has a simple structure, including a test circuit 520 and a test interface 530. The test interface 530 is used for docking with the device to be tested 600, and receives a test signal from the device to be tested 600 through the test interface 530. The test circuit 520 is used to generate test results according to the test signal. The test device 500 has a simple structure and a simple test method. Compared with using an expensive oscilloscope and a bit error tester for testing to generate test results, the test cost is reduced and the test accuracy is improved. efficiency. At the same time, compared with using an oscilloscope or a bit error tester for testing, the test device in this embodiment is directly connected to the device to be tested, and does not need to be connected to the oscilloscope or the bit error tester through a coaxial cable connector, nor does it need to change the same The connection position of the coaxial cable connector can simplify the test operation and improve the test efficiency.

Optionally, the test device 500 provided in the embodiment of the present application may be used for high-speed signal testing, or may be used for low-speed signal testing. The embodiment of the present application does not limit whether the test device 500 specifically uses high-speed signal testing or low-speed signal testing. The following embodiments take the test device 500 for high-speed signal testing as an example for illustrative description.

Exemplarily, when the test device 500 is used for high-speed signal testing, the above-mentioned device to be tested 600 may include a socket 610 and a processor 620 coupled to each other, the socket 610 is coupled to the test interface 530, and the test device 500 is used for testing the socket. The link between 610 and processor 620 is tested for high speed signals. The slot 610 is a high-speed signal slot.

Optionally, the above-mentioned test signal may be a test pattern, and a stable and repeatable test can be performed by using the test pattern, and the test pattern may include one of the following: a pseudo-random binary sequence (PRBS) )31, PRBS7, PRBS9, PRBS11, PRBS15, PRBS20 and PRBS23.

Optionally, the test apparatus 500 provided in this embodiment of the present application may be used for eye diagram testing to generate an eye diagram and/or an eye diagram test conclusion to determine whether the quality of the transmission link between the processor 620 and the test circuit 520 is qualified. Alternatively, the testing apparatus 500 can be used for bit error testing, and the bit error rate is determined to determine whether the quality of the receiving link between the processor 620 and the testing circuit 520 is qualified.

In a possible embodiment, as shown in FIG. 5 , when the test device 500 is used for eye diagram testing, the above-mentioned test signal may be a first test pattern, and the above-mentioned test result includes eye diagram data (or may be referred to as an electronic eye) Figure) and/or the eye-diagram test conclusion, the eye-diagram test conclusion is used to indicate whether the eye-diagram data meets the preset eye-diagram test index.

Optionally, when the test result is eye diagram data, the test circuit 520 is specifically configured to obtain the synchronization clock signal according to the first test pattern, determine waveform data of multiple clock cycles according to the first test pattern and the synchronization clock signal, and determine the waveform data of multiple clock cycles according to the first test pattern and the synchronization clock signal. The waveform data for multiple clock cycles determines the eye diagram data. When the test result is the eye-diagram test conclusion, the test circuit 520 is further configured to determine the eye-diagram test conclusion according to the eye-diagram data and the preset eye-diagram test index.

It can be understood that when the test result is eye pattern data, the control device 700 can receive the eye pattern data sent by the testing device 500, analyze and process the eye pattern data to generate an eye pattern test conclusion, and display the eye pattern test conclusion. When the test result is the eye-diagram test conclusion, the control device 700 can receive the eye-diagram test conclusion without analyzing and processing, and can directly display the eye-diagram test conclusion.

For example, the link between socket 610 and processor 620 may include multiple channels, and socket 610 and test interface 530 may include the same number of multiple channels. When the test result is eye pattern data, the processor 620 in the device under test 600 may receive the first control signal, generate the first test pattern according to the first control signal, and pass any of the multiple channels of the slot 610 through the first test pattern. One channel transmits the above-mentioned first test pattern. The test circuit 520 may receive the first test pattern through the corresponding channel in the test interface 530 , determine the eye pattern data according to the first test pattern, and send the eye pattern data through the interface circuit 510 . It can be understood that the processor 620 generates corresponding test patterns by receiving different control signals multiple times, so as to complete the eye pattern test of all channels between the socket 610 and the test interface 530 .

When the test result is an eye-diagram test conclusion, the test circuit 520 may store a preset eye-diagram test index, and the test circuit 520 can determine the eye-diagram test conclusion according to the above-mentioned eye-diagram data and the preset eye-diagram test index, and pass the interface circuit 510 transmits the above eye diagram data and/or eye diagram test conclusion.

It can be understood that when the test device 500 provided in this embodiment of the present application performs the eye diagram test, the test signal generated by the processor 620 is received through the test interface 530 , and the test interface 530 includes multiple channels corresponding to the slot 610 . Therefore, in the process of performing the eye diagram test, the test patterns sent by the processor 620 through different channels can be received by the test circuit 520 through the corresponding channels in the test interface 530, so that the connection between the socket 610 and the processor 620 can be completed. The eye diagram test of all channels does not need to change the connection position of the coaxial cable connector many times, so the operation is simple, the test efficiency can be improved, and the expensive oscilloscope 330 and the test fixture 320 are not required, which can reduce the cost.

In another possible embodiment, as shown in FIG. 6 , when the test device 500 is used for bit error testing, the above-mentioned test signal is the second test pattern, and the above-mentioned test result is bit error information (or called bit error code). rate), the interface circuit 510 is further configured to receive the second control signal, the test circuit 520 is configured to generate a third test pattern according to the second control signal, and the test interface 530 is further configured to send the third test pattern to the device under test 600 , the second test pattern is sent by the device under test 600 according to the received third test pattern.

When the test result is bit error information, the test circuit 520 is specifically configured to compare the second test pattern and the third test pattern bit by bit to determine the number of bits of the error in the second test pattern, and according to the number of bits of the error and the ratio of the total number of bits of the third test pattern to determine the bit error information, thereby judging whether the quality of the receiving link between the processor 620 and the test circuit 520 is qualified.

For example, the link between the socket 610 and the processor 620 may include multiple channels, the socket 610 and the test interface 530 may include multiple channels of the same number, and the test circuit 520 in the test device 500 may receive the second control signal, generate a third test pattern according to the second control signal, and send the third test pattern through any channel in the test interface 530 . The processor 620 in the device under test 600 can receive the third test pattern through the corresponding channel in the slot 610 , generate the second test pattern according to the third test pattern, and send the third test pattern through another channel in the slot 610 . The second test pattern. The test circuit 520 can receive the second test pattern through the corresponding channel in the test interface 530, compare the second test pattern and the third test pattern bit by bit, and determine the number of error bits of the second test pattern, The bit error information is determined according to the ratio of the number of error bits to the total number of bits of the third test pattern, and the bit error information is sent through the interface circuit 510 . The test circuit 520 generates corresponding test patterns by receiving different control signals multiple times, so as to complete the bit error test of all channels between the slot 610 and the test interface 530 .

It can be understood that when the test device 500 provided in the embodiment of the present application performs the bit error test, the test circuit 520 sends the third test pattern through the test interface 530, and receives the second test pattern generated by the processor 620 through the test interface 530, The test interface 530 includes a plurality of channels corresponding to the slot 610 . Therefore, in the process of performing the bit error test, the test circuit 520 can send the test pattern to the processor 620 through different channels in the test interface 530, or receive the test pattern generated by the processor 620, so as to complete the slot 610 and the processing Bit error test of all channels between the 620 devices without changing the connection position of the coaxial cable connector for many times, so the operation is simple, the test efficiency can be improved, and the expensive BER 360 and test fixture 320 are not required , can reduce costs.

Optionally, as shown in FIG. 5 and FIG. 6 , the above-mentioned first control signal and second control signal may be generated by the control device 700 . The control device 700 may also be configured to receive the above eye diagram data and/or eye diagram test conclusion, generate and display the eye diagram and/or eye diagram test conclusion, or be configured to receive the above bit error data and display the bit error rate. The control device may be an electronic device, such as a personal computer, a tablet computer, a mobile phone, and the like.

Exemplarily, when the test device 500 is used to perform eye-diagram testing on the high-speed signal in the device under test 600, the above-mentioned control device 700 may be coupled with the processor 620 and the interface circuit 510 in the device under test 600, and the control device 700 may It is used to generate the above-mentioned first control signal, and can also be used to receive the above-mentioned eye diagram data to generate and display the eye diagram. Further, the control device 700 may store preset eye diagram test indicators, and the control device 700 The eye diagram test index is set to determine the eye diagram test conclusion; alternatively, the control device 700 may be configured to receive the above eye diagram test conclusion and display the eye diagram test conclusion; or, the control device 700 may be configured to receive the above eye diagram data and the eye diagram test conclusion , generate and display eye diagrams and eye diagram test conclusions. When the test device 500 is used to perform bit error testing on the high-speed signal in the device to be tested 600, the control device 700 can be coupled with the interface circuit 510 of the test device 500, the control device 700 can be used to generate the second control signal, and also It can be used to receive the above bit error information to display the bit error rate.

Optionally, the control device 700 may include control software, which is used to start, pause, stop testing, collect, analyze test data, and output test reports. For example, the control software may be used to generate the above-mentioned first control signal and the first control signal. Two control signals and other control signals. specific. The test operator can select the test to be performed by clicking the virtual button in the control software. For example, the operator can select the eye diagram test, or can select the bit error test to control the test device 500 and the device to be tested 600 to execute the corresponding test. instruction to complete the test content such as eye diagram test or bit error test, receive the test result sent by the test device 500, analyze the test result to generate a test report, and complete the test of the device to be tested 600. Further, the tester can also perform parameter deflection and parameter optimization according to the test report generated by the control software, thereby improving the test efficiency.

Optionally, the above-mentioned interface circuit 510 may be an Ethernet interface circuit, a serial communication interface circuit, a universal serial bus (universal serial bus, USB) interface circuit or a wireless interface circuit. Not limited.

It can be understood that when the interface circuit 510 is a wireless interface circuit, the interface circuit 510 and the control device 700 do not need to be wirelessly connected through a wired connection. Compared with the wired connection, the positions of the control device 700 and the testing device 500 are not limited by cables. It is flexible, and the establishment of communication between the control device 700 and the testing device 500 is more convenient.

Exemplarily, when the interface circuit 510 is an Ethernet interface circuit, the interface circuit 510 may include an Ethernet interface and an Ethernet interface chip; when the interface circuit 510 is a serial communication interface circuit, the interface circuit 510 may include a serial communication interface and an Ethernet interface chip. serial communication interface chip; when the interface circuit 510 is a universal serial bus interface circuit, the interface circuit 510 may include a universal serial bus interface and a universal serial bus interface chip; when the interface circuit is a wireless interface circuit, the interface circuit 510 may Including wireless chip.

For example, when the interface circuit 510 includes an Ethernet interface and an Ethernet interface chip, the Ethernet interface can be a crystal jack 45 (registered jack 45, RJ-45) interface or a crystal jack 11 (registered jack 11, RJ-11) interface , the Ethernet interface chip may be a physical layer (physical layer, PHY) chip. When the interface circuit 510 includes a serial communication interface and a serial communication chip, the serial communication interface chip may be a 232 (recommended standard 232, RS232) serial chip of the Electronic Industries Alliance, wherein the serial communication interface may be referred to as a serial port for short. When the interface circuit 510 includes a universal serial bus interface and a universal serial bus interface chip, the universal serial bus interface can be a USB2.0 interface or a USB3.0 interface, and the universal serial bus interface chip can be a USB2.0 interface chip Or it can be a USB3.0 interface chip. When the interface circuit 510 includes a wireless interface chip, the wireless interface chip may be a Bluetooth (bluetooth) chip, a wireless fidelity (wireless fidelity, WIFi) chip or a Zigbee (Zigbee) chip. In FIGS. 5 and 6 , the interface circuit 510 is a serial communication interface circuit, and the serial communication interface circuit includes a serial port 511 and an RS232 serial port chip 512 as an example for illustration.

Optionally, as shown in FIG. 5 and FIG. 6 , the above-mentioned test circuit 520 may include a test chip 521, one end of the test chip 521 is coupled to the interface circuit 510, and the other end of the test chip 521 is coupled to the test interface 530, and the test chip 521 It is used to determine the test result of the device under test 600 according to the test signal.

Optionally, the above-mentioned test chip 521 includes one of the following: a high-speed clock and data recovery (clock and data recovery, CDR) chip, a signal driver (retimer) chip, and a selection (switch) chip. Type is not limited.

Optionally, as shown in FIG. 5 and FIG. 6 , the above-mentioned test circuit 520 may further include a clock circuit 522 and a reset circuit 523 , and the clock circuit 522 and the reset circuit 523 are respectively coupled to the test chip 521 . The clock circuit 522 is used to provide a clock for the test chip 521, and the reset circuit 523 is used to restore the test chip 521 to the initial state when the test of each channel in the device to be tested is completed, so that the test device 500 can complete all channels in the device to be tested 600. test.

Optionally, the above-mentioned test interface 530 (or referred to as a golden finger) is related to the type of the slot 610 in the device under test 600 , and the test interface 530 can be designed as different types of interfaces according to the type of the slot 610 . The test interface 530 may include one of the following: a high-speed serial computer expansion bus interface, a serial connection small computer system interface, a serial advanced technology accessory interface, a card electromechanical (CEM) interface, a non-volatile memory standard ( non-volatile memory express, NVME) interface and open core protocol (open core protocol, OCP) interface. Therefore, the test device 500 can be supported to test high-speed signals such as high-speed serial computer expansion bus signals, serial connection small computer system interface signals, serial advanced technology accessory signals, and universal serial bus signals.

Exemplarily, when the slot 610 is a high-speed serial computer expansion bus slot, the above-mentioned test interface 530 may be a high-speed serial computer expansion bus interface.

Optionally, when the test interface 530 is a high-speed serial computer expansion bus interface, the high-speed serial computer expansion bus interface may include 16 channels, 8 channels, 4 channels or 1 channel, or may include more The embodiment of the present application does not limit the specific number of channels included in the high-speed serial computer expansion bus interface.

Optionally, the test device 500 provided in the embodiment of the present application can be set to different forms according to the type of the test interface, so that it can be more conveniently used to test the device to be tested 600, and the form of the test device 500 may include one of the following: : High-speed serial computer expansion bus board, interface and open core protocol board, 2.5-inch hard disk, 3.5-inch hard disk or U disk, etc.

The test device 500 provided in the embodiment of the present application receives the test signal sent by the device to be tested 600 through the test interface 530 , or receives the test signal sent by the device to be tested 600 through the test interface 530 , the test interface 530 includes and the device to be tested 600 There are multiple channels corresponding to the slot 610 in the test circuit, so in the process of testing, it is not necessary to change the structure of the test circuit many times, and the test circuit 520 can receive the test signal sent by any one of the multiple channels. The signal can determine the test result of the device under test 600 . Therefore, the operation during the test is simple, the test efficiency can be improved, and at the same time, the expensive oscilloscope 330, the bit error tester 360 and the test fixture 320 are not required, which can reduce the cost.

In a possible embodiment, as shown in FIG. 7 , the above-mentioned test device 500 may further include a power supply circuit 540, the input end of the power supply circuit 540 is coupled with the test interface 530, and the output end of the power supply circuit 540 is connected with the interface circuit 510 and the interface circuit 510 and the test interface 530. Test interface 530 is coupled.

It should be noted that, the structure of the testing device 500 in FIG. 7 above is illustrative, and does not limit the embodiments of the present application.

The power supply circuit 540 is used to supply power to the interface circuit 510 and the test circuit 520 .

Specifically, the power supply circuit 540 is used to receive the power supply voltage from the test interface 530. When the power supply voltage is different from the power supply voltage required by the interface circuit 510 and the test circuit 520, the received power supply voltage can be voltage transformed to generate The supply voltage required by the interface circuit 510 and the test circuit 520 .

Optionally, the power supply voltages required by the interface circuit 510 and the test circuit 520 may be the same, or the required power supply voltages may be different, which is not limited in this embodiment of the present application. The following embodiments use the interface circuit 510 and the test circuit 520 The required power supply voltages are different power supply voltages as an example for illustration.

For example, referring to FIG. 7 , when the power supply voltages required by the interface circuit 510 and the test circuit 520 are different, the first output end of the power supply circuit 540 is coupled to the RS232 serial port chip in the interface circuit 510, and the power supply circuit 540 The second output terminal is coupled to the test chip 521 . Taking the power supply circuit 540 receiving the 12V power supply voltage provided by the device under test 600 through the test interface 530, the RS232 serial port chip in the interface circuit 510 needs a 1.8V power supply voltage, and the test chip 521 needs a 3.3V power supply voltage as an example, the power supply circuit 540 according to the 12V power supply voltage The power supply voltage can generate the 1.8V power supply voltage required by the RS232 serial port chip in the interface circuit 510 and the 3.3V power supply voltage required by the test chip 521 .

The test device 500 provided by the embodiment of the present application processes the power supply voltage received by the test interface 530 through the power supply circuit 540 , so that a stable power supply voltage can be provided for the interface circuit 510 and the test circuit 520 .

In other embodiments, the power supply circuit 540 may be coupled with the interface circuit 510, and the interface circuit 510 may receive a supply voltage from the control device 700, and when the supply voltage is different from the supply voltage required by the interface circuit 510 and the test circuit 520, it may Voltage conversion is performed on the received power supply voltage to generate the power supply voltage required by the interface circuit 510 and the test circuit 520 .

In other embodiments, the power supply circuit 540 may only provide a stable power supply voltage to the interface circuit 510 , or the power supply circuit 540 may only provide a stable power supply voltage to the test circuit 520 . Based on this, as shown in FIG. 8 , an embodiment of the present application further provides a test device 800 for testing the device to be tested 900 , and the test device 800 includes a control device 810 and a test device 820 that are coupled to each other. The control device 810 and the testing device 820 are respectively coupled to the device to be tested 900 . The structure of the test device 820 may be the structure of the test device 500 shown in FIG. 5 , FIG. 6 and FIG. 7 .

It should be noted that, the structure of the testing device 800 in FIG. 8 above is illustrative, and does not limit the embodiments of the present application.

The above-mentioned control device 810 is used for sending control signals, the device under test 900 is used for sending test signals according to the control signals, the testing device 820 is used for determining the test result of the device under test 900 according to the test signal, and the control device 810 is also used for receiving the test results.

Optionally, the test device 800 provided in this embodiment of the present application may be used for high-speed signal testing, or may be used for low-speed signal testing. This embodiment of the present application does not limit whether the test device 800 specifically uses high-speed signal testing or low-speed signal testing.

Optionally, the test equipment 800 provided in this embodiment of the present application may be used for eye diagram testing, to generate an eye diagram and/or an eye diagram test conclusion to determine the quality of the transmission link of the device under test 900, and the above test results are an eye diagram and/or an eye diagram test result. Or eye diagram test conclusion; or, it can be used for bit error test to determine bit error information (bit error rate) to judge the quality of the link received by the device under test 900, and the above test result is bit error information.

Optionally, the control device 810 may include control software, which is used to start, pause, stop the test, collect, analyze test data, and output the test report. For example, the control software may be used to generate the above-mentioned first control signal and the first control signal. Two control signals and other control signals. specific. The test operator can select the test to be performed by clicking the virtual button in the control software. For example, the operator can select the eye diagram test, or can select the bit error test to control the test device 820 and the device to be tested 900 to perform the corresponding test. order to complete the test content such as eye diagram test or bit error test, receive the test result sent by the test device 820 , analyze the test result to generate a test report, and complete the test of the device to be tested 900 . Further, the tester can also perform parameter deflection and parameter optimization according to the test report generated by the control software, thereby improving the test efficiency.

Exemplarily, the control device 810 may adjust the pre-emphasis according to the above eye diagram and/or the eye diagram test conclusion and the bit error rate, so as to improve the quality of the high-speed signal transmitted by the device under test 900 . The pre-emphasis refers to a signal processing method that compensates the high-frequency components of the high-speed signal when sending the high-speed signal. By adjusting the pre-emphasis, the loss of the high-speed signal in the transmission process can be compensated, and the quality of the high-speed signal can be improved.

Optionally, the above-mentioned control device 810 is an electronic device. For example, the electronic device may be a personal computer, a tablet computer, a mobile phone, and the like.

Optionally, the above-mentioned device to be tested 900 may include a mainboard 910 , and the mainboard 910 may be provided with a processor 911 and a slot 912 .

The above-mentioned test device 820 includes a test interface 821 for coupling with the slot 912 in the device to be tested 900 .

Optionally, the test interface 821 may include one of the following: a high-speed serial computer expansion bus interface, a serial connection to a small computer system interface, a serial advanced technology accessory interface, a card electromechanical interface, a non-volatile memory standard interface, and Open core protocol interface. Therefore, the test equipment 900 can be supported to test high-speed signals such as high-speed serial computer expansion bus signals, serial connection small computer system interface signals, serial advanced technology accessory signals, and universal serial bus signals.

Optionally, the above-mentioned test signal is a test pattern, and a stable and repeatable test can be performed by using the test pattern, and the test pattern may include one of the following: PRBS31, PRBS7, PRBS9, PRBS11, PRBS15, PRBS20 and PRBS23.

In a possible embodiment, as shown in FIG. 9 , the above-mentioned control device 810 may be integrated in the test device 820 , and the test device 800 may further include a human-computer interaction interface 830 , which is connected to the control device 810 . Coupling, the test operator can control the test equipment to test the device to be tested 900 by clicking the virtual button in the human-computer interaction interface 830, and the human-computer interaction interface 830 can also be used to display the test results.

In the test equipment 800 provided in this embodiment of the present application, the test result of the device to be tested 900 is determined by the test device 820 according to the test signal. The test device 820 is coupled to the device to be tested 900 through the test interface 821 and the slot 912. There are multiple channels corresponding to the slot 912. Therefore, in the process of testing, it is not necessary to change the structure of the test circuit many times. The test device 820 can receive the test signal in the device to be tested 900, and the test result can be determined according to the test signal. , the control device 810 can display the test result eye diagram and/or the eye diagram test conclusion according to the test result, or display the bit error rate, so that the quality of the transmission link and the reception link of the device under test 900 can be determined. Compared with the prior art, in the process of testing, it is not necessary to change the connection position of the coaxial cable connector many times, so the operation is simple, and the testing efficiency can be improved. 360 and test fixture 320, which can reduce the cost. It should be noted that, the relevant descriptions of the testing apparatus 500 in the above apparatus embodiments can be correspondingly cited in the embodiments of the testing apparatus 800 , and details are not described herein again in this embodiment of the present application.

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited to this, and any changes or substitutions within the technical scope disclosed in the present application should be covered within the protection scope of the present application. . Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims (10)

1. A test device, characterized in that the test device comprises: an interface circuit, a test circuit and a test interface, wherein the interface circuit, the test circuit and the test interface are coupled, wherein: The test interface is used to connect the device to be tested; the test interface for receiving a test signal from the device to be tested; the test circuit, configured to determine the test result of the device to be tested according to the test signal; The interface circuit is used for sending the test result. 2. test device according to claim 1, is characterized in that, described test signal is the first test pattern, and described test result comprises eye pattern data and/or eye pattern test conclusion, and described eye pattern test conclusion uses for indicating whether the eye pattern data meets the predetermined eye pattern test index. 3. The test device according to claim 2, wherein when the test result is the eye diagram data, the test circuit is specifically configured to obtain a synchronous clock signal according to the first test pattern, and according to The first test pattern and the synchronization clock signal determine waveform data of multiple clock cycles, and determine the eye diagram data according to the waveform data of the multiple clock cycles; Alternatively, when the test result is the eye-diagram test conclusion, the test circuit is further configured to determine the eye-diagram test conclusion according to the eye-diagram data and the preset eye-diagram test index. 4. test device according to claim 1, is characterized in that, described test signal is the second test pattern, and described test result is bit error information; The interface circuit is also used for receiving a control signal; The test circuit is further configured to generate a third test pattern according to the control signal; The test interface is further configured to send the third test pattern to the device under test, and the second test pattern is obtained by the device under test converted according to the third test pattern. 5. The test device according to claim 4, wherein the test circuit is specifically configured to compare the second test pattern and the third test pattern bit by bit to determine the second test pattern The number of error bits of the pattern is determined, and the error information is determined according to the ratio of the number of error bits to the total number of bits of the third test pattern. 6 . The test device according to claim 1 , wherein the test circuit comprises a test chip, one end of the test chip is coupled to the test interface, and the other end of the test chip is coupled to the test interface. 7 . coupled to the interface circuit. 7. The test device according to claim 6, wherein the test chip comprises a high-speed clock data recovery chip, a signal driver chip or a selection chip. 8 . The test device according to claim 6 , wherein the test circuit further comprises a clock circuit and a reset circuit, and the clock circuit and the reset circuit are respectively coupled to the test chip. 9 . 9. The test device according to any one of claims 1-8, wherein the test device further comprises a power supply circuit; The input end of the power supply circuit is coupled to the test interface, and the output end of the power supply circuit is coupled to the interface circuit and the test circuit. 10. A test equipment, characterized in that the test equipment is used to test a device to be tested, the test equipment comprises a control device and a test device coupled to each other, and the test device is any one of claims 1-9 The test device described in item; the control device, configured to send a control signal to the device to be tested; The test device is configured to receive a test signal sent by the device to be tested according to the control signal, and to determine the test result of the device to be tested according to the test signal; The control device is further configured to receive the test result.

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