CN108494533B

CN108494533B - Portable remote multi-channel communication device bit error rate testing device and method

Info

Publication number: CN108494533B
Application number: CN201810480539.XA
Authority: CN
Inventors: 邓彬伟; 张轶蔚; 胡学芝; 喻程鹏; 冷志雄; 付建
Original assignee: Hubei Polytechnic University
Current assignee: Hubei Polytechnic University
Priority date: 2018-05-18
Filing date: 2018-05-18
Publication date: 2023-06-23
Anticipated expiration: 2038-05-18
Also published as: CN108494533A

Abstract

The invention discloses a portable remote multi-channel communication device error rate testing device and a method, wherein the device comprises the following steps: the system comprises a high-speed serial interface expansion board, a parallel interface expansion board, a clock generator, an acquisition controller, a USB extension line and a remote terminal; the connection mode of the tested device and the device comprises the following steps: long-range connection and short-range connection; the device generates a pseudo-random sequence code seed with multiple modes as a mode code, performs mode comparison with a sequenced sequence generated by a tested device, finds a sequence consistent with the mode code after comparing a section of sequence, generates a corresponding sequence subsequent to the mode code according to the consistent sequence, and performs bit comparison with the sequenced sequence, thereby realizing error detection. The invention can be used in various severe test environments, and the device has the functions of multiple serial and parallel channels and can realize remote bit error rate test; and the testing precision is high, the portability of the device is good, and the use cost is low.

Description

Portable remote multi-channel communication device bit error rate testing device and method

Technical Field

The invention relates to the technical field of communication device detection, in particular to a portable remote multi-channel communication device bit error rate testing device and method.

Background

Digital communication systems are increasingly being used in various aspects of production, life, etc., and Bit Error (BER) performance is one of the most basic measures of performance of any digital communication system. Bit error indicators are typically measured using a bit error rate test analyzer. Particularly, with the enhancement of the anti-interference capability of the ASIC chip of the digital system, the digital communication system is also applied to the fields of medical system detectors with strong radiation environment, particle accelerators for high-energy physical research, communication systems in space exploration and the like in severe environments. Thus providing remote test capability when performing bit error rate testing. The current commercial bit error rate analyzer is mainly manufactured by Agilent, tektronix, anritsu and other companies, and the proposed bit error rate analyzer has the advantages of multifunction, eye pattern analysis capability and the like, but the instrument is heavy and expensive. Such as the Tektronix BSA series error rate analyzer, is also more than one hundred thousand dollars in cost. Further, the integrated BER analyzer MP2100A of high performance from the company Anritsu is inconvenient to carry with a weight of approximately seven kg, and its price is also over hundreds of thousands dollars. Even the Tektronix BA series bit error rate tester with a highest rate of only 1.6Gbps without network functionality costs over fifty thousand dollars. Therefore, the commercial bit error rate test system has strong test capability and extremely high precision, but is heavy and inconvenient to carry, and has influence on test installation in a severe environment.

FPGAs currently have specialized communication interfaces including clock data recovery and enhanced phase locked loop circuitry, and furthermore, performance and powerful communication capabilities are adequate for high speed communications and computation. Kintex-7 is a new generation of high performance field programmable gate arrays with 16 passes of up to 11.5Gbps transmission GTX and its Xilinx report indicates that the chip can withstand the radiation TID test (TID, a standard test method given in the ATLAS report) to a total dose of 1Mrad.

Disclosure of Invention

Aiming at the defects in the prior art, the invention provides a portable remote multi-channel communication device bit error rate testing device and a method.

The technical scheme adopted for solving the technical problems is as follows:

the invention provides a portable remote multi-channel communication device error rate testing device, which comprises: the system comprises a high-speed serial interface expansion board, a parallel interface expansion board, a clock generator, an acquisition controller, a USB extension line and a remote terminal; wherein:

the acquisition controller is provided with an LPC interface, an HPC interface, a first RJ45 interface and a serial reference clock interface; the clock generator is provided with a first USB interface and a plurality of clock signal output interfaces; the remote terminal is provided with a second USB interface and a second RJ45 interface; the high-speed serial interface expansion board and the parallel interface expansion board are respectively provided with an FMC interface and a serial reference clock interface;

the high-speed serial interface expansion board is connected with an HPC interface of the acquisition controller through a first FMC interface, and the parallel interface expansion board is connected with an LPC interface of the acquisition controller through a second FMC interface;

the clock generator is respectively connected with the serial reference clock interface of the high-speed serial interface expansion board and the acquisition controller through the clock signal output interface; the first USB interface on the clock generator is connected with the second USB interface on the remote terminal through a USB extension line; the first RJ45 interface on the acquisition controller is connected with the second RJ45 interface on the remote terminal through a network cable;

the connection mode of the tested device and the device comprises the following steps: long-range connection and short-range connection; the device to be tested is remotely connected with the acquisition controller through an optical fiber; the tested device is directly and closely connected with the high-speed serial interface expansion board, the parallel interface expansion board or the acquisition controller;

the device generates a pseudo-random sequence code seed with multiple modes as a mode code, performs mode comparison with a sequenced sequence generated by a tested device, finds a sequence consistent with the mode code after comparing a section of sequence, generates a corresponding sequence subsequent to the mode code according to the consistent sequence, and performs bit comparison with the sequenced sequence, thereby realizing error detection.

Further, the device of the invention also comprises an SFP+ optical fiber module and an SFP/SFP+ connector, wherein the SFP/SFP+ connector is arranged on the acquisition controller; the tested device is connected to the SFP+ optical fiber module through the optical fiber, and the SFP+ optical fiber module is inserted into the SFP/SFP+ connector, so that the remote connection between the tested device and the acquisition controller is realized.

Further, the short-range connection of the present invention includes three ways:

the high-speed serial interface expansion board is provided with a first SMA high-speed SEDES port, and the tested device is connected with the first SMA high-speed SEDES port through a coaxial cable;

the tested device is connected with the parallel interface expansion board through an IDE wire;

the acquisition controller is provided with a second SMA high-speed SEDES port, and the device to be tested is connected with the second SMA high-speed SEDES port through a coaxial cable.

Further, the acquisition controller of the present invention is a KC705Kintex-7 development board employing an FPGA chip.

Further, the remote terminal of the invention is a notebook computer or a PC computer.

Further, the acquisition controller comprises a pseudo-random sequencer generating module, a TEMAC network module, a GTX module, a FIFO module and an error detecting module which are connected with each other; the pseudo random sequence code pattern generated by the pseudo random sequence generator module includes PRBS7, PRBS15, PRBS23, PRBS31.

Further, the device of the invention also comprises a serializer and a deserializer; the output end of the pseudo-random sequencer is connected with the tested device through the serializer; the output end of the tested device is connected with the error detection module through the deserializer; the transmission rates of the serializer and the deserializer include 3.125Gbps, 4.8Gbps, 5.0Gbps, 5.12Gbps, 6.25Gbps, 8Gbps, 10Gbps.

Further, the parallel interface expansion board of the invention is provided with a plurality of columns of IDE interfaces.

The invention provides a portable remote multi-channel communication device error rate test method, which comprises the following steps:

selecting a connection mode of the device according to the test environment: the conventional environment is an area where operators can normally move; the harsher environment is a region which is harmful to human bodies but has no influence on device hardware; the severe environment is an area affecting the normal operation of the hardware of the device;

if the environment is a conventional environment, a short-range connection mode is adopted, a tested device in the conventional environment is directly connected with a high-speed serial interface expansion board, a parallel interface expansion board or an acquisition controller, and an operator performs short-range test;

if the device is in a harsher environment, a short-range connection mode is adopted, a device to be tested in the harsher environment is directly connected with a high-speed serial interface expansion board, a parallel interface expansion board or an acquisition controller, the acquisition controller is connected with a remote terminal through a network cable, and an operator performs remote test;

if the device is in a severe environment, a remote connection mode is adopted, a tested device in the severe environment is connected to the SFP+ optical fiber module through optical fibers, the SFP+ optical fiber module is inserted into an SFP/SFP+ connector of a remote acquisition controller, and an operator performs remote test.

Further, the test contents of the test device in the method of the invention comprise: loop test, optical fiber transmission error rate test and chip test.

The invention has the beneficial effects that: the invention discloses a portable remote multi-channel communication device error rate testing device and a method, which are suitable for remote error rate detection and low-price portability of devices such as an optical transmitter/receiver, a electric transmitter/receiver, a serializer, a deserializer and the like in communication.

Drawings

The invention will be further described with reference to the accompanying drawings and examples, in which:

FIG. 1 is an overall layout of an apparatus according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of the operation of the apparatus according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a high-speed serial interface expansion board according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a parallel interface expansion board according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a circuit connection according to an embodiment of the present invention;

FIG. 6 is a diagram of reference clock frequencies and corresponding transmission rates during serial transmission according to an embodiment of the present invention;

FIG. 7 is a schematic view of a photoelectric conversion board according to an embodiment of the present invention;

FIG. 8 is a LOCX2 test schematic of an embodiment of the invention;

in the figure: the system comprises a 1-high-speed serial interface expansion board, a 2-first FMC interface, a 3-first SMA high-speed SEDES port, a 4-serial reference clock access port, a 5-parallel interface expansion board, a 6-second FMC interface, a 7-first IDE interface, an 8-second IDE interface, a 9-acquisition controller, a 10-clock generator, an 11-remote terminal, a 12-LPC interface, a 13-HPC interface, a 14-SFP/SFP+ connector, a 15-first RJ45 interface, a 16-first USB interface, a 17-second USB interface, a 18-second RJ45 interface, a 19-USB extension line, a 20-second SMA high-speed SEDES port, a 21-photoelectric conversion board, a 22-SFP connection base, a 23-SMA base group and a 24-SFP+ optical fiber module.

Detailed Description

The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

As shown in FIG. 1, the portable remote multi-channel communication device error rate testing device in the embodiment of the invention comprises a high-speed serial interface expansion board, a parallel interface expansion board, an SFP+ optical fiber module (Finisar FTLX8571D3 BCL), an SFP/SFP+ connector, a clock generator (Si 5338), an acquisition controller and a notebook computer; the tested device is connected to the high-speed serial interface expansion board, the parallel interface expansion board or the SFP+ optical fiber module through a copper axis cable or optical fiber; the two expansion boards are connected to an HPC port and an LPC interface of the acquisition controller through an FMC interface, and the SFP+ optical fiber module is connected to an optical fiber module socket of the acquisition controller. The clock generator generates working clock which is connected to the high-speed serial interface expansion board and the acquisition controller serial clock input interface through the copper axis cable; the acquisition controller realizes the network functions of acquisition, detection, control and generation of the MAC protocol and is communicated with the notebook computer through a network cable.

The device takes a multimode pseudo-random sequence (PRBS) as information source information, adopts a digital logic calculation method to generate four pseudo-random sequences of 7, 15, 23 and 31, and realizes the maximum 68-line parallel data output capacity of 640 MHz.

The device designs a 7-path serializer and a deserializer with serial transmission rates of 3.125Gbps, 4.8Gbps, 5.0Gbps, 5.12Gbps, 6.25Gbps, 8Gbps and 10Gbps through researching a configuration method of a high-performance FPGA chip Kintex-7 high-speed transmitter in a customized way; and includes supporting 1-way fiber optic transmission links. Four of the paths are output through a self-designed high-speed serial expansion board. The binary file generated at 7 rates can be manually downloaded to the acquisition controller by the imact tool for operation as needed.

The device can decode the pseudo random sequence codes of four modes of PRBS7, PRBS15, PRBS23 and PRBS31 to realize the function of real-time error detection.

The device realizes the error detection of the multi-mode multi-bit wide PRBS by methods such as state mode matching and the like. The method comprises the steps of simultaneously generating a pseudo-random sequence code seed of a corresponding mode as a mode code by a local machine, carrying out mode comparison on a sequence to be tested, finding out sequence time consistent with the mode code after passing through a section of sequence, and then synchronously generating the corresponding sequence and the sequence to be tested by the mode code according to a sequence code generation formula by locking. Thereby enabling error detection.

In the device, a KC705Kintex-7 development board is adopted as the acquisition controller. The acquisition controller function is divided into a pseudo-random sequencer generation module, a TEMAC network module, a GTX module, a FIFO module, an error detection module and the like.

The pseudo-random sequencer generating module is used for generating 7, 15, 23 and 31 PRBS by adopting a digital logic calculation method and realizing the maximum 68-line parallel data output capability of 640 MHz. Taking PRBS7 sequence generation as an example, the generation formula is x0=x1=x7. The generation of the sequence can be realized by adopting a method which takes 127 bits as a cycle in the characteristic of the PRBS7 sequence, and since only 127 bits are adopted, all 127 bits can be listed, and then a shift operation is adopted to generate 40 bits of parallel data. While for the PRBS15, PRBS23, PRBS31, the provided sequence initialization seed is used, and then the related sequence is generated by the formula of its sequence generation. And generates a maximum of 68 lines of parallel data at the parallel clock recovered by the 640MHz high speed transmitter. In particular implementations, a sequence of up to 68 lines is also gated out by a one-out-of-four multiplexer.

The high-speed serial interface expansion board comprises 10 SMA female seats and 400 pin FMC interfaces, wherein 8 pairs of differential serial data input seats are 4 pairs, LVDS standard serial data transmission with the speed of up to 10Gbps can be ensured, and the other 2 pairs of differential serial reference clock input seats are 1 pair of differential serial reference clock input seats and can be connected with clock LVDS standard signals with the speed of up to 320MHz through copper axis cables; the parallel interface expansion board leads 68 parallel lines up to 640MHz LVDS25 signals out of KC705LPC except power supply, ground and clock signal lines.

SFP+ optical fiber module adopts Finisar FTLX8571D3BCL optical fiber module to support 850nm wavelength multimode optical fiber and 10Gbps transmission rate.

The clock generator, the Si5338EVB RV1.0 evaluation board was used. The generation of clocks supporting up to 700MHz LVDS signal standards.

The notebook computer adopts CPU above Kuui 3, hard disk above 500GB, memory above 4GB, USB above 2.0 interface, RJ45 network cable interface, and display above 14 inches.

In the device, the USB extender adopts a USB to network cable RJ45 port signal amplifier with a power supply to support the arrangement of Si5338 for 100 meters.

The conventional environment refers to an area where people can normally live and is also an area where the notebook computer is placed; the harsher environment area refers to an area such as a non-radiation source direct irradiation area or an area which has a certain harm to a human body but has no influence on a hardware circuit of the device; the severe environment area refers to an area such as a direct irradiation area of a radiation source or an area having an influence on the normal operation of a hardware circuit of the device, but a device under test needs an environment for testing.

In another embodiment of the present invention, the device comprises 68mm x 121mm high speed serial interface expansion board (including FMC interface male port connected to HPC, 4 pairs of high speed SEDES SMA ports and MGTREFCLK0_118 serial reference clock input port), 68mm x 55mm parallel interface expansion board (including FMC interface male port connected to LPC, 40 pin 1 IDE port and 40 pin 2 IDE port), si5338 clock generator (including CLK0A/CLK0B and CLK1A/CLK1B SMA ports connected to two pairs of LVDS signal outputs used by the device and USB interface No. 1 provided by transmission and power supply), acquisition controller is KC705 development board (mainly including Kintex-7FPGA, a pair of SMA high speed SEDES ports, a pair of sma_mgt_refc 117bank serial reference clock input ports (J10P, J10N), SFP ports, i.e. SFP/p+ connector, FMC female port, FMC HPC female port and RJ 45) and RJ45 port including USB interface No. 2 and USB interface No. 45.

The tested device is connected to any one pair of 4 pairs of high-speed SEDES SMA ports of the high-speed serial interface expansion board or a pair of SMA high-speed SEDES ports of the acquisition controller through a copper axis cable or connected to a 40-pin No. 1 IDE port or a 40-pin No. 2 IDE port of the parallel interface expansion board through an IDE wire; the high-speed serial interface expansion board is connected to an FMC HPC female port on the collector through an FMC interface male port connected with the HPC, and the parallel interface expansion board is connected to an FMC LPC female port on the collector through two expansion boards through an FMC interface male port connected with the LPC;

the tested device can also be connected to the SFP+ optical fiber module through the optical fiber and then inserted into an SFP port of the acquisition controller to realize photoelectric conversion and then enter the Kintex-7FPGA for detection. The Si5338 clock generator generates working clocks required by serial transmission and outputs the working clocks to the CLK0A and CLK0B, the working clocks are connected to a MGTREFCLK-118 serial reference clock port of the high-speed serial interface expansion board through a copper axis cable and a serial reference clock input interface of J10P and J10N which are connected to the acquisition controller through the CLK1A and CLK1B outputs, the No. 2 USB port of the notebook computer can reach 100 meters long distance through a USB extender by utilizing a network cable to communicate with the No. 1 USB port on the Si5338 clock generator to carry out configuration reference clocks, and the aim of remote error rate test through a network is ensured through the USB extender; the acquisition controller realizes the network functions of acquisition, detection, control and generation of the MAC protocol and is connected with the No. 2 RJ45 network port on the notebook computer through a network cable on the No. 1 RJ45 network port for communication. And running a program written by Labveiw on the notebook computer to analyze the uploaded network message for real-time recording and displaying.

The following 3 test experiments were performed:

1. loop test experiment

Connecting the transmitting end and the receiving end of the 4 pairs of high-speed SEDES SMA ports on the high-speed serial interface expansion board (P port and N port) in pairs through a copper axis cable, configuring a clock generator to generate 320MHz reference clock signals CLK0A and CLK0B, outputting and connecting the signals to a MGTREFCLK0_118 serial reference clock port of the high-speed serial interface expansion board, and connecting No. 1 RJ45 15 on the acquisition controller and No. 2 RJ45 on the notebook computer through a network cable; the Xilinx's iMPACT then downloads FPGA firmware running 3.12Gbps transmission rate to the acquisition controller. And testing the error rate in normal operation by running a monitoring program written by Labview of the notebook computer. Run time was 20 minutes. Then the SW4 key on the KC705 development board is pressed to inject errors, one bit at a time into all serial channels, observe the error count change, and view the log record at the end of this round of testing. And then the FPGA firmware which changes the frequency of the reference clock signal generated by the clock generator and the corresponding transmission rate is downloaded to the acquisition controller, and the steps are repeated until all the 7 rate conditions are measured. The fiber serial channel and the KC705 on-board SMA high-speed SEDES port channel are subjected to loop test by adopting the method, an SFP+ fiber module in the fiber serial channel adopts a Finisar FTLX8571D3BCL fiber module, and a 1-meter-long multimode fiber is used for connecting the optical output and the optical input of the SFP+ fiber module to form a loop. The repeated tests were performed at 7 transmission rates and six high-speed serial channels.

2. AVAGO AFBR-57D7APZ SFP+ optical fiber module error rate test

The AVAGO AFBR-57D7APZ SFP+ optical fiber module supports the multimode optical fiber to generate 850nm wavelength, and the maximum support of 8.5Gbps, and the error rate index is tested by using the device. The connection is shown in fig. 7, the AVAGO AFBR-57D7APZ sfp+ optical fiber module is inserted into the photoelectric conversion board, the 1m multimode optical fiber is connected to the light output and input ports of the AVAGO AFBR-57D7APZ sfp+ optical fiber module, the J13 receiving port of the SMA seat group of the photoelectric conversion board is connected to the J11 transmitting port of the acquisition controller, and meanwhile, the J14 transmitting port of the SMA seat group of the photoelectric conversion board is connected to the J12 receiving port of the acquisition controller. With the 8Gbps rate, PRBS31 mode, the Si5338 clock generator is configured to output a 125MHz clock to the CLK1A/CLK1B, downloading the 8Gbps rate firmware to the FPGA of the acquisition controller, running for 20 minutes, according to FIGS. 6 and 5. Because the acquisition controller and the Si5338 are connected with the notebook computer through a network, other parts of the device except the notebook computer for monitoring and recording data can be in a severe environment, and the tested AVAGO AFBR-57D7APZ SFP+ optical fiber module can be in a severe condition for carrying out error rate test on the optical fiber module, such as a strong x-ray environment.

3. LOCX2 chip test

LOCX2 is a 2-channel data transmission chip which is specially designed for working in a strong radiation environment and integrates linear coding and transmission, and the transmission rate of each channel is 5.12Gbps. A diagram of the LOCx2 test is shown in fig. 8. The LOCX2 board is connected with signals such as a clock and the like according to the working requirement of the chip, the parallel expansion board of the device is connected with the parallel input port of the LOCX2 board through 40-wire IDE wires, one path of signals serially output by the LOCX2 chip is connected with the SFP RX of the SFP optical fiber module inserted in the SFP port on the KC705 development board of the device through multimode optical fibers, and the other path of signals is connected with the SMA RX of a pair of SMA high-speed SEDES ports of the KC705 of the device through cables. Configuring a Si5338 generator to generate a 320MHz reference clock from a CLK1 port output over a reference clock input J10 of a high speed serial transmitter bank117 connected by a cable to a KC705 development board of the device; the firmware of two PRBS7 pseudo-random sequences with the serial rate of 5.12Gbps with LOCX2 decoder and 640MHz of output of parallel port is downloaded into KC705, and then the operation is carried out for 1 hour, so that the error rate condition can be observed and recorded in real time, and the error rate can be tested. LOCX2 is a chip for the operation in a strong radiation environment, and can be put under the radiation of a neutron source or under the x-ray for error rate test. Thus, the tester can conveniently and safely conduct the test far away from the radiation area.

It will be understood that modifications and variations will be apparent to those skilled in the art from the foregoing description, and it is intended that all such modifications and variations be included within the scope of the following claims.

Claims

1. A portable remote multi-way communication device bit error rate testing device, the device comprising: the system comprises a high-speed serial interface expansion board (1), a parallel interface expansion board (5), a clock generator (10), an acquisition controller (9), a USB extension line (19) and a remote terminal (11); wherein:

an LPC interface (12), an HPC interface (13), a first RJ45 interface (15) and a serial reference clock interface are arranged on the acquisition controller (9); the clock generator (10) is provided with a first USB interface (16) and a plurality of clock signal output interfaces; the remote terminal (11) is provided with a second USB interface (17) and a second RJ45 interface (18); the high-speed serial interface expansion board (1) and the parallel interface expansion board (5) are respectively provided with an FMC interface and a serial reference clock interface;

the high-speed serial interface expansion board (1) is connected with an HPC interface (13) of the acquisition controller (9) through a first FMC interface (2), and the parallel interface expansion board (5) is connected with an LPC interface (12) of the acquisition controller (9) through a second FMC interface (6);

the clock generator (10) is respectively connected with serial reference clock interfaces of the high-speed serial interface expansion board (1) and the acquisition controller (9) through clock signal output interfaces; a first USB interface (16) on the clock generator (10) is connected with a second USB interface (17) on the remote terminal (11) through a USB extension line (19); the first RJ45 interface (15) on the acquisition controller (9) is connected with the second RJ45 interface (18) on the remote terminal (11) through a network cable;

the connection mode of the tested device and the device comprises the following steps: long-range connection and short-range connection; the device to be tested is remotely connected with the acquisition controller (9) through an optical fiber; the tested device is directly and closely connected with the high-speed serial interface expansion board (1), the parallel interface expansion board (5) or the acquisition controller (9);

2. The portable remote multi-channel communication device bit error rate testing apparatus according to claim 1, further comprising an sfp+ fiber module (24) and an SFP/sfp+ connector (14), the SFP/sfp+ connector (14) being disposed on the acquisition controller (9); the tested device is connected to the SFP+ optical fiber module (24) through optical fibers, and the SFP+ optical fiber module (24) is inserted into the SFP/SFP+ connector (14) to realize remote connection of the tested device and the acquisition controller (9).

3. The portable remote multi-way communication device bit error rate testing apparatus of claim 1, wherein the short-range connection comprises three means:

a first SMA high-speed SEDES port (3) is arranged on the high-speed serial interface expansion board (1), and a device to be tested is connected with the first SMA high-speed SEDES port (3) through a coaxial cable;

the tested device is connected with the parallel interface expansion board (5) through IDE wires;

the acquisition controller (9) is provided with a second SMA high-speed SEDES port (20), and the device to be tested is connected with the second SMA high-speed SEDES port (20) through a coaxial cable.

4. The portable remote multi-channel communication device bit error rate test apparatus according to claim 1, wherein the acquisition controller (9) is a KC705 kenex-7 development board using an FPGA chip.

5. The portable remote multi-channel communication device bit error rate test apparatus according to claim 1, wherein the remote terminal (11) is a notebook computer or a PC computer.

6. The portable remote multi-way communication device bit error rate testing apparatus according to claim 1, wherein the acquisition controller (9) comprises a pseudo-random sequencer generating module, a TEMAC network module, a GTX module, a FIFO module and an error detecting module connected to each other; the pseudo random sequence code pattern generated by the pseudo random sequence generator module includes PRBS7, PRBS15, PRBS23, PRBS31.

7. The portable remote multi-way communication device bit error rate test apparatus of claim 6, further comprising a serializer and a deserializer; the output end of the pseudo-random sequencer is connected with the tested device through the serializer; the output end of the tested device is connected with the error detection module through the deserializer; the transmission rates of the serializer and the deserializer include 3.125Gbps, 4.8Gbps, 5.0Gbps, 5.12Gbps, 6.25Gbps, 8Gbps, 10Gbps.

8. The portable remote multi-channel communication device error rate test device according to claim 1, wherein a plurality of rows of IDE interfaces are provided on the parallel interface expansion board (5).

9. A method of testing a bit error rate test device using the portable remote multi-way communication device of claim 1, comprising the steps of:

10. The method for testing the error rate of the portable remote multi-way communication device according to claim 9, wherein the content of the test performed on the test device in the method comprises: loop test, optical fiber transmission error rate test and chip test.