JPWO2019241600A5 - Test measuring device and transmitter of test measuring device - Google Patents

Description

Precision testing of modern electronic devices currently requires a collection of expensive devices that are not necessarily designed to work together. The devices needed today to perform high-precision or high-frequency signal analysis on a communication link or communication device are typically a bit error rate tester (BERT), an arbitrary waveform generator (AWG), Potentially a programmable pattern generator (PPG), an oscilloscope, a computer that integrates the functionality of these devices, software running on this computer, and all of these devices connected to each other and into a device under test (DUT). There are multiple cables to connect.

In some embodiments, all of the functional blocks of the communication link tester 100 shown in FIG. 1 may be integrated into a single physical unit, which physical unit is stand-alone. It may be a unit) or it may be mounted in a test rack. The communication link tester 100, in addition to both the receiver 120 and the transmitter 150, powers all circuits of the physical unit with respect to the other components shown in the communication link tester 100 of FIG. There is a power supply 180 to supply. In addition, the receiver 120 and the transmitter 150 are connected to each other via a high speed parallel bus 182, which transfers data, communication, instructions, control information, etc. between the receiver 120 and the transmitter 150 . Used for transport. Although not shown separately, the parallel bus 182 also carries one or more clock signals generated by either the receiver 120 or the transmitter 150 in the communication link tester 100 or elsewhere. , May be sent to other components within the communication link tester 100. In other embodiments, the communication link tester 100 may be physically assembled in the form of a plurality of components. For example, the transmitting unit 150 may be housed in the first component, while the receiving unit 120 may be physically housed in another component.

The error checker 360 processor also receives other waveforms (such as pattern generator 354 for common multiple pattern types, custom waveform pattern memory 356, etc.) and inputs them for error checking. Can be compared with the waveform. The custom waveform pattern memory 356 allows the user to specify any waveform used for error checking or trigger processing. The waveform used for trigger processing can be digital or analog. Roughly speaking, the pattern generators 352, 354 , and 356 are synchronized and compared with the input data. The trigger is satisfied if a match occurs or if no match occurs.

The pattern generators 352, 354 , 356 may be selected by the multiplexer 358, which selects and validates one of the plurality of pattern generators. The receiving unit 300 executes an error check by a bit error rate (BER) calculation process 362 in the processor in addition to the error checker 360. These are described in detail below.

In addition to error checking and BER calculations by blocks 360, 362 and related triggering functions, other common triggers are also possible, as shown in block 364. For example, an external trigger may be set to store the input data in the receiving unit 300 or execute another function when the external trigger is satisfied. Block 364 triggers also include protocol-based triggering (based on the protocol recovered in block 370), forced triggering, and triggering on sampled input data, similar to traditional oscilloscope functionality. May be included. Further, the trigger block 364 may be set to trigger for an error, in which case the receiving unit 300 stores the input data after the error occurs. An error occurs when the data input to the receiver 300 does not match the input data expected from the pattern generators 352, 354 , 356 (this is evidence that an error has occurred). May be. In some embodiments, the input data is received in a circular memory buffer, and when an error occurs, it also stores a portion of the input data from before the error occurred, which may be an enhancement for analysis. Will provide the tools that have been used. The trigger processing for the error will be described in more detail below.

Claims (20)

An input unit configured to receive an analog signal from the device under test (DUT),
An analog-to-digital converter (ADC) coupled to the input unit and configured to convert the analog signal into a digital signal.
A receiver configured to receive the digital signal and use a first digital signal processor to perform signal conditioning, symbol recovery and analysis of the digital signal.
A transmitter configured to generate a digital output signal using a second digital signal processor,
A digital-to-analog converter (DAC) coupled to the transmitter, configured to convert the digital output signal from the transmitter into an analog signal, and transmit the analog signal to the DUT. )When,
A test measuring device including a communication path between a receiving unit and a transmitting unit that does not pass through the DUT. The test and measurement apparatus according to claim 1, wherein at least a part of the first digital signal processor or the second digital signal processor is physically realized by a reconfigurable processor. The test / measuring device according to claim 1, wherein the transmitting unit and the receiving unit are housed in separate physical devices, and the communication path between the transmitting unit and the receiving unit is a wired connection or a wireless connection . An input unit configured to receive an analog signal from the device under test (DUT),
An analog-to-digital converter (ADC) coupled to the input section and configured to convert the analog signal into a digital signal.
In response to the digital signal, the first digital signal processor is used to perform signal adjustment, symbol recovery and analysis of the digital signal at a rate equal to or higher than the rate at which the analog signal was received from the DUT. A test and measurement device including a receiver configured to continuously process the analog signal from the DUT. The test measuring device according to claim 4 , wherein the receiving unit has a second input unit that receives a second analog signal from the second device under test (DUT). The test and measurement device according to claim 5 , wherein each of the analog signal and the second analog signal carries the first component and the second component of the signal according to a specific protocol. The test measuring device according to claim 5 , wherein the receiving unit is configured to recover a protocol signal from a combination of the analog signal and the second analog signal according to the specific protocol. A signal generator configured to generate a basic output signal,
A digital signal processor configured to add one or more faults to the basic output signal to form a composite output signal.
Test measurements with a digital-to-analog converter (DAC) coupled to the digital signal processor and configured to convert the combined output signal to an analog signal and send the analog signal to the test device. Transmitter of the device. The transmission unit of the test measuring device according to claim 8 , further comprising a second signal generation unit that generates a second output signal. The transmitter of the test measuring device according to claim 8 , further comprising an analog fault emulator, in which a fault is added to the analog signal before it is output to the device for testing. The transmitter of the test measuring device according to claim 10 , wherein the analog fault emulator applies a differential skew , common mode fault or crosstalk to the analog signal before it is output to the device for testing. The transmission unit of the test / measurement device according to claim 8 , further comprising a clock generation unit, wherein the transmission unit of the test / measurement device transmits the clock signal generated by the clock generation unit to the device. The transmitter of the test measuring device according to claim 12 , further comprising a clock stress generator configured to alter the clock signal before it is sent to the device. The test according to claim 8 , further comprising a digital marker waveform generation unit, wherein the transmission unit of the test measuring device transmits the digital marker signal generated by the digital marker waveform generation unit to the device. Transmitter of measuring device. The transmission unit of the test measuring device according to claim 14 , wherein the digital marker signal is related to the analog signal. The transmitter of the test measuring device according to claim 8 , further comprising a noise fault waveform generator, wherein the generated noise fault is added to the analog signal before it is output to the device for testing. A signal receiver configured to receive and generate an input data stream from one or more input signals.
A bit error trigger generator configured to generate a bit error based on a comparison of a static trigger pattern with a portion of the input data stream above.
After the bit error trigger is generated, at least one of the one or more input signals is in memory containing a portion of the stored signal that existed before the bit error trigger was generated. A test and measurement device with a memory storage that stores relevant data and measurements. The signal receiver is configured to perform the first test before the bit error is triggered, and the signal receiver performs the second test after the bit error is triggered. The test and measurement device according to claim 17 , which is configured to be the same. The test according to claim 17 , wherein one or more of the input signals are received from the device or communication link, and the test measuring device further comprises a fault generator and a transmitter coupled to the device or communication link. measuring device. The fault generator is configured to generate the first set of faults before the bit error is triggered, and the fault generator is configured to generate the first set of faults after the bit error is triggered. The test measuring device according to claim 17 , which is configured to generate a set.