CN114978960B - Ethernet frame header trigger - Google Patents
Ethernet frame header trigger Download PDFInfo
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- CN114978960B CN114978960B CN202210914293.9A CN202210914293A CN114978960B CN 114978960 B CN114978960 B CN 114978960B CN 202210914293 A CN202210914293 A CN 202210914293A CN 114978960 B CN114978960 B CN 114978960B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
- H04L43/0823—Errors, e.g. transmission errors
- H04L43/0829—Packet loss
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/06—Management of faults, events, alarms or notifications
- H04L41/0695—Management of faults, events, alarms or notifications the faulty arrangement being the maintenance, administration or management system
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/08—Configuration management of networks or network elements
- H04L41/0866—Checking the configuration
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Abstract
The application discloses ethernet frame head trigger includes: FPGA chip, memory chip, ethernet chip, SMA interface, JTAG interface and ethernet interface, wherein: the Ethernet chip is electrically connected with the Ethernet interface and used for receiving an Ethernet data packet transmitted by the network performance testing equipment through the Ethernet interface; the FPGA chip is electrically connected with the Ethernet chip and the storage chip and is used for converting each Ethernet data packet into a corresponding pulse signal; the SMA interface is electrically connected with the FPGA chip and used for outputting a pulse signal; the JTAG interface is electrically connected with the FPGA chip and is used for configuring and debugging the FPGA chip; the storage chip is electrically connected with the FPGA chip and used for storing data. The Ethernet frame header trigger in the application can realize the calibration of the network performance test equipment.
Description
Technical Field
The embodiment of the application relates to the field of metering, in particular to an Ethernet frame header trigger.
Background
Data communication is a communication mode generated by combining communication technology and computer technology. With the continuous evolution of computer network technology, multimedia communication technology and other technologies, the applications of data centers, cloud computing, internet of things and the like are rapidly developed, the proportion of data communication in the communication industry is higher and higher, and the data communication network also becomes an important component in the communication network.
In a data communication network, a network performance testing device needs to be used to test the data communication network, such as simulating a time delay, a packet loss rate, and the like in a data communication process, so as to evaluate the performance of the network or the network device under different network loads. In the prior art, before a network performance testing device is used to test a data communication network, the network performance testing device generally needs to be calibrated. However, the inventors have found that in order to facilitate calibration of the network performance testing device, it is generally necessary to convert the network data into a pulse signal and then calibrate the network performance testing device according to the pulse signal. However, the prior art lacks a device for converting network data into pulse signals, so that the network performance test equipment is difficult to calibrate.
Disclosure of Invention
The embodiment of the application provides an Ethernet frame header trigger, which is used for solving the problem that the prior art is difficult to calibrate network performance test equipment.
In order to solve the foregoing technical problem, an embodiment of the present application provides an ethernet frame header trigger, including: FPGA chip, memory chip, ethernet chip, SMA interface, JTAG interface and ethernet interface, wherein: the Ethernet chip is electrically connected with the Ethernet interface and is used for receiving an Ethernet data packet transmitted by the network performance testing equipment through the Ethernet interface; the FPGA chip is electrically connected with the Ethernet chip and the storage chip and is used for converting each Ethernet data packet into a corresponding pulse signal; the SMA interface is electrically connected with the FPGA chip and used for outputting a pulse signal; the JTAG interface is electrically connected with the FPGA chip and is used for configuring and debugging the FPGA chip; the storage chip is electrically connected with the FPGA chip and used for storing data.
Optionally, the FPGA chip includes a data receiving module, a data packet checking module, and a pulse generating module, wherein: the data receiving module is used for receiving the Ethernet data packet transmitted by the Ethernet chip; the data packet checking module is used for carrying out data checking on the Ethernet data packet; and the pulse generation module is used for converting each Ethernet data packet after verification into a corresponding pulse signal.
Optionally, the data packet checking module is configured to perform cyclic redundancy check on the ethernet data packet.
Optionally, the memory chip is a Flash chip.
The embodiment of the present application further provides a time delay calibration device of a network performance testing device, including a traffic generator, a splitter, a first ethernet frame header trigger, a second ethernet frame header trigger, a network performance testing device and a frequency meter, where the first ethernet frame header trigger and the second ethernet frame header trigger are the ethernet frame header triggers as described above, where: the traffic generator is used for generating Ethernet traffic; the splitter is configured to forward the ethernet traffic into two paths of outputs, where one path of output is output to the first ethernet frame header trigger, and the other path of output is output to the network performance test device; the first ethernet frame header trigger is configured to synchronously convert a plurality of ethernet packets in received ethernet traffic into corresponding pulse signals, where each ethernet packet is synchronously converted into one pulse signal; the network performance testing device is used for outputting the received Ethernet flow to the second Ethernet frame header trigger in a set time delay; the second ethernet frame header trigger is used for synchronously converting a plurality of ethernet data packets in the received ethernet traffic into corresponding pulse signals; and the frequency meter is used for measuring the time interval between the pulse signal output by the first Ethernet frame header trigger and the pulse signal output by the second Ethernet frame header trigger.
The embodiment of the present application further provides a packet loss rate calibration apparatus for a network performance testing device, including a traffic generator, an ethernet frame header trigger, a network performance testing device and a frequency meter, where the ethernet frame header trigger is the ethernet frame header trigger as described above, where: the flow generator is used for generating Ethernet flow; the network performance testing equipment is used for outputting the received Ethernet flow to the Ethernet frame head trigger at a set packet loss rate; the Ethernet frame header trigger is used for synchronously converting a plurality of Ethernet data packets in the received Ethernet flow into corresponding pulse signals; and the frequency meter is used for counting the number of pulse signals output from the Ethernet frame head trigger.
Optionally, the traffic generator is configured to generate ethernet traffic in a fixed number traffic mode.
The Ethernet frame head trigger converts the Ethernet data packet transmitted by the Ethernet chip into the pulse signal through the FPGA chip, thereby conveniently synchronously converting the Ethernet signal into the pulse signal and conveniently calibrating the network performance testing equipment.
Drawings
The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiment(s) of the application and together with the description serve to explain the application and not limit the application. In the drawings:
fig. 1 is a schematic diagram of a hardware architecture of an ethernet frame header trigger according to an embodiment of the present application;
fig. 2 is a schematic hardware architecture diagram of a delay calibration apparatus of a network performance testing device in an embodiment of the present application;
fig. 3 is a schematic diagram of a hardware architecture of a packet loss rate calibration apparatus of a network performance testing device in an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that the descriptions relating to "first", "second", etc. in the embodiments of the present application are only for descriptive purposes and are not to be construed as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between the various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should not be considered to exist, and is not within the protection scope of the present application.
As shown in fig. 1, an embodiment of the present application provides an ethernet frame header trigger, including: the FPGA chip comprises an FPGA chip 10, a memory chip 11, an Ethernet chip 12, an SMA interface 13, a JTAG interface 14 and an Ethernet interface 15.
The ethernet chip 12 is electrically connected to the ethernet interface 15, and is configured to receive, through the ethernet interface 15, an ethernet data packet transmitted by a network performance testing device. The network performance testing device is used for simulating the performance of a network or network equipment under different network loads, and can be a network damage instrument.
In this embodiment, the ethernet interface 15 is connected to the network performance testing device through a network cable, so that the network performance testing device can transmit network data to the ethernet chip 12 through the ethernet interface 15.
In one embodiment, the ethernet chip 12 is available from Realtek corporation.
The FPGA chip 10 is electrically connected to the ethernet chip 12 and the memory chip 11, and is configured to convert each ethernet packet into a corresponding pulse signal.
In this embodiment, the FPGA chip 10 may perform data communication with the ethernet chip 12 through a bus, and configure or read a register inside the ethernet chip 12 through an MDI/MDIO management interface. The FPGA chip 10 may also communicate data with the memory chip 11 via a bus. As an example, the FPGA chip may be a product of Xilinx corporation.
In an exemplary embodiment, the FPGA chip includes a data receiving module, a packet verifying module, and a pulse generating module.
The data receiving module is configured to receive an ethernet data packet transmitted by the ethernet chip 12.
In an embodiment, the data receiving module may receive an ethernet packet (also referred to as an ethernet frame) by using a state machine, that is, the receiving process of the ethernet frame is controlled by a condition of state transition.
And the data packet checking module is used for carrying out data checking on the Ethernet data packet.
In this embodiment, after the data receiving module receives the ethernet data packet, data verification processing is performed on the ethernet data packet to verify whether the received ethernet data packet is correct.
In an exemplary embodiment, each ethernet packet includes a CRC (Cyclic Redundancy Check) code with 4 bytes, so in this embodiment, the packet checking module may implement a Cyclic Redundancy Check on the ethernet packet by using a combinational logic circuit to verify whether the received ethernet packet is correct.
And the pulse generation module is used for synchronously converting each verified Ethernet data packet into a corresponding pulse signal.
In this embodiment, when the pulse generation module converts each verified ethernet packet into a corresponding pulse signal, the pulse generation module may generate a pulse signal with a certain width based on an FPGA clock, and the generated pulse signal may last for 32 clock cycles. For example, in a gigabit ethernet, the clock frequency is 125MHz, and the pulse width is about 256ns.
The SMA interface 13 is electrically connected to the FPGA chip 10, and is configured to output a pulse signal.
In this embodiment, after the FPGA chip 10 converts the ethernet packet into a pulse signal, the ethernet packet may be connected to a frequency meter, an oscilloscope, and the like through the SMA interface 13 via a radio frequency cable, so as to transmit the pulse signal to the frequency meter, the oscilloscope, and the like.
The JTAG interface 14 is electrically connected to the FPGA chip 10, and is configured and debugged for the FPGA chip 10. In one embodiment, the compiled program may be downloaded into the FPGA chip 10 through the JTAG interface 14. In another embodiment, the configuration program of the memory chip 11 may also be downloaded into the memory chip 11 through the JTAG interface 14.
The memory chip 11 is electrically connected to the FPGA chip 10 and is configured to store data.
In this embodiment, the memory chip 11 may be a Flash chip.
In the ethernet frame header trigger in this embodiment, the FPGA chip converts the ethernet packet transmitted by the ethernet chip into the pulse signal, so as to conveniently convert the ethernet signal into the pulse signal, which is convenient for calibrating the network performance testing device.
As shown in fig. 2, an embodiment of the present application further provides a delay calibration apparatus for a network performance testing device, which includes a traffic generator 20, a splitter 21, a first ethernet frame header trigger 22, a second ethernet frame header trigger 23, a network performance testing device 24, and a frequency meter 25.
A traffic generator 20 for generating ethernet traffic.
In this embodiment, the traffic generator 20 may generate ethernet traffic of a specific protocol and transmission rate, such as generating UDP protocol and ethernet traffic of 1000Mbps rate.
The splitter 21 is configured to forward the ethernet traffic into two paths of outputs, where one path of output is sent to the first ethernet frame header trigger 22, and the other path of output is sent to the network performance test device 24.
In this embodiment, the splitter 21 is a splitter, and the ethernet traffic input to the splitter 21 can be split into two ethernet traffic after being processed by the splitter 21.
The first ethernet frame header trigger 22 synchronously converts a plurality of ethernet packets in the received ethernet traffic into corresponding pulse signals, wherein each ethernet packet is synchronously converted into one pulse signal.
In this embodiment, the first ethernet frame header trigger 22 is the ethernet frame header trigger in the above embodiment, and the specific structure thereof is not described in detail in this embodiment. After receiving the ethernet traffic output from the demultiplexer 21, the first ethernet frame header trigger 22 will synchronously convert each ethernet packet in the ethernet traffic into a corresponding pulse signal. As an example, the ethernet traffic includes 1000 ethernet packets, and 1000 pulse signals are generated after the ethernet packet is processed by the first ethernet frame header trigger 22.
And the network performance testing device 24 is configured to output the received ethernet traffic to the second ethernet frame header trigger with a set time delay.
In this embodiment, the network performance testing device 24 is preferably a network impairment tester.
As an example, assuming that the set time delay is 1 ms, the network performance testing device 24 will delay the reception of the ethernet traffic by 1 ms before outputting the received signal to the second ethernet frame header trigger 23.
It should be noted that the setting of the time delay may be set by a user according to an actual situation, and a specific value thereof is not limited in this embodiment.
The second ethernet frame header trigger 23 is configured to synchronously convert a plurality of ethernet packets in the received ethernet traffic into corresponding pulse signals.
In this embodiment, the second ethernet frame header trigger 23 is the ethernet frame header trigger in the foregoing embodiment, and the specific structure thereof is not described in detail in this embodiment. After receiving the ethernet traffic output by the network performance testing device 24, the second ethernet frame header trigger 23 will synchronously convert each ethernet packet in the ethernet traffic into a corresponding pulse signal. As an example, the ethernet traffic includes 1000 ethernet packets, and 1000 pulse signals are generated after the processing by the first ethernet frame header trigger 22.
And a frequency meter 25 for measuring a time interval between the pulse signal output by the first ethernet frame header trigger 22 and the pulse signal output by the second ethernet frame header trigger 23.
In this embodiment, after receiving the two pulse signals, the frequency meter 25 calculates the time intervals of the two received pulse signals one by one, that is, sequentially calculates the time m of the 1 st pulse signal in the first received pulse signal 1 The time n of the 1 st pulse signal in the received second path of pulse signals 1 Time interval t of 1 =m 1 -n 1 Calculating the time m of the 2 nd pulse signal in the received first path of pulse signal 2 The time n of the 2 nd pulse signal in the received second pulse signal is compared with 2 Time interval t of 2 =m 2 -n 2 8230, calculating the time m of the jth pulse signal in the received first pulse signal j The time n of the jth pulse signal in the received second path of pulse signals j Time interval t of j =m j -n j Wherein j is an integer greater than or equal to 1.
In this embodiment, after obtaining the time intervals of all the pulse signals, the obtained average value of all the time intervals may be used as the delay value of the network performance testing device 24. After obtaining the delay value, the delay value may be compared with a delay value set by a user, so as to calibrate the delay parameter value of the network performance testing device 24 according to the difference between the two values.
In the present embodiment, the frequency meter 25 may set the measurement mode to the time interval measurement mode when measuring the time interval.
The time delay calibration device of the network performance test equipment in the embodiment can directly trace the time delay parameters to the frequency meter, so that source-meter closed loop mutual test is avoided.
As shown in fig. 3, an embodiment of the present application further provides a device for calibrating a packet loss rate of a network performance testing apparatus, which includes a traffic generator 30, an ethernet frame header trigger 31, a network performance testing apparatus 32, and a frequency meter 33.
A traffic generator 30 for generating ethernet traffic.
In this embodiment, the traffic generator 30 may generate ethernet traffic of a specific protocol and transmission rate, such as ethernet traffic generating UDP protocol and 1000Mbps rate.
In an exemplary embodiment, traffic generator 30 generates ethernet traffic in a fixed number traffic pattern when generating ethernet traffic, where a fixed number traffic pattern refers to a pattern that generates a fixed number of ethernet packets. For example, 10000 ethernet traffic packets need to be generated, and after the traffic generator 30 mode is set to the fixed number traffic mode, the traffic generator 30 will not generate the ethernet packets after generating the 10000 ethernet traffic packets.
And the network performance test device 32 is configured to output the received ethernet traffic to the ethernet frame header trigger 31 at the set packet loss rate.
In this embodiment, the network performance testing device 32 is preferably a network impairment tester.
As an example, assuming that the set packet loss rate is 10%, the ethernet traffic is composed of 10000 ethernet packets, after receiving the ethernet traffic, the network performance testing device 32 performs packet loss processing on the received ethernet traffic to discard 1000 ethernet packets, and outputs the remaining 9000 ethernet packets to the ethernet frame header trigger 31.
It should be noted that the setting of the packet loss rate may be set by a user according to actual situations, and the specific value is not limited in this embodiment.
The ethernet frame header trigger 31 is configured to synchronously convert a plurality of ethernet packets in the received ethernet traffic into corresponding pulse signals.
In this embodiment, the ethernet frame header trigger 31 is the ethernet frame header trigger in the above embodiment, and the specific structure thereof is not described in detail in this embodiment. After receiving the ethernet traffic output by the network performance testing device 32, the ethernet frame header trigger 31 will synchronously convert each ethernet packet in the ethernet traffic into a corresponding pulse signal. As an example, the ethernet traffic includes 1000 ethernet packets, and 1000 pulse signals are generated after being processed by the ethernet frame header trigger 31.
And a frequency meter 33 for counting the number of pulse signals output from the ethernet frame header flip-flop.
In this embodiment, the frequency meter 33 counts the number of all received pulse signals.
In one embodiment, to count the number of pulses conveniently, the frequency meter 33 may be set to a counting mode, such that the frequency meter 33 will count up by 1 each time it receives a pulse signal.
After counting the sum of the pulse signals output by the ethernet frame header trigger 31, the sum is counted by the number N 1 And the number N of ethernet packets contained in the ethernet traffic generated by the traffic generator 30 2 Comparing to obtain the packet loss rate, namely the packet loss rate = (N) 2 - N 1 ）/ N 2 。
After obtaining the packet loss rate, the packet loss rate may be compared with a packet loss rate set by a user, so as to calibrate a packet loss rate parameter value of the network performance testing device 32 according to a difference between the packet loss rate and the packet loss rate.
The packet loss rate calibration device of the network performance test equipment in the embodiment can directly trace the packet loss rate parameter to the frequency meter, so that source-meter closed loop mutual test is avoided.
Finally, it should be noted that: although the present application has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments described in the foregoing embodiments, or equivalents may be substituted for elements thereof. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (7)
1. An ethernet frame header trigger, comprising: FPGA chip, memory chip, ethernet chip, SMA interface, JTAG interface and ethernet interface, wherein:
the Ethernet chip is electrically connected with the Ethernet interface and is used for receiving an Ethernet data packet transmitted by the network performance testing equipment through the Ethernet interface;
the FPGA chip is electrically connected with the Ethernet chip and the storage chip and is used for converting each Ethernet data packet into a corresponding pulse signal, wherein the FPGA chip generates the pulse signal based on a system clock in the FPGA, and the pulse signal is used for calibrating the network performance test equipment;
the SMA interface is electrically connected with the FPGA chip and used for outputting a pulse signal;
the JTAG interface is electrically connected with the FPGA chip and is used for configuring and debugging the FPGA chip;
the storage chip is electrically connected with the FPGA chip and used for storing data.
2. An ethernet frame header trigger according to claim 1, wherein the FPGA chip comprises a data receiving module, a data packet checking module and a pulse generating module, wherein:
the data receiving module is used for receiving the Ethernet data packet transmitted by the Ethernet chip;
the data packet checking module is used for carrying out data checking on the Ethernet data packet;
and the pulse generation module is used for converting each verified Ethernet data packet into a corresponding pulse signal.
3. An ethernet frame header trigger according to claim 2, wherein said packet checking module is configured to perform a cyclic redundancy check on the ethernet packet.
4. An ethernet frame header trigger according to claim 3, wherein the memory chip is a Flash chip.
5. A delay calibration device of a network performance testing device, comprising a traffic generator, a splitter, a first ethernet frame header trigger, a second ethernet frame header trigger, a network performance testing device, and a frequency meter, wherein the first ethernet frame header trigger and the second ethernet frame header trigger are the ethernet frame header triggers according to any one of claims 1 to 4, wherein:
the flow generator is used for generating Ethernet flow;
the splitter is configured to forward the ethernet traffic into two paths of outputs, where one path of output is output to the first ethernet frame header trigger, and the other path of output is output to the network performance test device;
the first ethernet frame header trigger is configured to synchronously convert a plurality of ethernet packets in received ethernet traffic into corresponding pulse signals, where each ethernet packet is synchronously converted into one pulse signal;
the network performance testing device is used for outputting the received Ethernet flow to the second Ethernet frame header trigger in a set time delay;
the second ethernet frame header trigger is used for synchronously converting a plurality of ethernet data packets in the received ethernet traffic into corresponding pulse signals;
and the frequency meter is used for measuring the time interval between the pulse signal output by the first Ethernet frame header trigger and the pulse signal output by the second Ethernet frame header trigger.
6. A packet loss rate calibration apparatus for a network performance testing device, comprising a traffic generator, an ethernet frame header trigger, a network performance testing device and a frequency meter, wherein the ethernet frame header trigger is the ethernet frame header trigger according to any one of claims 1 to 4, wherein:
the flow generator is used for generating Ethernet flow;
the network performance testing equipment is used for outputting the received Ethernet flow to the Ethernet frame head trigger at a set packet loss rate;
the Ethernet frame header trigger is used for synchronously converting a plurality of Ethernet data packets in the received Ethernet flow into corresponding pulse signals;
and the frequency meter is used for counting the number of pulse signals output from the Ethernet frame head trigger.
7. The apparatus of claim 6, wherein the traffic generator is configured to generate ethernet traffic in a fixed number traffic mode.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1407834A (en) * | 2001-08-24 | 2003-04-02 | 深圳市中兴通讯股份有限公司上海第二研究所 | Method for realizing transmission of time division multichannel pulse modified signals in ether network |
| CN1538679A (en) * | 2003-04-15 | 2004-10-20 | 中兴通讯股份有限公司 | Method of transmitting time division multic channel pulse coding modulation signal in Ethernet |
| KR20070067280A (en) * | 2005-12-23 | 2007-06-28 | 엘지노텔 주식회사 | Voip system vocoder including ethernet controller and thereof data transferring method |
| CN210839620U (en) * | 2019-11-27 | 2020-06-23 | 东软集团股份有限公司 | Vehicle-mounted Ethernet signal relay equipment |
-
2022
- 2022-08-01 CN CN202210914293.9A patent/CN114978960B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1407834A (en) * | 2001-08-24 | 2003-04-02 | 深圳市中兴通讯股份有限公司上海第二研究所 | Method for realizing transmission of time division multichannel pulse modified signals in ether network |
| CN1538679A (en) * | 2003-04-15 | 2004-10-20 | 中兴通讯股份有限公司 | Method of transmitting time division multic channel pulse coding modulation signal in Ethernet |
| KR20070067280A (en) * | 2005-12-23 | 2007-06-28 | 엘지노텔 주식회사 | Voip system vocoder including ethernet controller and thereof data transferring method |
| CN210839620U (en) * | 2019-11-27 | 2020-06-23 | 东软集团股份有限公司 | Vehicle-mounted Ethernet signal relay equipment |
Non-Patent Citations (1)
| Title |
|---|
| 《自适应拥塞控制系统中 LDoS 攻击仿真和分析》;刘陶等;《系统仿真学报》;20110508;第23卷(第5期);正文1-3页 * |
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