CN110535789A - SRIO-ETH protocol conversion chip checking device and method - Google Patents
SRIO-ETH protocol conversion chip checking device and method Download PDFInfo
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- CN110535789A CN110535789A CN201910628138.9A CN201910628138A CN110535789A CN 110535789 A CN110535789 A CN 110535789A CN 201910628138 A CN201910628138 A CN 201910628138A CN 110535789 A CN110535789 A CN 110535789A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
- H04L49/109—Integrated on microchip, e.g. switch-on-chip
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/08—Protocols for interworking; Protocol conversion
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2212/00—Encapsulation of packets
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Abstract
The present invention provides a kind of SRIO-ETH protocol conversion chip checking device and methods, including the end TX, the end RX and packet to count transformation rule computing module, and it includes packet counting submodule and macrodefinition submodule that the packet, which counts transformation rule computing module,；The end TX is for transmission source protocol package to protocol translation chip, protocol conversion chip parses and extracts the payload of the source protocol packet and composition target protocol packet is routed to the end RX, the end the RX parsing target protocol packet obtains payload, when the source protocol is SRIO agreement, the target protocol corresponds to ETH agreement, when the source protocol is ETH agreement, the ETH agreement corresponds to SRIO agreement, the macrodefinition submodule is used to configure counting check information for the end RX and the end TX, the packet counting submodule carries out packet counting after extracting the counting check information.The present invention improves the power of test of the protocol conversion chip to different fragment rules, keeps the whole device scope of application wider, flexibility is higher.
Description
Technical field
The invention belongs to chip checking technical fields, verify device more particularly, to a kind of SRIO-ETH conversion chip.
Background technique
With the gradually popularization of 5G and Internet of Things, all things on earth can all interconnect Basic Education for Techers disintegrate each agreement it
Between the chains that communicate, need protocol translation chip to erect the bridge to interconnect.ETH (Ethernet, ETH) agreement is to make extensively
A kind of agreement is suitable for down toward physical layer because supporting multilayer encapsulation up to application layer, applied widely, flexibility
It is high.And high performance distributed embedded processing system then mostly uses Serial RapidIO (SRIO) to be used as interface standard,
Signal interference is effectively reduced in SRIO signal lead less, can save pin resource while provide the transmission of high accuracy, be widely used
It is connected in embedded interconnection with the cabling of backboard.Therefore there is the protocol conversion core of a large amount of realization ETH to SRIO in Vehicles Collected from Market
Piece provides the data transmission channel across framework for hardware-accelerated system.
The bridging device of existing R & D design ETH to SRIO, the agreement of each high speed data interface can software definition at
Any one in above two agreement, can be realized clog-free, the low time delay, highly reliable interconnection between two kinds of heterogeneous protocol
Intercommunication.The bridging device application scenarios of ETH and SRIO are very extensive, and function is very powerful, and successfully exploitation will be in many fields
It is greatly convenient to bring.
In the development phase of chip, how to verify conversion chip successfully to have the function of protocol conversion is highly important class
Topic.The inspection that protocol conversion chip functions are completed currently without suitable scheme, for the functional verification of single-protocol forwarding chip
Whether testing scheme is counted and is compared by statistics transmitting terminal and receiving end packet, to examine the function of forwarding chip normal.
Protocol conversion chip can be verified by UVM logical simulation, but the method simulation velocity is slow, works as digital circuit
When scale is bigger, logical simulation speed can become slower, and the proving period that will lead to entire project becomes tediously long, restrain entire
The delivery cycle of project；The functional verification based on FPGA is generallyd use, is the side for counting and comparing by transmitting-receiving both ends statistics packet
Formula carries out the function of verifying forwarding chip, in the function of indentification protocol conversion chip, whether can not directly compare packet counting
It is equal to judge whether protocol conversion function is normal.Or only by examining CRC check position that can not determine the correct of protocol conversion
Property, because of the case where there may be whole segment data packet loss.Or the scheme of accumulated counts is carried out by counting in transmitting terminal packet
Equal single-protocols forwarding capability checkschema, is not all suitable for the function check of protocol conversion chip.It is contemplated that looking into test
The PAYLOAD for seeing transmitting terminal and receiving end, is manually compared, but is taken time and effort, and does not support the test of line rate.
During protocol conversion, data packet is in transmission process because of protocol conversion, the number of different agreement support
Long different according to packet, the number of data packet may change at this time, it is desirable to compare the data packet number of receiving end and transmitting terminal
Whether meet the rule of protocol conversion, the transformation rule between different agreement can only be analyzed by tester, agreement is calculated and turns
The variation of front and back packet quantity is changed, and then whether comparison data packet number is correct, certainly will consume a large amount of human resources in this way, examine
It is larger to consider test scene quantity of giving out a contract for a project, and being bound to can not line rate real-time verification.
Most of agreements can cut packet rule using customized simultaneously, and when changing accept port, cutting packet rule may
Change completely, while the slice rule in view of being ignorant of between port may be different, if configuring packet counting check one by one again
Rule may influence the speed entirely tested.
Summary of the invention
In view of this, the present invention is directed to propose a kind of SRIO-ETH protocol conversion chip checking device and method, to solve
The above problem.
In order to achieve the above objectives, the technical scheme of the present invention is realized as follows:
SRIO-ETH protocol conversion chip checking device, including the end TX, the end RX and packet count transformation rule computing module,
It includes packet counting submodule and macrodefinition submodule that the packet, which counts transformation rule computing module,；
For transmission source protocol package to protocol translation chip, protocol conversion chip parses and extracts the source association at the end TX
It discusses the payload payload of packet and composition target protocol packet is routed to the end RX, the end the RX parsing target protocol packet obtains
Payload payload is obtained, when the source protocol is SRIO agreement, the target protocol corresponds to ETH agreement, the source protocol
When for ETH agreement, the ETH agreement corresponds to SRIO agreement, and the macrodefinition submodule is used for as the end RX and the TX
End configuration counting check information, the packet counting submodule carry out packet counting after extracting the counting check information.
Further, the end TX includes sequentially connected PAYLOAD_GEN module, PKT_GEN module, TX_PKT_CNT
Module and TX_Port module, the PAYLOAD_GEN module are used to generate the payload in the source protocol packet
Payload, the PKT_GEN module are used to the payload being packaged into source protocol packet, and the TX_PKT_CNT module is used for
The quantity of the source protocol packet is calculated, the TX_Port module is the end TX port.
Further, the end RX includes sequentially connected RX_Port module, RX_PKT_CNT module, PKT_GET module
And PAYLOAD_GET module, the RX_Port module are the end RX port, the RX_PKT_CNT module is for calculating
The quantity of the target protocol packet, the PKT_GET module is for parsing the target protocol packet, the PAYLOAD_GET mould
Block is used to obtain the payload of the target protocol packet.
Further, the macrodefinition submodule includes SDI interface unit, for the TX_Port module and RX_
Port module is configured, and further includes Macro_Define unit, for the TX_PKT_CNT module and RX_PKT_CNT
Module configures counting check information.
Further, the packet counting submodule, including GET_CNT unit, for extracting the end TX and the end RX
Counting check information, further include PKT_CNT_CALCULATE unit, for wrap count.
Further, the TX_PKT_CNT module and RX_PKT_CNT module further include Packet type counting unit, are passed through
The FTYPE field of different Packet types is extracted to complete Packet type and count.
A kind of SRIO-ETH protocol conversion chip verification method using above-mentioned verifying device, which is characterized in that including such as
Lower step:
Step 1: the end TX, which generates payload payload and is packaged into source protocol packet, is sent to protocol conversion chip；
Step 2: the protocol conversion chip receives the source protocol packet and is parsed and encapsulate generation target protocol packet；
Step 3: the end RX, which receives the target protocol packet and parses, generates payload payload；
Step 4: the end TX and the end RX being configured by the macrodefinition submodule；
Step 5: packet counting being carried out by the packet counting submodule, and exports packet count results；
Further, the step 1 further includes that the quantity of the source protocol packet is calculated by the TX_PKT_CNT module,
The step 3 further includes that the quantity of the target protocol packet is calculated by the RX_PKT_CNT module.
Further, the step 4 includes: by the SDI interface unit to the TX_Port module and RX_Port
Module is configured, and by the Macro_Define unit, to the TX_PKT_CNT module and RX_PKT_CNT module
Configure counting check information.
Further, the step 5 includes:
Step 51: the received maximum packet length RX_MAX_L in packet length TX_P_L, RX end, packet count results are sent to the end TX
Pre_C_Cnt is initialized；
Step 52: the counting check information being extracted by GET_CNT unit, and starts to verify；
Step 53: packet counting being carried out by the PKT_CNT_CALCULATE unit: by the length TX_P_L of source protocol packet
It is compared with receiving end maximum packet length RX_MAX_L；
Step 54: as TX_P_L > RX_MAX_L, packet count results Pre_C_Cnt=(TX_P_L/RX_MAX_L)+X, X
>=1, as TX_P_L≤RX_MAX_L, packet count results Pre_C_Cnt=GEN_Cnt, wherein GEN_Cnt is the end TX packet
It counts.
Compared with the existing technology, a kind of SRIO-ETH protocol conversion chip checking device and method of the present invention has
Following advantage:
(1) verifying device of the present invention is provided with packet counting submodule and macrodefinition submodule, greatlys improve
To the power of test of the protocol conversion chip of different fragment rules, keep the whole device scope of application wider, flexibility is higher.
(2) present invention supports two-way simultaneous to send data packet and verifies.
(3) it is provided with Packet type counting unit, the data of later period debugging efforts is facilitated to acquire.
Detailed description of the invention
The attached drawing for constituting a part of the invention is used to provide further understanding of the present invention, schematic reality of the invention
It applies example and its explanation is used to explain the present invention, do not constitute improper limitations of the present invention.In the accompanying drawings:
Fig. 1 is that the end TX described in the embodiment of the present invention is ETH protocol devices, the verifying dress when end RX is SRIO protocol devices
Set structural schematic diagram；
Fig. 2 is verification method flow diagram described in the embodiment of the present invention；
It is protocol devices that Fig. 3, which is the end SRIO described in the embodiment of the present invention, the verifying device when end RX is ETH protocol devices
Structural schematic diagram；
Verifying ETH agreement turns SRIO agreement while Fig. 4 is described in the embodiment of the present invention and SRIO agreement turns ETH agreement
Verify apparatus structure schematic diagram.
Specific embodiment
The present invention will be described in detail below with reference to the accompanying drawings and embodiments.
SRIO-ETH protocol conversion chip checking device, including the end TX, the end RX and packet count transformation rule computing module,
It includes packet counting submodule and macrodefinition submodule that the packet, which counts transformation rule computing module,；
For transmission source protocol package to protocol conversion chip, the protocol conversion chip is parsed and is extracted described at the end TX
The payload and composition target protocol packet of source protocol packet are routed to the end RX, and the end the RX parsing target protocol packet obtains
Payload, when the source protocol is SRIO agreement, the target protocol corresponds to ETH agreement, and the source protocol is ETH agreement
When, the ETH agreement corresponds to SRIO agreement, and the macrodefinition submodule is used to count for the end RX and the end TX configuration
Check information, the packet counting submodule carry out packet counting after extracting the counting check information.
The end TX include sequentially connected PAYLOAD_GEN module, PKT_GEN module, TX_PKT_CNT module and
TX_Port module, the PAYLOAD_GEN module is used to generate the payload payload in the source protocol packet, described
PKT_GEN module is used to for the payload being packaged into source protocol packet, and the TX_PKT_CNT module is for calculating the source association
The quantity of packet is discussed, the TX_Port module is the end TX port.
The end RX include sequentially connected RX_Port module, RX_PKT_CNT module, PKT_GET module and
PAYLOAD_GET module, the RX_Port module are the end RX port, and the RX_PKT_CNT module is described for calculating
The quantity of target protocol packet, the PKT_GET module are used for parsing the target protocol packet, the PAYLOAD_GET module
In the payload for obtaining the target protocol packet.
The macrodefinition submodule includes SDI interface unit, for the TX_Port module and RX_Port module into
Row configuration, further includes Macro_Define unit, based on to the TX_PKT_CNT module and the configuration of RX_PKT_CNT module
Number check information.
The packet counting submodule, including GET_CNT unit, for extracting the counting check at the end TX Yu the end RX
Information further includes PKT_CNT_CALCULATE unit, for carrying out packet counting.
The TX_PKT_CNT module and RX_PKT_CNT module further include Packet type counting unit, by extracting different packets
The FTYPE field of type counts to complete Packet type, if SRIO protocol package includes following 6 seed type: NREAD, NWRITE,
NWRITE_R, DOORBELL, MESSAGE, RESPONS generate different queues for different types of packet format and are counted,
Because of the packet of different transaction types, FTYPE is different, counting can be completed by extracting FTYPE field:
The present invention also proposes a kind of SRIO-ETH protocol conversion chip verification method using above-mentioned verifying device, such as Fig. 2
It is shown, include the following steps:
Step 1: at the end TX, the payload in source protocol packet being generated by the PAYLOAD_GEN module
Payload, and by being sent to protocol conversion chip after PKT_GEN module packaged source protocol package；
Step 2: the protocol conversion chip receives the source protocol packet and is parsed and encapsulate generation target protocol packet；
Step 3: at the end RX, target protocol packet being parsed by the PKT_GET module, passes through the PAYLOAD_GET
Module obtains the payload payload in target protocol packet and receives the target protocol packet and parse generation payload
payload；
Step 4: the end TX and the end RX being configured by the macrodefinition submodule；
Step 5: packet counting being carried out by the packet counting submodule, and exports packet count results；
Preferably, the step 1 further includes that the quantity of the source protocol packet, institute are calculated by the TX_PKT_CNT module
Stating step 3 further includes that the quantity of the target protocol packet is calculated by the RX_PKT_CNT module, and the step 4 includes: logical
It crosses the SDI interface unit to configure the TX_Port module and RX_Port module, and passes through the Macro_
Define unit configures counting check information to the TX_PKT_CNT module and RX_PKT_CNT module.
Preferably, the step 5 includes:
Step 51: the received maximum packet length RX_MAX_L in packet length TX_P_L, RX end, packet count results are sent to the end TX
Pre_C_Cnt is initialized；
Step 52: the counting check information being extracted by GET_CNT unit, and starts to verify；
Step 53: packet counting being carried out by the PKT_CNT_CALCULATE unit: by the length TX_P_L of source protocol packet
It is compared with receiving end maximum packet length RX_MAX_L；
Step 54: as TX_P_L > RX_MAX_L, packet count results Pre_C_Cnt=(TX_P_L/RX_MAX_L)+X, X
>=1, as TX_P_L≤RX_MAX_L, packet count results Pre_C_Cnt=GEN_Cnt, wherein GEN_Cnt is the end TX packet
It counts.Under normal circumstances, the part beyond the received maximum packet length in the end RX is directly encapsulated as 1 packet, and the value of X is 1 at this time, but
In view of the regular possible face type user versatility of unpacking of ratio complementing part may be split as the length of 2 integral number power, or
Person uses the rule of unpacking for being applicable in concrete scene, at this time X >=1.
Such as the case where Fig. 1 is the end TX, i.e., transmitting terminal is ETH protocol devices, and the end RX, i.e. receiving end are SRIO protocol devices,
The data packet of ETH protocol format is converted to the identifiable SRIO agreement number in the end RX by DUT module, that is, protocol conversion chip in figure
According to packet, at the end TX, by PKT_GEN module by payload data packet at the data packet of ETH agreement, DUT module includes
Parser unit, DE-Parser unit, PKT_Segment unit and Head_Maper unit, the DUT module receive ETH
Protocol package, and parsed by the Parser unit, the payload in the protocol package received is extracted and by described
Whether PKT_Segment unit judges, which need, divides, and reads target protocol encapsulating packet rule simultaneously by the Head_Maper unit
It is packaged by the DE-Parser unit, generates SRIO protocol data packet and is routed to the end RX, described in the end the RX warp
It is every that PAYLOAD_GET module obtains payload payload, the PAYLOAD_CHECK module record in SRIO protocol data packet
The payload length of a packet, via PKT_CNT_CALCULATE unit calculate SRIO agreement packet number, the end RX with
Packet count results are compared, and identification protocol conversion chip meets performance requirement if the two is identical.
In view of the fragment rule of the corresponding SRIO agreement of different port is different, pass through the SDI interface unit pair first
The TX_Port and RX_Port inputs macrodefinition command information, by the Macro_Define unit to the TX_PKT_
CNT module and TX_PKT_CNT module configure counting check information, wherein comprising each port protocol information, sending and receiving end state,
For the protocol information format of each port are as follows: (Port_Num, protocol type organize packet specification), GET_CNT unit, which extracts, to be counted
Check information, and packet counting is carried out by the PKT_CNT_CALCULATE unit, it is with the integral number power that sliced fashion is 2
Example, the ETH packet a length of 255 such as received will then generate the packet of 7 SRIO, and packet length is respectively 128,64,32,16,8,4,
2,1.The value of X is 7 at this time.
It is SRIO protocol devices if Fig. 3 is the end TX, the case where end RX is ETH protocol devices, because of SRIO agreement PAYLOAD
Length can be directly encapsulated as the packet of an independent ETH format, so the packet that ETH format can't occur turns
The case where turning to the fractionation packet that SRIO format packet is occurred, it is contemplated that there may be packets under certain special envoy's scenes
Counting is not still one-to-one relationship, so still reserving packet number computing module.
If Fig. 4 is two-way simultaneous transmission data packet and is verified, SRIO agreement can be verified simultaneously and turns ETH agreement and ETH agreement
Turn SRIO agreement, the end TX and the end RX are combined together, two endpoint devices need while bearing transmission to set in this case
Standby and calibration equipment function.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all in essence of the invention
Within mind and principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (10)
1.SRIO-ETH protocol conversion chip checking device, it is characterised in that: count transformation rule including the end TX, the end RX and packet
Computing module, it includes packet counting submodule and macrodefinition submodule that the packet, which counts transformation rule computing module,；
The end TX parses for transmission source protocol package to protocol translation chip, protocol conversion chip and extracts the source protocol packet
Payload payload and composition target protocol packet be routed to the end RX, the end the RX parsing target protocol packet is had
Effect load payload, when the source protocol is SRIO agreement, the target protocol corresponds to ETH agreement, and the source protocol is
When ETH agreement, the ETH agreement corresponds to SRIO agreement, and the macrodefinition submodule is used for as the end RX and the end TX
Counting check information is configured, the packet counting submodule carries out packet counting after extracting the counting check information.
2. SRIO-ETH protocol conversion chip checking device according to claim 1, it is characterised in that: the end TX includes
Sequentially connected PAYLOAD_GEN module, PKT_GEN module, TX_PKT_CNT module and TX_Port module, it is described
PAYLOAD_GEN module is used to generate the payload payload in the source protocol packet, and the PKT_GEN module is used for will
The payload is packaged into source protocol packet, and the TX_PKT_CNT module is used to calculate the quantity of the source protocol packet, described
TX_Port module is the end TX port.
3. SRIO-ETH protocol conversion chip checking device according to claim 1, it is characterised in that: the end RX includes
Sequentially connected RX_Port module, RX_PKT_CNT module, PKT_GET module and PAYLOAD_GET module, the RX_
Port module is the end RX port, and the RX_PKT_CNT module is used to calculate the quantity of the target protocol packet, described
PKT_GET module is for parsing the target protocol packet, and the PAYLOAD_GET module is for obtaining the target protocol packet
payload。
4. SRIO-ETH protocol conversion chip checking device according to claim 3, it is characterised in that: macrodefinition
Module includes SDI interface unit, further includes Macro_ for configuring to the TX_Port module and RX_Port module
Define unit, for configuring counting check information to the TX_PKT_CNT module and RX_PKT_CNT module.
5. SRIO-ETH protocol conversion chip checking device according to claim 3, it is characterised in that: the packet counts son
Module, including GET_CNT unit further include PKT_CNT_ for extracting the counting check information at the end TX Yu the end RX
CALCULATE unit is counted for wrapping.
6. SRIO-ETH protocol conversion chip checking device according to claim 3, it is characterised in that: the TX_PKT_
CNT module and RX_PKT_CNT module further include Packet type counting unit, by extracting the FTYPE field of different Packet types come complete
It is counted at Packet type.
7. the SRIO-ETH protocol conversion chip verification method of application verifying device as claimed in any one of claims 1 to 6,
It is characterized in that, includes the following steps:
Step 1: the end TX, which generates payload payload and is packaged into source protocol packet, is sent to protocol conversion chip；
Step 2: the protocol conversion chip receives the source protocol packet and is parsed and encapsulate generation target protocol packet；
Step 3: the end RX, which receives the target protocol packet and parses, generates payload payload；
Step 4: the end TX and the end RX being configured by the macrodefinition submodule；
Step 5: packet counting being carried out by the packet counting submodule, and exports packet count results.
8. SRIO-ETH protocol conversion chip verification method according to claim 7, it is characterised in that: the step 1 is also
Quantity including calculating the source protocol packet by the TX_PKT_CNT module, the step 3 further include by the RX_
PKT_CNT module calculates the quantity of the target protocol packet.
9. SRIO-ETH protocol conversion chip verification method according to claim 7, it is characterised in that: step 4 packet
It includes: the TX_Port module and RX_Port module being configured by the SDI interface unit, and pass through the Macro_
Define unit configures counting check information to the TX_PKT_CNT module and RX_PKT_CNT module.
10. SRIO-ETH protocol conversion chip verification method according to claim 9, it is characterised in that: step 5 packet
It includes:
Step 51: the received maximum packet length RX_MAX_L in packet length TX_P_L, RX end, packet count results Pre_ are sent to the end TX
C_Cnt is initialized；
Step 52: the counting check information being extracted by GET_CNT unit, and starts to verify；
Step 53: packet counting is carried out by the PKT_CNT_CALCULATE unit: by the length TX_P_L of source protocol packet with connect
Receiving end maximum packet length RX_MAX_L is compared；
Step 54: as TX_P_L > RX_MAX_L, packet count results Pre_C_Cnt=(TX_P_L/RX_MAX_L)+X, X >=1,
As TX_P_L≤RX_MAX_L, packet count results Pre_C_Cnt=GEN_Cnt, wherein GEN_Cnt is the end TX packet meter
Number.
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