CN112152883B - Nuclear power plant field bus communication error rate testing device and testing method - Google Patents
Nuclear power plant field bus communication error rate testing device and testing method Download PDFInfo
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- CN112152883B CN112152883B CN202011063962.3A CN202011063962A CN112152883B CN 112152883 B CN112152883 B CN 112152883B CN 202011063962 A CN202011063962 A CN 202011063962A CN 112152883 B CN112152883 B CN 112152883B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
- H04L43/0823—Errors, e.g. transmission errors
- H04L43/0847—Transmission error
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector
- H04L1/203—Details of error rate determination, e.g. BER, FER or WER
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Abstract
The invention discloses a device and a method for testing the communication error rate of a field bus of a nuclear power plant, wherein the testing device comprises an error rate detection unit, a terminal resistance configuration unit and a communication parameter input/output unit; the bit error rate detection unit is realized on the basis of a programmable logic device and is used for generating a pseudo-random test signal and transmitting the pseudo-random test signal to a link of a field bus to be tested so as to test the bit error rate of the link of the field bus to be tested; the terminal resistance matching unit is used for realizing the electrical isolation between the error rate detection unit and the bus to be tested and adjusting the resistance value of the matched terminal of the field bus link to be tested according to the test parameters; the communication parameter input/output unit is used for realizing the input of the environmental parameters of the field bus to be tested and outputting the communication parameter result obtained by the test to the upper computer. The invention can comprehensively and systematically test the communication function and the transmission signal error rate of the field bus link.
Description
Technical Field
The invention belongs to the field of instrument control devices of safety level protection systems of nuclear power plants, and particularly relates to a device and a method for testing the communication error rate of a field bus of a nuclear power plant.
Background
In a digital instrument control system in the nuclear power field, the development and progress of a communication network technology and a control system enable a field bus control system to be well applied in the nuclear power field. At present, the field bus control system standards such as a Profibus bus, a Modbus, an Interbus bus and the like are mainly used in the industry. The transmission technology of the field bus physical layer usually adopts RS-485 standard transmission, a shielding twisted pair cable is used as a transmission cable, the transmission rate can be selected from 4.8kbit/s to 12Mbit/s, and the selected transmission communication baud rate is designed according to parameters such as actual communication distance, cable specification, terminal resistance setting and the like. When the field bus is transmitted in a long distance, parasitic parameters of a transmission cable cause impedance discontinuity of a bus link, and then a reflected noise signal is generated, so that a communication data link is influenced, and the communication error rate is increased. The method is characterized in that the bit error rate of a bus link is reduced by configuring a terminal resistor and reducing a communication baud rate, but configuration parameters of the terminal resistor and the communication baud rate are often set according to design early-stage simulation calculation, reliable communication parameter adjustment cannot be well carried out according to differences of field wiring in the construction process, the actual impedance of the bus link can be changed by access of node equipment of different manufacturers, and the adjusted link is not effectively tested for the bit error rate and the communication parameters of the bus link are optimized in the prior field application, so that the reliability is poor while the flexibility is poor.
Disclosure of Invention
Aiming at the error rate detection which is lacked in the specific construction process of the existing field bus, the channel signal quality test is carried out after the communication parameters of the bus link are set, and then the communication parameter design of the bus link is optimized. The invention provides a nuclear power plant field bus communication error rate testing device.
The invention is realized by the following technical scheme:
a nuclear power plant field bus communication error rate testing device comprises an error rate detection unit, a terminal resistance configuration unit and a communication parameter input/output unit;
the bit error rate detection unit is realized on the basis of a programmable logic device and is used for generating a pseudo-random test signal and transmitting the pseudo-random test signal to a link of a field bus to be tested so as to test the bit error rate of the link of the field bus to be tested;
the terminal resistance matching unit is used for realizing the electrical isolation between the error rate detection unit and the bus to be tested and adjusting the resistance value of the matched terminal of the field bus link to be tested according to the test parameters;
the communication parameter input/output unit is used for realizing the input of the environmental parameters of the field bus to be tested and outputting the communication parameter result obtained by the test to the upper computer.
The testing device realizes the test of the transmission error rate based on the programmable logic device, outputs the error rates corresponding to different communication baud rates under the transmission distance, simultaneously measures the optimal terminal matching resistance value and the communication baud rate under the given transmission distance, and is convenient for configuring the proper transmission parameters according to the actual requirements in engineering application.
Optionally, the apparatus of the present invention further comprises a power management unit;
and the power supply management unit is used for supplying power to the error rate detection unit, the terminal resistance configuration unit and the communication parameter input/output unit.
Optionally, the bit error rate detection unit of the present invention includes two pseudo random sequence generation algorithm modules, two RAMs, a calculation module and a logic control module;
the two pseudo-random sequence generation algorithm modules generate two paths of same pseudo-random sequence signals, one path of signal is injected onto a bus to be tested, the signal is returned through a field bus to be tested and analyzed through the logic control module, and when an appointed sequence is analyzed, all information after the sequence is stored into an RAM; the other path of signal is directly analyzed through a logic control module, and when an appointed sequence is analyzed, all information after the sequence is stored into another RAM;
the calculation module is used for comparing data in the two RAMs and calculating the data error rate of the field bus link to be tested, and outputting different baud rates, terminal resistance values and error rates obtained by testing to the communication parameter input/output unit through the communication parameter I/O interface;
the logic control module is used for analyzing signals according to input link parameters of the field bus to be tested and configuring the communication baud rate of the field bus to be tested and the resistance value of the access terminal.
Optionally, the terminal resistor configuration unit of the present invention includes an isolation transceiver and a digital potentiometer;
the isolation transceiver is used for realizing electrical isolation protection between the bit error rate detection unit and the field bus to be detected;
and the digital potentiometer and the error rate detection unit realize the adjustment of the resistance value of the link terminal of the field bus to be detected.
Optionally, the isolation transceiver of the present invention is an RS485 isolation transceiver.
Optionally, the communication parameter input/output unit of the present invention is configured to implement input of an environmental parameter of a fieldbus to be tested, where the environmental parameter of the fieldbus to be tested includes a node number, a cable type, a transmission distance, a parasitic parameter, or a communication baud rate.
Optionally, the programmable device of the present invention is not limited to FPGA.
On the other hand, the invention also provides a method for testing the communication error rate of the field bus of the nuclear power plant, which comprises the following steps:
respectively connecting the two nuclear power plant field bus communication error rate testing devices to the head end and the tail end of a bus link to be tested;
the testing devices at the head end and the tail end input environmental parameters of the bus to be tested through the communication parameter input/output unit respectively to complete the configuration of testing signals of the bus to be tested;
after configuration is successful, the testing devices at the head end and the tail end are respectively connected into the bus link, and the pseudo-random testing signals received by the tail end testing device from the bus interface are analyzed and transmitted back to the head end testing device;
the head end testing device analyzes the returned signal data, when an appointed sequence is analyzed, all information after the sequence is stored into one RAM, and the comparison module carries out bit comparison on two pseudo-random sequences which are stored in the two RAMs and take the appointed sequence as an initial bit, so that the corresponding error rate under the conditions of the given terminal resistance and the communication baud rate is obtained.
The testing device is directly connected to a field bus link, parameters such as terminal resistance, communication rate and the like are flexibly configured, bus quality is evaluated by detecting the bit error rate of the link, and the optimal bus terminal resistance configuration parameter and the maximum communication baud rate under remote communication are given.
Optionally, the method of the present invention further comprises:
transmitting the test parameters to an upper computer through a communication parameter input/output unit of the head end test device;
the working personnel configures the parameters of the field bus to be tested according to the test parameters and sends the parameters to the communication parameter input/output unit of the head end test device through the upper computer;
and the bit error rate detection unit in the head end test device controls the terminal resistor configuration unit to output the corresponding resistance value parameter to the field bus link to be tested according to the configuration parameter received by the communication parameter input/output unit.
Optionally, a plurality of node devices on the field bus link to be tested of the present invention are connected to the bus by adopting a daisy chain topology structure.
The invention has the following advantages and beneficial effects:
1. the testing device of the invention designs a pseudo-random sequence generation algorithm module based on a programmable logic device (FPGA), performs error rate testing of communication link channel signal quality, feeds back to a terminal resistor configuration circuit for resistance parameter setting optimization according to a test result, and can perform data frame format coding and decoding summary testing according to actual field bus communication protocols such as Modbus, Profibus and the like, thereby comprehensively testing the communication function and transmission signal error rate of a bus link.
2. The FPGA can achieve higher data processing capacity through parallel processing and pipeline design, so that the bit error rate of the test bus can be detected quickly, and the test time is shortened.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:
FIG. 1 is a schematic block diagram of a testing apparatus of the present invention.
Fig. 2 is a schematic block diagram of the bit error rate detection unit of the present invention.
Fig. 3 is a schematic block diagram of a termination resistance configuration unit according to the present invention.
FIG. 4 is a schematic diagram of the application principle of the testing device of the present invention.
Detailed Description
Hereinafter, the term "comprising" or "may include" used in various embodiments of the present invention indicates the presence of the invented function, operation or element, and does not limit the addition of one or more functions, operations or elements. Furthermore, as used in various embodiments of the present invention, the terms "comprises," "comprising," "includes," "including," "has," "having" and their derivatives are intended to mean that the specified features, numbers, steps, operations, elements, components, or combinations of the foregoing, are only meant to indicate that a particular feature, number, step, operation, element, component, or combination of the foregoing, and should not be construed as first excluding the existence of, or adding to the possibility of, one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing.
In various embodiments of the invention, the expression "or" at least one of a or/and B "includes any or all combinations of the words listed simultaneously. For example, the expression "a or B" or "at least one of a or/and B" may include a, may include B, or may include both a and B.
Expressions (such as "first", "second", and the like) used in various embodiments of the present invention may modify various constituent elements in various embodiments, but may not limit the respective constituent elements. For example, the above description does not limit the order and/or importance of the elements described. The foregoing description is for the purpose of distinguishing one element from another. For example, the first user device and the second user device indicate different user devices, although both are user devices. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of various embodiments of the present invention.
It should be noted that: if it is described that one constituent element is "connected" to another constituent element, the first constituent element may be directly connected to the second constituent element, and a third constituent element may be "connected" between the first constituent element and the second constituent element. In contrast, when one constituent element is "directly connected" to another constituent element, it is understood that there is no third constituent element between the first constituent element and the second constituent element.
The terminology used in the various embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the various embodiments of the invention. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the present invention belong. The terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning that is consistent with their contextual meaning in the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein in various embodiments of the present invention.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples and accompanying drawings, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not meant to limit the present invention.
Example 1
The embodiment provides a communication error rate testing device for a field bus of a nuclear power plant. The testing device of the embodiment is based on a programmable logic device (FPGA) to realize the test of the transmission bit error rate, output the bit error rates corresponding to different communication baud rates under the transmission distance, and simultaneously measure the optimal terminal matching resistance value and the communication baud rate under the given transmission distance, thereby being convenient for configuring the proper transmission parameters according to the actual requirements in the engineering application.
As shown in fig. 1, the testing apparatus of the present embodiment includes an error rate detecting unit, a terminal resistance configuration unit, a communication parameter input/output unit, and a power management unit.
The functional units of the test device are described as follows:
1. an error rate detection unit:
the bit error rate detection unit of the embodiment is realized based on an FPGA and comprises two pseudo-random sequence generation algorithm modules, two RAMs, a calculation module and a logic control module.
The two pseudo-random sequence generation algorithm modules of the embodiment generate two paths of same pseudo-random sequence signals, one path of signal is injected onto a field bus to be tested, the signal is returned through the field bus to be tested (the signal is transmitted back to a head end testing device through a testing device at the tail end of the bus) and is analyzed through a logic control module, and when an appointed sequence is analyzed, all information after the sequence is stored into an RAM (RAM 1); the other signal is directly analyzed by the logic control module, and when the appointed sequence is analyzed, all information after the sequence is stored in another RAM (RAM 2).
The calculation module (including the bit comparison module and the BER count module shown in fig. 2) of this embodiment is configured to compare data in the two RAMs, calculate a data error rate of the fieldbus link to be tested, and output different baud rates, terminal resistance values, and error rates obtained by the test to the communication parameter input/output unit through the communication parameter I/O interface.
The logic control module of this embodiment is configured to perform signal analysis according to an input link parameter of the fieldbus to be tested, and configure a communication baud rate of the fieldbus to be tested and an access terminal resistance value.
In order to facilitate the comparison of two paths of data, a specified sequence is added to trigger the recording of a pseudo-random sequence into a corresponding RAM. The internal logic design of the bit error rate detection unit is shown in fig. 2.
2. Terminal resistor configuration unit
The terminal resistor configuration unit mainly comprises an RS485 isolation transceiver and a digital potentiometer. The RS485 isolation transceiver realizes the electrical isolation protection of the bus and the control circuit, blocks the high voltage of the external field bus outside a circuit system of the testing device, and can effectively protect the system safety and the safety of operators.
Because the terminal resistance value is set depending on factors such as data transmission rate, cable length, signal conversion rate and the like, the impedance continuity of the transmission cable is met by reasonably adjusting the value of the matched terminal resistance of the access bus link according to the measured error rate. The adjustment process of the resistance value of the terminal resistor is realized by the bit error rate detection unit and the digital potentiometer. A block circuit diagram of the termination resistance configuration unit is shown in fig. 3.
3. Communication parameter input/output unit
The communication parameter input/output unit is mainly used for completing the input of environment parameters of the test bus, such as information of node number, cable type, transmission distance, parasitic parameters and the like, and outputting the test communication parameter result to the upper computer. The interface circuit is an RS232 interface. The unit can also set a test communication data format according to different bus communication protocols, and after receiving the set protocol, the FPGA tests the bus link communication function according to a specified protocol, thereby meeting the data link test under different protocols and better matching the actual operating environment.
4. Power management unit
The power management unit provides power supply and starting time sequence management for the test device and has a hot plug function.
The testing device of the embodiment is connected to the head and the tail of the bus link to inject detection data into the bus, test the bit error rates corresponding to different communication baud rates, and test the communication parameters such as the matching resistance, the baud rate and the like of the corresponding bus link terminal under the optimal bit error rate.
Example 2
The testing device provided in embodiment 1 realizes testing a field bus to be tested, and the specific process is as follows:
the access mode of the test device for field practical application is shown in fig. 4, and two test devices are configured to be respectively accessed to the head end and the tail end of the bus link. A plurality of node devices on a bus link are connected to a bus by adopting a daisy chain topology structure, and the topology structure requires that the length of a branch line of the node connected to the bus is as small as possible and is generally controlled within 40cm, so that the interference of the overlong branch line to a signal is prevented. The design adopts a special field bus D-SUB connector to directly branch two paths at the connector to access the bus, thereby eliminating the influence factor of overlong branch lines and improving the communication reliability.
The head end and tail end testing device receives actual field bus parameters such as bus cable transmission impedance, bus cable length, communication baud rate, node number and the like through a communication parameter input/output unit interface, and then completes configuration of the injected bus test signal, wherein the configuration information comprises a terminal resistance value, a communication baud rate and the like. And after the configuration is successful, the head and tail end test devices are respectively accessed into the bus link. The tail end testing device analyzes the pseudo random testing signal received by the bus interface and transmits the pseudo random testing signal back to the head end testing device. The head end test device analyzes the data transmitted back, and when the specified sequence is analyzed, all information after the sequence is stored in the RAM1 inside the FPGA. The comparison module carries out bit comparison on two pseudo-random sequences which take the appointed sequences as initial bits and are stored in the RAM1 and the RAM2, and carries out 100 cycles of each baud rate test cycle on several common baud rates (such as 9600bps, 115200bps and the like) of a communication rate segment of 4.8 kbit/s-12 Mbit/s, so as to obtain the corresponding bit error rate BER under the conditions of given terminal resistance and communication baud rate. And finally, outputting test information through a communication parameter input/output unit interface of the head end test device, configuring parameters such as terminal matching resistance, communication baud rate and the like of the field bus by a worker according to the test parameters, sending the configuration parameters to the parameter input/output unit interface through an upper computer, and controlling the terminal resistance configuration unit to output corresponding resistance parameters to be accessed into a bus link. The testing device can effectively improve the communication quality and the communication reliability of the bus signals.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (9)
1. A nuclear power plant field bus communication error rate testing device is characterized by comprising an error rate detection unit, a terminal resistance configuration unit and a communication parameter input/output unit;
the bit error rate detection unit is realized on the basis of a programmable logic device and is used for generating a pseudo-random test signal and transmitting the pseudo-random test signal to a link of a field bus to be tested so as to test the bit error rate of the link of the field bus to be tested;
the terminal resistance configuration unit is used for realizing the electrical isolation between the error rate detection unit and the field bus to be tested and adjusting the link matching terminal resistance value of the field bus to be tested according to the test parameters;
the terminal resistance configuration unit comprises an isolation transceiver and a digital potentiometer;
the isolation transceiver is used for realizing electrical isolation protection between the error rate detection unit and the field bus to be detected;
the digital potentiometer and the error rate detection unit realize the adjustment of the resistance value of the link terminal of the field bus to be detected;
the communication parameter input/output unit is used for realizing the input of the environmental parameters of the field bus to be tested and outputting the communication parameter result obtained by the test to the upper computer.
2. The nuclear power plant fieldbus communication bit error rate testing device of claim 1, further comprising a power management unit;
and the power supply management unit is used for supplying power to the error rate detection unit, the terminal resistance configuration unit and the communication parameter input/output unit.
3. The nuclear power plant fieldbus communication bit error rate testing device of claim 1, characterized in that the bit error rate detecting unit comprises two pseudo-random sequence generation algorithm modules, two RAMs, a calculation module and a logic control module;
the two pseudo-random sequence generation algorithm modules generate two paths of same pseudo-random sequence signals, one path of signal is injected onto a field bus to be tested, the signal is returned through the field bus to be tested and analyzed through the logic control module, and when an appointed sequence is analyzed, all information after the sequence is stored into an RAM; the other path of signal is directly analyzed through a logic control module, and when an appointed sequence is analyzed, all information after the sequence is stored into another RAM;
the calculation module is used for comparing data in the two RAMs and calculating the data error rate of the field bus link to be tested, and outputting different baud rates, terminal resistance values and error rates obtained by testing to the communication parameter input/output unit through the communication parameter I/O interface;
the logic control module is used for analyzing signals according to input link parameters of the field bus to be tested and configuring the communication baud rate of the field bus to be tested and the resistance value of the access terminal.
4. The nuclear power plant fieldbus communication error rate testing device of claim 1, wherein the isolation transceiver is an RS485 isolation transceiver.
5. The nuclear power plant fieldbus communication error rate testing device of claim 1, wherein the communication parameter input/output unit is configured to enable input of fieldbus environment parameters to be tested, and the fieldbus environment parameters to be tested include the number of nodes, cable types, transmission distances, parasitic parameters, or communication baud rates.
6. The nuclear power plant fieldbus communication bit error rate testing device of claim 1, wherein the programmable logic device is an FPGA.
7. A nuclear power plant field bus communication error rate test method is characterized by comprising the following steps:
respectively connecting two nuclear power plant field bus communication error rate testing devices according to any one of claims 1-6 to the head end and the tail end of a field bus link to be tested;
the testing devices at the head end and the tail end respectively input the environmental parameters of the field bus to be tested through the communication parameter input/output unit to complete the configuration of the testing signals of the field bus to be tested;
after configuration is successful, the testing devices at the head end and the tail end are respectively connected into the bus link, and the pseudo-random testing signals received by the tail end testing device from the bus interface are analyzed and transmitted back to the head end testing device;
the head end testing device analyzes the returned signal data, when an appointed sequence is analyzed, all information after the sequence is stored into one RAM, and the comparison module carries out bit comparison on two pseudo-random sequences which are stored in the two RAMs and take the appointed sequence as an initial bit, so that the corresponding error rate under the conditions of the given terminal resistance and the communication baud rate is obtained.
8. The nuclear power plant fieldbus communication bit error rate testing method of claim 7, further comprising:
transmitting the test parameters to an upper computer through a communication parameter input/output unit of the head end test device;
the working personnel configures the parameters of the field bus to be tested according to the test parameters and sends the parameters to the communication parameter input/output unit of the head end test device through the upper computer;
and the bit error rate detection unit in the head end test device controls the terminal resistor configuration unit to output the corresponding resistance value parameter to the field bus link to be tested according to the configuration parameter received by the communication parameter input/output unit.
9. The method for testing the communication error rate of the fieldbus of the nuclear power plant according to claim 7, wherein the plurality of node devices on the fieldbus link to be tested are connected to the bus by adopting a daisy chain topology structure.
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