CN203014839U - 10 G error detector based on high-speed transceiver chip - Google Patents
10 G error detector based on high-speed transceiver chip Download PDFInfo
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- CN203014839U CN203014839U CN 201220655612 CN201220655612U CN203014839U CN 203014839 U CN203014839 U CN 203014839U CN 201220655612 CN201220655612 CN 201220655612 CN 201220655612 U CN201220655612 U CN 201220655612U CN 203014839 U CN203014839 U CN 203014839U
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Abstract
The utility model discloses a 10 G bit error tester based on a high-speed transceiver chip. The 10 G bit error tester is connected with a tested device. The 10 G bit error tester includes a clock source, the high-speed transceiver chip, a control module, a USB/I2C protocol conversion module and an upper computer. A bit pattern generating end of the high-speed transceiver chip is connected with a receiving end of the tested device; a bit error detecting end of the high-speed transceiver chip is connected with a transmitting end of the tested device; a clock end of the high-speed transceiver chip is connected with the clock source; a control end of the high-speed transceiver chip is connected with an I/O interface of the control module; and an output end of the control module is connected with a USB port of the upper computer through the USB/I2C protocol conversion module. The test rate of the 10G bit error tester based on the high-speed transceiver chip of the utility model can reach up to 10 Gbps. With the 10 G bit error tester adopted, signal processing speed and test performance of the bit error tester can be improved; the miniaturization and integration of the bit error tester can be realized; and cost and power consumption can be lowered; and the 10 G bit error tester is suitable for high-speed communication systems.
Description
Technical field
The utility model relates to the technical field of digital communication system, relates in particular to a kind of 10G code error tester based on the high speed transceiving chip.
Background technology
Code error tester is tester most important, the most basic in digital communication, be mainly used in the transmission quality of testing digital communication signal, its main test parameter comprises error code, alarm etc., development, production, maintenance and metrology and measurement that it is widely used in digital communication equipment, also can be applicable to digital communications network construction, open and check and accept and maintenance test.
Domestic existing code error tester flank speed is 10Gbps, mostly adopts the FPGA mode to realize error code testing.Because FPGA is generally larger, power consumption is also relatively high, and is also relatively high to power supply requirement.Therefore, very difficult based on the code error tester miniaturization of FPGA.
The utility model content
Main purpose of the present utility model is to propose a kind of 10G code error tester based on the high speed transceiving chip, is intended to improve conversion speed and the test performance of code error tester, and realizes the miniaturization of code error tester and integrated, reduces costs and power consumption.
in order to achieve the above object, the utility model proposes a kind of 10G code error tester based on the high speed transceiving chip, should be connected with equipment under test based on the 10G code error tester of high speed transceiving chip, comprise for generation of pseudo-random code sequence and also can detect the high speed transceiving chip of error code, be used for providing the clock source of reference clock, the control module that is used for controlling each functional module normal operation and sends corresponding information according to the state of each functional module, for the USB/I2C protocol conversion module of controlling the described high speed transceiving chip test error rate and the host computer that shows test results and being used for connecting described control module and described host computer, wherein:
The pattern of described high speed transceiving chip produces end and is connected with the receiving terminal of described equipment under test, the Error detection end of described high speed transceiving chip is connected with the transmitting terminal of described equipment under test, the clock end of described high speed transceiving chip is connected with described clock source, the control end of described high speed transceiving chip is connected with the I/O mouth of described control module, the output of described control module is connected with the input of described USB/I2C protocol conversion module, and the output of described USB/I2C protocol conversion module is connected with the USB mouth of host computer.
Preferably, described clock source is the SI514 crystal oscillator.
Preferably, described high speed transceiving chip is the PHY1066 chip.
Preferably, described high speed transceiving chip comprises pattern generation module and error code detection module; Wherein:
The transmitting terminal of described pattern generation module produces end as the pattern of described high speed transceiving chip, is connected with the receiving terminal of described equipment under test; The receiving terminal of described error code detection module is connected with the transmitting terminal of described equipment under test as the pattern test side of described high speed transceiving chip.
Preferably, described control module is the ADuC7020 single-chip microcomputer.
Preferably, described USB/I2C protocol conversion module is the CP2112 module.
Preferably, described host computer is PC.
The 10G code error tester based on the high speed transceiving chip that the utility model proposes, by adopting the pattern generation module in the PHY1066 chip to produce pseudo-random code sequence, error code detection module is carried out Bit Error Code Statistics, and the calculating error rate, normal operation by each module of ADuC7020 Single-chip Controlling, state according to each module, send the information such as error code event, state alarm, fault prompting, the ADuC7020 single-chip microcomputer is processed by the interface conversion of CP2112 module, carry out exchanges data with PC, PC shows test results, and realizes error code testing.The utility model reaches 10Gbps based on the test rate of the 10G code error tester of high speed transceiving chip, can test the high speed optoelectronic signal.Simultaneously, compare with existing code error tester, the 10G code error tester based on the high speed transceiving chip that the utility model proposes has improved conversion speed and the test performance of code error tester, reduced the fault that occurs in the test process or tested the problems such as inaccurate, realize the miniaturization of code error tester and integrated, reduce costs and power consumption.
Description of drawings
Fig. 1 is that the utility model is based on the modular structure schematic diagram of the 10G code error tester preferred embodiment of high speed transceiving chip;
Fig. 2 is that the utility model is based on the formant modular structure schematic diagram of the 10G code error tester preferred embodiment of high speed transceiving chip.
The realization of the utility model purpose, functional characteristics and advantage are described further with reference to accompanying drawing in connection with embodiment.
Embodiment
Further illustrate the technical solution of the utility model below in conjunction with Figure of description and specific embodiment.Should be appreciated that specific embodiment described herein only in order to explaining the utility model, and be not used in restriction the utility model.
With reference to Fig. 1, Fig. 1 is that the utility model is based on the modular structure schematic diagram of the 10G code error tester preferred embodiment of high speed transceiving chip.
In the utility model embodiment, based on the 10G code error tester of high speed transceiving chip, be connected with equipment under test 10, comprise high speed transceiving chip 20, clock source 30, control module 40, USB/I2C protocol conversion module 50 and host computer 60.
In the present embodiment, high speed transceiving chip 20 is for generation of pseudo-random code sequence and can detect error code, clock source 30 is used for providing reference clock, reference clock as high speed transceiving chip 20, control module 40 is used for controlling each functional module normal operation and sends corresponding information according to the state of each functional module, host computer 60 is used for controlling the high speed transceiving chip 20 test error rates and shows test results, and USB/I2C protocol conversion module 50 is used for link control module 40 and host computer 60.
wherein, the pattern of high speed transceiving chip 20 produces end and is connected with the receiving terminal of equipment under test 10, the Error detection end of high speed transceiving chip 20 is connected with the transmitting terminal of equipment under test 10, between high speed transceiving chip 20 and equipment under test 10, connect by coaxial cable, the clock end of high speed transceiving chip 20 is connected with clock source 30, the control end of high speed transceiving chip 20 is connected with the I/O mouth of control module 40, the output of control module 40 is connected with the input of USB/I2C protocol conversion module 50, the output of USB/I2C protocol conversion module 50 is connected with the USB mouth of host computer 60.
In the present embodiment, when powering on, 40 pairs of high speed transceiving chips 20 of control module and clock source 30 carry out initialization, control each functional module, it is the normal operation of high speed transceiving chip 20, clock source 30, USB/I2C protocol conversion module 50 and host computer 60, clock source 30 vibrations produce a reference clock, and export this reference clock to high speed transceiving chip 20, this high speed transceiving chip 20 reference clock that 30 vibrations provide according to clock source, obtain single local clock, local clock is with after reference clock is synchronizeed, and high speed transceiving chip 20 produces pseudo-random code sequences; And, high speed transceiving chip 20 receives the signal of telecommunication of equipment under test 10 inputs, control module 40 is controlled 20 pairs of signals of telecommunication of high speed transceiving chip and is carried out error code testing, this signal of telecommunication and local clock are compared by bit, high speed transceiving chip 20 is according to comparative result, add up current error code number, and calculate the current error rate according to the testing time.
The formula of the present embodiment calculating error rate is as follows:
Pe=Ne/N
In formula, Pe is the error rate; The figure place of Ne for wherein makeing mistakes; N is the data sum of transmission.
the present embodiment produces continuous pseudo-random code sequence by high speed transceiving chip 20, statistics error code number and the calculating error rate, control the normal operation of each module by control module 40, state according to each module, send the error code event, the state alarm, the information such as fault prompting, host computer 60 carries out exchanges data by USB/I2C protocol conversion module 50 and control module 40, and the error code testing result is shown, realize that test rate is up to the code error tester of 10Gbps, conversion speed and the test performance of code error tester have been improved, realize the miniaturization of code error tester and integrated.
In conjunction with Fig. 1 and Fig. 2, Fig. 1 is that the utility model is based on the modular structure schematic diagram of the 10G code error tester preferred embodiment of high speed transceiving chip; Fig. 2 is that the utility model is based on the formant modular structure schematic diagram of the 10G code error tester preferred embodiment of high speed transceiving chip.
In above-described embodiment, clock source 30 is preferably selected SI514 crystal oscillator 31.
The operating frequency of SI514 crystal oscillator 31 is 155.52MHz, and frequency deviation is less than 50PPM.Utilize SI514 crystal oscillator 31 to produce stable reference clock, as the reference clock of high speed transceiving chip 20.
In addition, abovely only describe with a specific embodiment, also can select to have equal performance, can provide other equivalent crystal oscillators of reference clock as clock source 30.
In above-described embodiment, high speed transceiving chip 20 is preferably selected PHY1066 chip 21.
Particularly, high speed transceiving chip 21 comprises pattern generation module 211 and error code detection module 212.
Wherein, the transmitting terminal of pattern generation module 211 produces end as the pattern of high speed transceiving chip 20, is connected with the receiving terminal of equipment under test 10; The receiving terminal of error code detection module 212 is connected with the transmitting terminal of described equipment under test 10 as the pattern test side of high speed transceiving chip 20.
PHY1066 chip 21 is supported multiple speed, inner integrated BERT(Bit Error Rate Tester, the bit error rate tester) and PRBS(Pseudo Random Binary Sequence, pseudo-random binary sequence) functional module, wherein, the PRBS functional module is the pattern generation module 211 of PHY1066 chip 21, is connected with the receiving terminal of equipment under test 10, the BERT functional module is the error code detection module 212 of PHY1066 chip 21, is connected with the transmitting terminal of equipment under test 10; Pattern generation, bit error analyzing and BERT power of test that PHY1066 chip 21 is supported up to 10Gbps, the test pattern comprises PRBS:2
31-1, PRBS:2
23-1, PRBS:2
15-1, PRB:S
27-1, the speed of test error code is up to 11Gbps.
in the present embodiment, between PHY1066 chip 21 and equipment under test 10, connect by coaxial cable, and carry out the transmission of high-speed serial data, the reference clock that the pattern generation module 211 of PHY1066 chip 21 produces with SI514 crystal oscillator 31 as a reference, obtain single local clock, this local clock is synchronizeed with the reference clock that SI514 crystal oscillator 31 provides and is reached contrast, produce continuous pseudo-random code sequence, this pseudo-random code sequence is sent to the receiving terminal of equipment under test 10 from the transmitting terminal of pattern generation module 211, equipment under test 10 sends the signal of telecommunication after treatment, the error code detection module 212 of PHY1066 chip 21 receives the signal of telecommunication that equipment under test 10 sends, and the signal of telecommunication is detected, statistics error code number, and calculate the error rate.Compare with existing transceiving chip, the error code rate that the PHY1066 chip 21 that the present embodiment adopts can be tested is faster, and cost and low in energy consumption.
What deserves to be explained is, below only describe with a specific embodiment, also can select to have identical function, can produce the random pattern sequence of Continuous Pseudo, statistics error code and calculate the error rate, support other equivalent high speed transceiving chips of 10Gbps pattern test as high speed transceiving chip 20.
Particularly, control module 40 is preferably selected ADuC7020 single-chip microcomputer 41.
The ADuC7020 single-chip microcomputer has two-forty, low-power consumption, good confidentiality, the advantage such as with low cost, can support the code error tester of 10Gbps transmission rate, has reduced widely the fault that occurs in the test process or has tested the problems such as inaccurate.Compare with the single-chip microcomputer of the existing error rate be used to recording error code number that PHY1066 chip 21 adds up and calculating, this ADuC7020 single-chip microcomputer 41 can be supported higher transmission rate.
The ADuC7020 single-chip microcomputer is that utility model is based on the control core of the 10G code error tester of high speed transceiving chip, when powering on, each functional module is configured, control the normal operation of each functional module, and according to the state that each functional module provides, send the information such as error code event, state alarm, fault prompting to host computer 60.
In addition, abovely only describe with a specific embodiment, also can select to have identical function, can control each functional module normal operation, send other equivalent single-chip microcomputers of corresponding information of each functional module state as control module 40.
Particularly, USB/I2C protocol conversion module 50 is preferably selected CP2112 module 51.
In addition, abovely only describe with a specific embodiment, also can select to have identical function, can realize that control module 40 and host computer 60 carry out other equivalent modular converters of exchanges data as USB/I2C protocol conversion module 50.
Particularly, host computer 60 is preferably selected PC 61.
The present embodiment is by programming on PC 61, each register in PHY1066 chip 21 is arranged, and control command is sent to ADuC7020 single-chip microcomputer 41 by CP2112 module 51, ADuC7020 single-chip microcomputer 41 sends to control command PHY1066 chip 21 again, complete the setting to each register, realize the control of 41 pairs of PHY1066 chips 21 of ADuC7020 single-chip microcomputer; Simultaneously, the test result that PC 61 records ADuC7020 single-chip microcomputer 41 is implemented Graphics Processing, in order to analyze and judge the accuracy of code error tester test.The present embodiment is preferably used for showing that the program of error code testing result adopts C# language to write on PC 61, C# language is simple and be easy to debugging, in addition, facilitates needs also can adopt other computer languages to write according to debugging.
the 10G code error tester based on the high speed transceiving chip that the utility model proposes, by adopting the pattern generation module 211 in PHY1066 chip 21 to produce pseudo-random code sequence, error code detection module 212 is carried out Bit Error Code Statistics, and the calculating error rate, control the normal operation of each module by ADuC7020 single-chip microcomputer 41, the state that provides according to each module, send the error code event, the state alarm, the information such as fault prompting, ADuC7020 single-chip microcomputer 41 is processed by the interface conversion of CP2112 module 51, carry out exchanges data with PC 61, PC 61 shows test results, realize error code testing.The utility model reaches 10Gbps based on the test rate of the 10G code error tester of high speed transceiving chip, can test the high speed optoelectronic signal.Simultaneously, compare with existing code error tester, the 10G code error tester based on the high speed transceiving chip that the utility model proposes has improved conversion speed and the test performance of code error tester, reduced the fault that occurs in the test process or tested the problems such as inaccurate, realize the miniaturization of code error tester and integrated, reduce costs and power consumption.
The above is only preferred embodiment of the present utility model; not thereby limit the scope of the claims of the present utility model; every equivalent structure or equivalent flow process conversion that utilizes the utility model specification and accompanying drawing content to do; or directly or indirectly be used in other relevant technical fields, all in like manner be included in scope of patent protection of the present utility model.
Claims (7)
1. 10G code error tester based on the high speed transceiving chip, be connected with equipment under test, it is characterized in that, comprise for generation of pseudo-random code sequence and can detect error code the high speed transceiving chip, be used for providing reference clock clock source, be used for controlling each functional module normal operation and send the control module of corresponding information, the USB/I2C protocol conversion module that is used for controlling the described high speed transceiving chip test error rate and the host computer that shows test results and is used for connecting described control module and described host computer according to the state of each functional module; Wherein:
The pattern of described high speed transceiving chip produces end and is connected with the receiving terminal of described equipment under test, the Error detection end of described high speed transceiving chip is connected with the transmitting terminal of described equipment under test, the clock end of described high speed transceiving chip is connected with described clock source, the control end of described high speed transceiving chip is connected with the I/O mouth of described control module, the output of described control module is connected with the input of described USB/I2C protocol conversion module, and the output of described USB/I2C protocol conversion module is connected with the USB mouth of host computer.
2. 10G code error tester as claimed in claim 1, is characterized in that, described clock source is the SI514 crystal oscillator.
3. 10G code error tester as claimed in claim 1, is characterized in that, described high speed transceiving chip is the PHY1066 chip.
4. 10G code error tester as claimed in claim 3, is characterized in that, described high speed transceiving chip comprises pattern generation module and error code detection module; Wherein:
The transmitting terminal of described pattern generation module produces end as the pattern of described high speed transceiving chip, is connected with the receiving terminal of described equipment under test; The receiving terminal of described error code detection module is connected with the transmitting terminal of described equipment under test as the pattern test side of described high speed transceiving chip.
5. 10G code error tester as claimed in claim 1, is characterized in that, described control module is the ADuC7020 single-chip microcomputer.
6. 10G code error tester as claimed in claim 1, is characterized in that, described USB/I2C protocol conversion module is the CP2112 module.
7. 10G code error tester as claimed in claim 1, is characterized in that, described host computer is PC.
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| CN 201220655612 CN203014839U (en) | 2012-12-03 | 2012-12-03 | 10 G error detector based on high-speed transceiver chip |
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| CN 201220655612 CN203014839U (en) | 2012-12-03 | 2012-12-03 | 10 G error detector based on high-speed transceiver chip |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104796938A (en) * | 2015-04-24 | 2015-07-22 | 深圳市国电科技通信有限公司 | Micropower wireless communication error rate detection analyzer |
| CN106027172A (en) * | 2016-04-22 | 2016-10-12 | 北京联盛德微电子有限责任公司 | Method and device for testing receiver chip |
| CN107493202A (en) * | 2017-09-29 | 2017-12-19 | 珠海思开达技术有限公司 | Expansible high speed code error tester |
| CN109039450A (en) * | 2018-08-24 | 2018-12-18 | 武汉恒泰通技术有限公司 | A kind of multi tate device for detecting code error and its detection method |
| CN109167640A (en) * | 2018-09-26 | 2019-01-08 | 东莞铭普光磁股份有限公司 | A kind of Error Detector |
| CN111010241A (en) * | 2019-12-03 | 2020-04-14 | 杭州电子科技大学富阳电子信息研究院有限公司 | Multi-protocol high-speed pseudo-random signal loop test system based on FPGA |
| CN111241021A (en) * | 2020-01-07 | 2020-06-05 | 吴丁伢 | Multi-channel split error code instrument |
| CN114295963A (en) * | 2021-12-31 | 2022-04-08 | 龙迅半导体（合肥）股份有限公司 | Chip testing method and system |
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2012
- 2012-12-03 CN CN 201220655612 patent/CN203014839U/en not_active Expired - Fee Related
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104796938A (en) * | 2015-04-24 | 2015-07-22 | 深圳市国电科技通信有限公司 | Micropower wireless communication error rate detection analyzer |
| CN106027172A (en) * | 2016-04-22 | 2016-10-12 | 北京联盛德微电子有限责任公司 | Method and device for testing receiver chip |
| CN106027172B (en) * | 2016-04-22 | 2021-05-04 | 北京联盛德微电子有限责任公司 | Method and device for testing receiver chip |
| CN107493202A (en) * | 2017-09-29 | 2017-12-19 | 珠海思开达技术有限公司 | Expansible high speed code error tester |
| CN107493202B (en) * | 2017-09-29 | 2024-03-22 | 珠海思开达技术有限公司 | Extensible high-speed error code tester |
| CN109039450A (en) * | 2018-08-24 | 2018-12-18 | 武汉恒泰通技术有限公司 | A kind of multi tate device for detecting code error and its detection method |
| CN109167640A (en) * | 2018-09-26 | 2019-01-08 | 东莞铭普光磁股份有限公司 | A kind of Error Detector |
| CN109167640B (en) * | 2018-09-26 | 2021-04-20 | 东莞铭普光磁股份有限公司 | Error code instrument |
| CN111010241A (en) * | 2019-12-03 | 2020-04-14 | 杭州电子科技大学富阳电子信息研究院有限公司 | Multi-protocol high-speed pseudo-random signal loop test system based on FPGA |
| CN111010241B (en) * | 2019-12-03 | 2021-12-14 | 杭州电子科技大学富阳电子信息研究院有限公司 | Multi-protocol high-speed pseudo-random signal loop test system based on FPGA |
| CN111241021A (en) * | 2020-01-07 | 2020-06-05 | 吴丁伢 | Multi-channel split error code instrument |
| CN114295963A (en) * | 2021-12-31 | 2022-04-08 | 龙迅半导体（合肥）股份有限公司 | Chip testing method and system |
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Granted publication date: 20130619 Termination date: 20211203 |