CN106027172B

CN106027172B - Method and device for testing receiver chip

Info

Publication number: CN106027172B
Application number: CN201610251279.XA
Authority: CN
Inventors: 梅张雄; 程晟
Original assignee: Beijing Winner Microeletronics Co ltd
Current assignee: Beijing Winner Microeletronics Co ltd
Priority date: 2016-04-22
Filing date: 2016-04-22
Publication date: 2021-05-04
Anticipated expiration: 2036-04-22
Also published as: CN106027172A

Abstract

The invention relates to a method and a device for testing a receiver chip, which comprises the following steps: the standard chip transmits a signal under the test rate to the chip to be tested according to the first test item; and the standard chip receives the BER fed back by the chip to be tested, and when the BER is higher than a preset threshold value, the standard chip judges that the first test item passes the test. According to the method and the device for testing the receiver chip, the chip is used for transmitting and receiving the signal of the chip to be tested and analyzing the signal, so that an instrument in the traditional calibration and test mode is replaced, and the automation of calibration and test is realized through firmware.

Description

Method and device for testing receiver chip

Technical Field

The invention relates to the field of WIFI chips of the Internet of things, in particular to a method and a device for testing a receiver chip.

Background

Due to the difference of devices in the chip manufacturing process and the influence of temperature and external environment on the operation of devices in the chip, even the radio frequency chips produced in the same batch have certain difference in performance. In order to ensure the consistency of products, the analog circuit of the WIFI radio frequency chip is subjected to direct current bias and in-phase I/orthogonal Q two-path phase and amplitude calibration before the products are delivered, so that the influence of process deviation in the manufacturing process on the operation of the analog circuit is corrected, and performance test is carried out to ensure that the delivered products meet the performance requirements.

The performance of the rf chip is generally measured by using a specific instrument to transmit and receive rf signals of a specific format when the rf chip is calibrated and tested. This method requires additional instrumentation, which increases the cost of the test. Meanwhile, one instrument can only correspond to one radio frequency chip, if a plurality of instruments are not purchased, simultaneous testing of a plurality of instruments cannot be achieved, and the efficiency of calibration and testing is difficult to improve.

Disclosure of Invention

Technical problem

In view of the above, the technical problem to be solved by the present invention is how to provide a method and an apparatus for testing a receiver chip, so that the receiver chip can perform a self-test.

Solution scheme

To solve the above technical problem, the present invention provides, in a first aspect, a method for testing a receiver chip, including:

the standard chip transmits a signal under the test rate to the chip to be tested according to the first test item;

and the standard chip receives the BER fed back by the chip to be tested, and when the BER is higher than a preset threshold value, the standard chip judges that the first test item passes the test.

In one possible implementation manner, after the first test item passes the test, the method further includes: the standard chip transmits a signal at a test rate to the chip to be tested according to a second test item; and

and the standard chip receives the BER fed back by the chip to be tested, and when the BER is higher than a preset threshold value, the standard chip judges that the second test item passes the test.

In a possible implementation manner, after the transmitting a signal at a test rate to the chip to be tested according to the test firmware, the method further includes: and the chip to be tested receives and stores the signal under the test rate, and demodulates the signal under the test rate.

In a possible implementation manner, before the transmitting a signal at a test rate to a chip to be tested according to test firmware, the method further includes:

and the standard chip receives an instruction of a testing machine to enter a testing state according to the instruction.

In a possible implementation manner, when the BER is lower than a preset threshold, it is determined that the first test item fails to test; and

the standard chip transmits a signal at a test rate to a chip to be tested according to the first test item;

and the standard chip receives the bit error rate BER fed back by the chip to be detected.

To solve the above technical problem, the present invention provides, in a second aspect, a test apparatus for a receiver chip, including:

a chip to be tested;

the standard chip is connected with the chip to be tested and used for transmitting signals at a test rate to the chip to be tested according to the first test item; and receiving the BER fed back by the chip to be tested, and judging that the first test item passes the test when the BER is higher than a preset threshold value.

In a possible implementation manner, the standard chip is further configured to transmit a signal at a test rate to the chip to be tested according to the second test item after the first test item passes the test; and

In a possible implementation manner, the chip to be tested is configured to receive and store the signal at the test rate after the signal at the test rate is transmitted to the chip to be tested according to the test firmware, and demodulate the signal at the test rate.

In a possible implementation manner, the testing apparatus further includes:

and the test machine is used for sending an instruction to the standard chip before transmitting a signal at a test rate to the chip to be tested according to the test firmware so as to enable the standard chip to enter a test state according to the instruction.

In a possible implementation manner, the standard chip is further configured to determine that the first test item fails to test when the BER is lower than a preset threshold; and

the standard chip is also used for transmitting signals under the test rate to the chip to be tested according to the first test item and receiving the bit error rate BER fed back by the chip to be tested.

Advantageous effects

According to the method and the device for testing the receiver chip, the standard chip transmits signals at a test rate to the chip to be tested according to the first test item; and the standard chip receives the bit error rate BER fed back by the chip to be tested, and judges that the first test item passes the test when the BER is higher than a preset threshold value, so that an instrument in the traditional calibration and test mode is replaced, and the test automation is realized through firmware.

According to the method and the device for testing the receiver chip, provided by the invention, simultaneous testing of a plurality of chips can be rapidly realized by adding the standard chip (gold chip), so that the testing efficiency is improved and the cost is saved.

Other features and aspects of the present invention will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features, and aspects of the invention and, together with the description, serve to explain the principles of the invention.

Fig. 1 is a schematic structural diagram illustrating a testing apparatus for a receiver chip according to an embodiment of the present invention;

fig. 2 is a flow chart illustrating a method for testing a receiver chip according to an embodiment of the present invention;

FIG. 3 shows a model diagram of a transmitter;

FIG. 4 shows a model diagram of a receiver;

fig. 5 shows a schematic diagram of a digital baseband receive path.

Detailed Description

Various exemplary embodiments, features and aspects of the present invention will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers can indicate functionally identical or similar elements. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present invention. It will be understood by those skilled in the art that the present invention may be practiced without some of these specific details. In some instances, methods, means, elements well known to those skilled in the art have not been described in detail so as not to obscure the present invention.

Example 1

Based on the requirements of the communication system for cost, area, power consumption and integration level, the zero intermediate frequency transceiver has been widely adopted in the communication system with a simpler structure, higher bandwidth, smaller area and lower power consumption compared with the super heterodyne structure transceiver.

The 802.11 protocol specifies the minimum criteria that the rf circuit should meet at different rates and modulation schemes. The primary indicators for the receiver are receive sensitivity, and for the transmitter are spectral mask, Error Vector Magnitude (EVM) and transmit power. Each WIFI chip needs to pass the performance test before delivery.

Fig. 1 is a schematic structural diagram of a test apparatus 1 for a receiver chip according to an embodiment of the present invention, and as shown in fig. 1, the test apparatus 1 includes: a gold chip 11, a testing machine 12 and a chip to be tested 13.

The standard chip (e.g., the gold chip 11) is connected to the chip 13 to be tested, and the testing machine 12 is connected to the standard chip (e.g., the gold chip 11) and the chip 13 to be tested, respectively.

In one possible implementation, the test station 12 may direct operations of transmitting a specific signal or receiving a storage signal through a specific pin. The antenna terminal of the chip to be tested 13 will be connected to the antenna terminal of the gold chip 11 to send and receive signals to communicate with the gold chip 11. Tester 12 also communicates with the chip 13 through specific pins to synchronize the calibration and test processes.

Fig. 2 is a flowchart illustrating a method for testing a receiver chip according to an embodiment of the present invention, where as shown in fig. 2, the method may include:

in step S1, the gold chip 11 transmits a signal at a test rate to the chip 13 to be tested according to the first test item.

In step S2, the chip to be tested 13 receives and stores the signal at the test rate.

Step S3, the chip to be tested 13 demodulates the signal at the test rate.

And the chip to be tested 13 demodulates the signal under the test rate and calculates the bit error rate BER.

Step S4, the gold chip 11 receives the BER fed back by the chip 13 to be tested, and when the BER is higher than the preset threshold, the first test item test is judged to pass.

In one possible implementation manner, after the first test item passes the test, the method further includes: step S5, the standard chip transmits a signal under the test rate to the chip to be tested according to a second test item; and the standard chip receives the BER fed back by the chip to be tested, and when the BER is higher than a preset threshold value, the standard chip judges that the second test item passes the test.

The receiver testing process is to test a certain speed under a certain channel, the transmitter adjusts the gain and the speed according to the receiving sensitivity regulation of the speed in the national standard, and transmits the data content appointed by the testing program stored in the testing chip in advance. The receiver demodulates and decodes the signal received from the transmitter, and then uses the received signal to compare with the previously agreed data content to calculate the BER. If the BER is higher than the threshold of the rate under the receiving gain in the national standard, i.e. the preset threshold, the test of the rate under the channel passes. The test program will continue to test other channels or other rates, at this time, the test item is changed from the first test item to the second test item, and the transmitter should adjust the rate and gain according to the change of the test item, the gold chip 11 will also transmit a signal at the test rate to the chip 13 to be tested according to the second test item, and repeat the above steps until all the receiving test items prefabricated in the test program pass.

If BER is below the threshold for the gain for that rate in the national standard, the test item fails. The test program marks the test failure of the chip to be tested according to a preset processing program or jumps out of the test program.

In one possible implementation, the testing of other channels and rates is continued, and then the channel is retested for the rate, in other words, the second test item is tested first and then the first test item is tested back, and the BER is counted for a longer time window, so as to avoid the influence of accidental events on the testing.

In summary, if the test item passes or fails, the transmitter should adjust the transmission gain and rate according to the change of the test item according to the indication of the test program.

In a possible implementation manner, before the transmitting a signal at a test rate to a chip to be tested according to test firmware, the method further includes: receiving an instruction of the testing machine 12 to enter a testing state according to the instruction.

According to the method and the device for testing the receiver chip, the standard chip transmits signals at a test rate to the chip to be tested according to the first test item; and the standard chip receives the bit error rate BER fed back by the chip to be tested, and when the BER is higher than a preset threshold value, the standard chip judges that the first test item test passes, so that an instrument in the traditional calibration and test mode is replaced, the test automation is realized through firmware, the instrument in the traditional calibration and test mode is replaced, and the test automation is realized through firmware.

The testing device 1 for the receiver chip and the testing method for the receiver chip provided by the embodiment of the invention can rapidly realize simultaneous testing of a plurality of chips by adding the standard chip (gold chip 11), thereby improving the testing efficiency and saving the cost.

Fig. 3 shows a model diagram of a transmitter. The embodiment of the invention is suitable for the transmitter shown in fig. 3. As shown in fig. 3, the transmitter 2 includes: a first digital baseband 21, a first dc offset and IQ mismatch compensation circuit 22, a digital-to-analog converter 23, a first low pass filter 24, a first mixer 25, a power amplifier 26.

Wherein the first digital baseband 21 is used to modulate the data to be transmitted such that the data is suitable for transmission via the wireless antenna. RF _ BIST _ MEM: for storing the sampled signals required for calibration and test operations. A first DC offset and IQ mismatch compensation circuit (abbreviated DC ADJ)22 compensates for DC offset and IQ mismatch on the receive path by calibration and configuration. A Digital-to-Analog Converter (DAC) 23 converts the Digital signal into an Analog signal. A first Low Pass Filter (LPF) 24 for suppressing out-of-band interference signals. The first mixer 25 modulates the data signal to a radio frequency band using a local oscillator signal mixed with a zero intermediate frequency signal. A Power Amplifier (PA) 26 for amplifying the Power of the signal outputted from the mixer and transmitting the amplified signal to the antenna.

The zero intermediate frequency transmitter has a simple structure and high integration level, but is very sensitive to direct current offset and IQ mismatch. The local oscillator leakage occurs at the transmitting end due to the direct current offset, and the carrier signal has a signal with the same frequency as the local oscillator, which causes a serious direct current offset at the receiving end and affects the performance of the receiver. Therefore, the transmission accuracy in the whole communication system can be well improved by compensating the direct current offset of the transmitter through the calibration circuit. Because signals in the zero-if transmitter are transmitted through the orthogonal I and Q signal paths, the mismatch of device performance in the two transmission circuits may cause the mismatch of amplitude and phase of the orthogonal two signal paths, resulting in the generation of useless lower sideband signals during the transmission process, which affects the performance of the receiving circuit. Therefore, the I/Q mismatch is compensated at the transmitting end, so that the performance of the transmission path can be improved. In the transmitter architecture, the pre-DAC DC _ ADJ module is used to adjust the transmitter's direct current Offset (english DC Offset) and I/Q channel mismatch.

Fig. 4 shows a diagram of a receiver model, and as shown in fig. 4, the receiver 3 comprises: a low noise amplifier 31, a local oscillator 32, a second mixer 33, a second low pass filter 34, an analog-to-digital converter 35, a second dc offset and IQ mismatch compensation circuit 36, and a second digital baseband 37.

The Low Noise Amplifier (LNA) 31 receives and amplifies a radio frequency signal received by the radio frequency antenna. A Local Oscillator 32 (LO for short). And a local oscillator 32 for generating a local oscillation signal. The second mixer 33 mixes the local oscillator signal with the RF signal received by the RF filter and converts the local oscillator signal into a zero intermediate frequency signal. And a second Low Pass Filter (LPF) 34 for suppressing out-of-band interference signals. An Analog-to-Digital Converter (ADC) 35 converts an Analog signal at zero intermediate frequency into a Digital signal. A second DC offset and IQ mismatch compensation circuit (abbreviated DC ADJ)36 compensates for DC offset and IQ mismatch on the receive path by calibration and configuration. The second digital baseband 37 demodulates the signal received on the antenna to recover the original data transmitted by the transmitter. RF _ BIST _ MEM: for storing the sampled signals required for calibration and test operations.

Since a zero intermediate frequency receiver converts a bandwidth signal to a zero intermediate frequency, excessive bias voltage may degrade the signal and may cause saturation of the mixed circuit, such as LPF or ADC. Therefore, the compensation of the direct current bias can ensure that the circuit works in an ideal working area after frequency mixing, thereby improving the performance of the receiver.

IQ mismatch is also an important factor affecting the performance of receivers with zero intermediate frequency architecture. In the zero-if structure, as shown in fig. 4, the zero-if signal output by the mixer is divided into two paths for transmission, and since there may be differences in performance among the filters, amplifiers, ADCs, and other devices in the I/Q two-path transmission path, the two paths of signals that should be orthogonal may have amplitude or phase mismatch problems, which may result in deterioration of the constellation diagram of the demodulated signal. In the receiver module, the DC _ ADJ module is also used to adjust the DC Offset and I/Q channel mismatch of the receiver. The DC _ ADJ is configured through the calibration process to compensate the amplitude and the phase of the digital signals of the I/Q two paths, so that the demodulation performance of the digital baseband can be effectively improved.

Fig. 5 shows a schematic diagram of a digital baseband receiving path, as shown in fig. 5, a Radio-Frequency (RF) circuit receives wireless data from an antenna and converts the wireless data into a digital signal. And detecting a frame header, namely detecting a transmission signal of the radio frequency circuit, and if the frame header of the data/management frame defined in the wireless transmission protocol exists, informing a subsequent baseband circuit to start demodulating the data. And performing serial-to-parallel conversion, namely dividing the OFDM signal stream into N parallel time domain signal streams, wherein each time domain signal corresponds to one subcarrier in N orthogonal subcarriers. Fast Fourier Transform (FFT) converts the N parallel time domain signals into frequency domain signals and outputs N parallel frequency domain signals. Channel estimation/equalization, which estimates transmission channel parameters for wireless transmission from a transmission signal and compensates received data using the estimated channel parameters to correct a deviation of the signal in the wireless transmission channel. And de-mapping, namely mapping the received data to a constellation diagram and decoding a corresponding data stream according to the constellation diagram. And outputting N paths of parallel data streams. And performing parallel-serial conversion, namely combining the N paths of data streams output by the demapper into one path of data stream. And channel coding demodulation, namely demodulating the channel coding according to a predefined channel coding mode in a wireless transmission protocol and restoring the data stream into original data.

The difference Vector Magnitude (EVM) test is an index for considering the quality of a modulated signal, and specifically indicates how close an IQ component generated when a receiver demodulates a signal is to an ideal signal component. The difference vector magnitude (EVM) is defined as the ratio of the root mean square value of the error vector signal mean power to the root mean square value of the ideal signal mean power and is expressed in percentage. The smaller the EVM, the better the signal quality.

As can be seen from the EVM definition, the original data of the EVM test is the data before entering the demapper, i.e. the data stream after channel estimation/equalization, so the data recorded by the RF _ BIST _ MEM when testing the EVM needs to be sampled from the channel estimation/equalization module later and the receiving path of the receiving end needs to work normally.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. A method of testing a receiver chip, comprising:

the chip to be tested receives and stores the signal under the test rate;

the chip to be tested demodulates the signal under the test rate and calculates the bit error rate BER;

the standard chip receives the bit error rate BER fed back by the chip to be tested, and when the BER is higher than a preset threshold value, the standard chip judges that the first test item test is passed;

the chip to be tested is a WIFI chip, the pins of the test machine station are used for guiding the signals of the standard chip at the test speed and guiding the chip to be tested to receive and store the signals at the test speed, and the pins of the test machine station are used for communicating with the chip to be tested so as to synchronize the calibration and test processes;

the standard chip is a gold chip, the receiver comprises a low noise amplifier, a local oscillator, a second mixer and a second low-pass filter, the low-noise amplifier is used for receiving and amplifying received radio-frequency signals, the local oscillator is used for generating local oscillator signals, the second mixer is used for mixing the local oscillator signals with the received radio-frequency signals and converting the local oscillator signals into zero intermediate-frequency signals, the second low-pass filter is used for suppressing out-of-band interference signals, the analog-digital converter is used for converting analog signals on the zero intermediate-frequency signals into digital signals, the second direct-current bias and IQ mismatch compensation circuit is used for compensating direct-current bias and IQ mismatch on a receiving path through calibration and configuration, and the second digital baseband demodulation is used for restoring the received signals into original data transmitted by the transmitter.

2. The method of claim 1, further comprising, after the first test item test passes: the standard chip transmits a signal at a test rate to the chip to be tested according to a second test item; and the standard chip receives the BER fed back by the chip to be tested, and when the BER is higher than a preset threshold value, the standard chip judges that the second test item passes the test.

3. The method according to claim 2, wherein before transmitting the signal at the test rate to the chip under test according to the first test item, the method further comprises: and the standard chip receives an instruction of a testing machine to enter a testing state according to the instruction.

4. The test method according to claim 1, wherein the first test item is determined to fail when the BER is lower than a preset threshold; the standard chip transmits signals under the test rate to the chip to be tested according to the first test item; and the standard chip receives the bit error rate BER fed back by the chip to be detected.

5. A test apparatus for a receiver chip, comprising:

the chip to be tested is a WIFI chip;

the standard chip is connected with the chip to be tested and used for transmitting signals at a test rate to the chip to be tested according to the first test item; receiving a bit error rate BER fed back by the chip to be tested, and judging that the first test item passes the test when the BER is higher than a preset threshold value;

the chip to be tested is used for receiving and storing the signals under the test rate, demodulating the signals under the test rate and calculating the Bit Error Rate (BER);

the test machine is respectively connected with the chip to be tested and the standard chip, leads the signal under the test speed of the standard chip and the signal under the test speed to be received and stored by the chip to be tested through pins of the test machine, and communicates with the chip to be tested through the pins of the test machine to synchronize the calibration and test processes;

6. The test device of claim 5, wherein the standard chip is further configured to transmit a signal at a test rate to the chip under test according to a second test item after the first test item passes the test; and the standard chip receives the BER fed back by the chip to be tested, and when the BER is higher than a preset threshold value, the standard chip judges that the second test item passes the test.

7. The testing device of claim 6, wherein the testing machine is further configured to send an instruction to the standard chip before the signal at the testing rate is transmitted to the chip to be tested according to the first test item, so that the standard chip enters the testing state according to the instruction.

8. The testing device of claim 5, wherein the standard chip is further configured to determine that the first test item fails when the BER is lower than a preset threshold; and the standard chip is also used for transmitting a signal under the test rate to the chip to be tested according to the first test item and receiving the bit error rate BER fed back by the chip to be tested.