CN103036740B - To the method for testing of network terminal gigabit ethernet interface signal in a kind of EPON system - Google Patents
To the method for testing of network terminal gigabit ethernet interface signal in a kind of EPON system Download PDFInfo
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- CN103036740B CN103036740B CN201210548382.2A CN201210548382A CN103036740B CN 103036740 B CN103036740 B CN 103036740B CN 201210548382 A CN201210548382 A CN 201210548382A CN 103036740 B CN103036740 B CN 103036740B
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Abstract
The invention discloses as follows to the method for testing of network terminal gigabit ethernet interface signal, its collocation method in a kind of EPON system：Step S1, the computer is connected with the equipment under test by serial ports, the tested interface of the equipment under test is connected with the cable interface on the experiment fixture by connecting line, the oscillograph is connected with the differential pair on the experiment fixture by connecting line；Step S2, under computer test environment, the numerical value of actual registers is read；Step S3, the numerical value of register is changed, the currency of the register read is converted into 16 bits, and is arranged to different numerical value by its high three, represents different test patterns respectively；Step S4, operation has connected each equipment of completion, selects gigabit Ethernet test event to be tested on oscillograph.By the method for testing of the present invention, ethernet port compatibility and uniformity can be tested, ensures good intercommunication between various distinct devices.
Description
Technical field
The present invention relates in local area network equipment signal testing method, more particularly to a kind of EPON system to the network terminal thousand
The method of testing of mbit ethernet interface signal.
Background technology
The coded system PAM-5 (Pyatyi pulse-amplitude modulation) of gigabit Ethernet terminal interface, when gigabit Ethernet is tested
Force full duplex and close auto negotiation.Because each pair differential pair of gigabit Ethernet can be carried out receiving and dispatching, in chip
Inside is mixed, separated, so during with oscillograph test signal, it is impossible to directly test to obtain eye as 100 m ethernet
Figure, but need to be tested by some other methods.
The content of the invention
The problem of intuitively eye pattern signal can not be directly obtained by oscillograph for gigabit Ethernet, the present invention provide one
To the method for testing of network terminal gigabit ethernet interface signal in kind EPON system.
The technical proposal for solving the technical problem of the invention is：
To the method for testing of network terminal gigabit ethernet interface signal in a kind of EPON system, based on a kind of test system
Realize, the test system includes computer, equipment under test, oscillograph and experiment fixture, and described experiment fixture one end is treated provided with 4
The differential pair of survey, the other end are provided with cable interface, and one end that the experiment fixture is provided with differential pair is connected with the oscillograph, institute
State the other end of the experiment fixture provided with cable interface to be connected with the interface end on the equipment under test, the serial ports of the computer leads to
Data wire is crossed to be connected with serial ports on the equipment under test；Wherein：
By following collocation method test interface signal：
Step S1, the computer is connected with the equipment under test by serial ports, by the tested interface of the equipment under test
It is connected with the cable interface on the experiment fixture by connecting line, by the oscillograph and the differential pair on the experiment fixture
It is connected by connecting line；
Step S2, under computer test environment, the numerical value in current equipment under test physical layer register is read；
Step S3, the numerical value of the register is changed, the currency of the register read is converted into 16 binary systems
Number, and it is arranged to different numerical value by high three of 16 bit, different test patterns is represented respectively, specifically
For：001 is arranged to by high three and represents test pattern 1, and being arranged to 010 by high three represents test pattern 2, by high three settings
Test pattern 3 is represented for 011, being arranged to 100 by high three represents test pattern 4, and amended 16 bit is converted
For 4 hexadecimal numbers, modification order is formed to configure physical chip, physical chip is operated under test mode；
Step S4, operation has connected each equipment of completion, and gigabit Ethernet test event is selected on the oscillograph
Tested.
To the method for testing of network terminal gigabit ethernet interface signal in the EPON system, wherein, the test mould
Formula 1 is tested to send signal waveform；The test pattern 2 is the jitter test of host clock；When the test pattern 3 is slave
The jitter test of clock；The test pattern 4 is transmission signal waveform distortion measurement.
To the method for testing of network terminal gigabit ethernet interface signal in the EPON system, wherein, the oscillograph
For 6GHz bandwidth oscillographs.
To the method for testing of network terminal gigabit ethernet interface signal in the EPON system, wherein, the experiment system
4 differential pairs that tool is provided with are provided with numbering, and all tested interfaces of the equipment under test are both needed to 4 described differential pairs
Tested one by one.
Above-mentioned technical proposal has the following advantages that or beneficial effect：
The inventive method is by changing the value of physical layer register inside counting device in Devices to test so that equipment under test is carried out
Ethernet signal integrity test, ethernet port compatibility and uniformity can be improved by test, ensure that various differences are set
Good intercommunication between standby.
Brief description of the drawings
Fig. 1 is the test that a kind of method of testing of ethernet network terminal gigabit ethernet interface signal of the present invention is based on
System architecture diagram.
Embodiment
The invention will be further described with specific embodiment below in conjunction with the accompanying drawings, but not as limiting to the invention.
A kind of method of testing of ethernet network terminal interface signal of the present invention, the network for the gigabit Ethernet that is particularly suitable for use in
Terminal interface method of testing.Value of the invention by changing corresponding counter in the physical layer register in equipment under test, so as to
Change the state of physical chip, it is operated under different test patterns and equipment under test is tested.
As shown in figure 1, the present invention is realized based on a kind of test system, test system includes setting tested by testing fixture
Standby to be linked together with oscillograph, the one end for testing fixture is provided with 4 differential pairs to be measured, and differential pair passes through connecting line and oscillography
Device connects, wherein, oscillograph is 6GHz bandwidth oscillographs, and the other end for testing fixture is provided with RJ45 cable interfaces, RJ45 netting twines
Interface is connected by the interface end of connecting line and equipment under test, and the serial ports on equipment under test passes through data wire and computer serial port phase
Even.
The configuration that the present invention tests is completed as follows：
Step 1：Devices to test, oscillograph, testing making apparatus and computer are connected by above-mentioned connected mode；
Step 2：The initial value of physical chip register 9 is obtained by initial command, specifically, being inputted under serial ports
The 0x09 of sw port phyreg-get 0 are ordered, wherein 0 represents the numbering of equipment under test the corresponding interface, i.e., tested interface 0,
0x09 represents the register 9 of equipment under test；
Step 3：The initial value of the physical chip register 9 obtained before is changed as follows, after obtaining modification
Numerical value：
1. the initial value for assuming to read the 0th interface register 9 is 0xe00（Hexadecimal number）；
2. the hexadecimal number is converted into by 16 bits, as 0000111000000000 by computing；
3. its high three corresponding numerical value are modified, i.e., the 15th, 14,13 of physical chip register 9 is repaiied
Change, wherein, high three bit value corresponding to test pattern 1 is 001, and high three of 16 bits before are replaced,
I.e. amended binary number is 0010111000000000；
4. amended binary number is converted into 4 hexadecimal numbers, as 0x2e00；
5. the order of modification is the 0x09 0x2e00 of sw port phyreg-set 0；
Step 4：Each equipment connected is run, and selects gigabit Ethernet test event to be surveyed on oscillograph
Examination.
The interface testing of the present invention includes test pattern 1：Send signal waveform test；Test pattern 2：Host clock is trembled
Dynamic test；Test pattern 3：The jitter test of slave clock；Test pattern 4：Send signal waveform distortion measurement.Above-mentioned step
For the collocation method of test pattern 1, the test configuration method of remaining test pattern is by the 3rd in above-mentioned step 3,4,5 steps
Modify, its specific test configuration method is as follows：
The collocation method of test pattern 2 (jitter test of host clock)：
Step 1：Devices to test, oscillograph, testing making apparatus and computer are connected by above-mentioned connected mode；
Step 2：The initial value of physical chip register 9 is obtained by initial command, specifically, being inputted under serial ports
The 0x09 of sw port phyreg-get 0 are ordered, wherein 0 represents the numbering of equipment under test the corresponding interface, i.e., tested interface 0,
0x09 represents the register 9 of equipment under test；
Step 3：The initial value of the physical chip register 9 obtained before is changed as follows, after obtaining modification
Numerical value：
1. the initial value for assuming to read register 9 in the 0th interface register is 0xe00（Hexadecimal number）；
2. the hexadecimal number is converted into by 16 bits, as 0000111000000000 by computing；
3. its high three corresponding numerical value are modified, i.e., the 15th, 14,13 of physical chip register 9 is repaiied
Change, wherein, high three bit value corresponding to test pattern 2 is 010, and high three of 16 bits before are replaced,
I.e. amended binary number is 0100111000000000；
4. amended binary number is converted into 4 hexadecimal numbers, as 0x4e00；
5. the order of modification is the 0x09 0x4e00 of sw port phyreg-set 0；
Step 4：Each equipment connected is run, and selects gigabit Ethernet test event to be surveyed on oscillograph
Examination.
The collocation method of test pattern 3 (jitter test of slave clock)：
Step 1：Devices to test, oscillograph, testing making apparatus and computer are connected by above-mentioned connected mode；
Step 2：The initial value of physical chip register 9 is obtained by initial command, specifically, being inputted under serial ports
The 0x09 of sw port phyreg-get 0 are ordered, wherein 0 represents the numbering of equipment under test the corresponding interface, i.e., tested interface 0,
0x09 represents the register 9 of equipment under test；
Step 3：The initial value of the physical chip register 9 obtained before is changed as follows, after obtaining modification
Numerical value：
1. the initial value for assuming to read the 0th interface register 9 is 0xe00（Hexadecimal number）；
2. the hexadecimal number is converted into by 16 bits, as 0000111000000000 by computing；
3. its high three corresponding numerical value are modified, i.e., the 15th, 14,13 of physical chip register 9 is repaiied
Change, wherein, high three bit value corresponding to test pattern 3 is 011, and high three of 16 bits before are replaced,
I.e. amended binary number is 0110111000000000；
4. amended binary number is converted into 4 hexadecimal numbers, as 0x6e00；
5. the order of modification is the 0x09 0x6e00 of sw port phyreg-set 0；
Step 4：Each equipment connected is run, and selects gigabit Ethernet test event to be surveyed on oscillograph
Examination.
The collocation method of test pattern 4 (sending signal waveform distortion measurement)：
Step 1：Devices to test, oscillograph, testing making apparatus and computer are connected by above-mentioned connected mode；
Step 2：The initial value of physical chip register 9 is obtained by initial command, specifically, being inputted under serial ports
The 0x09 of sw port phyreg-get 0 are ordered, wherein 0 represents the numbering of equipment under test the corresponding interface, i.e., tested interface 0,
0x09 represents the register 9 of equipment under test；
Step 3：The initial value of the physical chip register 9 obtained before is changed as follows, after obtaining modification
Numerical value：
1. the initial value for assuming to read the 0th interface register 9 is 0xe00（Hexadecimal number）；
2. the hexadecimal number is converted into by 16 bits, as 0000111000000000 by computing；
3. its high three corresponding numerical value are modified, i.e., the 15th, 14,13 of physical chip register 9 is repaiied
Change, wherein, high three bit value corresponding to test pattern 4 is 100, and high three of 16 bits before are replaced,
I.e. amended binary number is 1000111000000000；
4. amended binary number is converted into 4 hexadecimal numbers, as 0x8e00；
5. the order of modification is the 0x09 0x8e00 of sw port phyreg-set 0；
Step 4：Each equipment connected is run, and selects gigabit Ethernet test event to be surveyed on oscillograph
Examination.
Preferred embodiments of the present invention are the foregoing is only, not thereby limit the claim of the present invention, so
All equivalent structures with made by description of the invention and diagramatic content change, and are all contained in protection scope of the present invention.
Claims (3)
- It is 1. real based on a kind of test system to the method for testing of network terminal gigabit ethernet interface signal in a kind of EPON system Existing, the test system includes computer, equipment under test, oscillograph and experiment fixture, and described experiment fixture one end is to be measured provided with 4 Differential pair, the other end is provided with cable interface, and one end that the experiment fixture is provided with differential pair is connected with the oscillograph, described The other end that experiment fixture is provided with cable interface is connected with the interface end on the equipment under test, and the serial ports of the computer passes through Data wire is connected with serial ports on the equipment under test；Interface testing includes test pattern 1 to send signal waveform test, tests mould Formula 2 is the jitter test of host clock, and test pattern 3 is the jitter test of slave clock, and test pattern 4 is transmission signal waveform Distortion measurement, it is characterised in that：By following collocation method test interface signal：The collocation method of test pattern 1：Step S1, the computer is connected with the equipment under test by serial ports, by the tested interface of the equipment under test and institute The cable interface stated on experiment fixture is connected by connecting line, and the oscillograph and the differential pair on the experiment fixture are passed through Connecting line is connected；Step S2, under computer test environment, the 0x09 of input order sw port phyreg-get 0 under serial ports, wherein 0 generation The numbering of table equipment under test the corresponding interface, i.e., tested interface 0,0x09 represent the register 9 of equipment under test, read current be tested and set Numerical value 0xe00 in standby physical layer register；Step S3, the numerical value of the register is changed, the currency 0xe00 of the 0th interface register 9 read is converted to 16 Bit 0000111000000000, and high three of 16 bit 0000111000000000 are arranged to 001 represents test pattern 1, i.e., amended binary system is 0010111000000000, by amended 16 bit 0010111000000000 is converted into 4 hexadecimal number 0x2e00, forms modification order sw port phyreg-set 0 0x09 0x2e00 configure physical chip, physical chip is operated under test mode；Step S4, operation has connected each equipment of completion, selects gigabit Ethernet test event to carry out on the oscillograph Test；The collocation method of test pattern 2：Step S21, the computer is connected with the equipment under test by serial ports, by the tested interface of the equipment under test and institute The cable interface stated on experiment fixture is connected by connecting line, and the oscillograph and the differential pair on the experiment fixture are passed through Connecting line is connected；Step S22, under computer test environment, the 0x09 of input order sw port phyreg-get 0 under serial ports, wherein 0 The numbering of equipment under test the corresponding interface is represented, i.e., tested interface 0,0x09 represents the register 9 of equipment under test, reads current tested Numerical value 0xe00 in physical layer of device register；Step S23, the numerical value of the register is changed, the currency 0xe00 of the 0th interface register 9 read is converted to 16 bits 0000111000000000, and high three of 16 bit 0000111000000000 are set Test pattern 2 is represented for 010, i.e., amended binary system is 0100111000000000, by amended 16 bit 0100111000000000 is converted into 4 hexadecimal number 0x4e00, forms modification order sw port phyreg-set 0 0x09 0x4e00 configure physical chip, physical chip is operated under test mode；Step S24, operation has connected each equipment of completion, selects gigabit Ethernet test event to carry out on the oscillograph Test；The collocation method of test pattern 3：Step S31, the computer is connected with the equipment under test by serial ports, by the tested interface of the equipment under test and institute The cable interface stated on experiment fixture is connected by connecting line, and the oscillograph and the differential pair on the experiment fixture are passed through Connecting line is connected；Step S32, under computer test environment, the 0x09 of input order sw port phyreg-get 0 under serial ports, wherein 0 The numbering of equipment under test the corresponding interface is represented, i.e., tested interface 0,0x09 represents the register 9 of equipment under test, reads current tested Numerical value 0xe00 in physical layer of device register；Step S33, the numerical value of the register is changed, the currency 0xe00 of the 0th interface register 9 read is converted to 16 bits 0000111000000000, and high three of 16 bit 0000111000000000 are set Test pattern 3 is represented for 011, i.e., amended binary system is 0110111000000000, by amended 16 bit 0110111000000000 is converted into 4 hexadecimal number 0x6e00, forms modification order sw port phyreg-set 0 0x09 0x6e00 configure physical chip, physical chip is operated under test mode；Step S34, operation has connected each equipment of completion, selects gigabit Ethernet test event to carry out on the oscillograph Test；The collocation method of test pattern 4：Step S41, the computer is connected with the equipment under test by serial ports, by the tested interface of the equipment under test and institute The cable interface stated on experiment fixture is connected by connecting line, and the oscillograph and the differential pair on the experiment fixture are passed through Connecting line is connected；Step S42, under computer test environment, the 0x09 of input order sw port phyreg-get 0 under serial ports, wherein 0 The numbering of equipment under test the corresponding interface is represented, i.e., tested interface 0,0x09 represents the register 9 of equipment under test, reads current tested Numerical value 0xe00 in physical layer of device register；Step S43, the numerical value of the register is changed, the currency 0xe00 of the 0th interface register 9 read is converted to 16 bits 0000111000000000, and high three of 16 bit 0000111000000000 are set Test pattern 4 is represented for 100, i.e., amended binary system is 1000111000000000, by amended 16 bit 1000111000000000 are converted into 4 hexadecimal number 0x8e00, form modification order sw port phyreg-set 0 0x09 0x8e00 configure physical chip, physical chip is operated under test mode；Step S44, operation has connected each equipment of completion, selects gigabit Ethernet test event to carry out on the oscillograph Test.
- 2. to the method for testing of network terminal gigabit ethernet interface signal, its feature in EPON system as claimed in claim 1 It is, the oscillograph is 6GHz bandwidth oscillographs.
- 3. to the method for testing of network terminal gigabit ethernet interface signal, its feature in EPON system as claimed in claim 1 It is, 4 differential pairs being provided with of experiment fixture are provided with numbering, and all tested interfaces of the equipment under test are both needed to pair 4 described differential pairs are tested one by one.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103701660B (en) * | 2013-12-20 | 2018-01-02 | 上海斐讯数据通信技术有限公司 | A kind of ethernet device attachment means and its test system and method for application |
| CN103955418A (en) * | 2014-04-10 | 2014-07-30 | 龙芯中科技术有限公司 | Method and system for testing network card chip |
| CN105391603B (en) * | 2015-12-17 | 2019-06-21 | 迈普通信技术股份有限公司 | A kind of system and method for testing 10,000,000,000 electric signals |
| CN107426118B (en) * | 2017-07-24 | 2020-05-12 | 西安微电子技术研究所 | Gigabit Ethernet switching circuit access device based on MDC/MDIO interface |
| CN109194537A (en) * | 2018-08-02 | 2019-01-11 | 郑州云海信息技术有限公司 | A kind of Ethernet is given out a contract for a project test method and device |
| CN110798383B (en) * | 2019-11-04 | 2022-03-29 | 中国铁道科学研究院集团有限公司 | Gigabit Ethernet test system and method |
| CN111060772B (en) * | 2019-12-31 | 2022-11-11 | 瑞斯康达科技发展股份有限公司 | Test system and test method |
| CN116257398B (en) * | 2023-05-11 | 2023-10-03 | 中星联华科技（北京）有限公司 | Serial port testing method and system |
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| CN1538681A (en) * | 2003-04-17 | 2004-10-20 | 华为技术有限公司 | Code flow generator for testing Ethernet interface |
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| CN1538681A (en) * | 2003-04-17 | 2004-10-20 | 华为技术有限公司 | Code flow generator for testing Ethernet interface |
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