CN103036740A - Ethernet passive optical network (EPON) system testing method for network terminal gigabit Ethernet interface signal - Google Patents
Ethernet passive optical network (EPON) system testing method for network terminal gigabit Ethernet interface signal Download PDFInfo
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- CN103036740A CN103036740A CN2012105483822A CN201210548382A CN103036740A CN 103036740 A CN103036740 A CN 103036740A CN 2012105483822 A CN2012105483822 A CN 2012105483822A CN 201210548382 A CN201210548382 A CN 201210548382A CN 103036740 A CN103036740 A CN 103036740A
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Abstract
The invention discloses an Ethernet passive optical network (EPON) system testing method for a network terminal gigabit Ethernet interface signal. The method comprises the following steps: S1 connecting a computer with a device to be tested through serial ports, connecting an interface to be tested of the device to be tested with a network cable interface of a test tool through a connecting wire, and connecting an oscillograph with a differential pair of the test tool through a connecting wire, S2 reading a current value of a register under computer test environment, S3 modifying the value of the register, converting the read current value of the register to a 16 bit binary number, and setting three high orders into different values which respectively stand for different test modes, and S4 operating connected each device and conducting test by choosing gigabit Ethernet test items in the oscillograph. According to the testing method, compatibility and consistency of Ethernet ports can be tested, and good interflow among various different devices is guaranteed.
Description
Technical field
The present invention relates to LAN device signal method of testing, relate in particular in a kind of EPON system method of testing to network terminal gigabit ethernet interface signal.
Background technology
The coded system PAM-5 of gigabit Ethernet terminal interface (Pyatyi pulse-amplitude modulation) will force full duplex and close auto negotiation during the gigabit Ethernet test.Because every pair of differential pair of gigabit Ethernet can be received and dispatched, mix, separate at chip internal, so during with the oscilloscope test signal, can not as 100 m ethernet, direct test obtain eye pattern, but need to test by some additive methods.
Summary of the invention
Can't directly obtain the intuitively problem of eye pattern signal by oscilloscope for gigabit Ethernet, the invention provides in a kind of EPON system method of testing to network terminal gigabit ethernet interface signal.
The technical scheme that technical solution problem of the present invention adopts is:
In a kind of EPON system to the method for testing of network terminal gigabit ethernet interface signal, realize based on a kind of test macro, described test macro comprises computer, equipment under test, oscilloscope and test fixture, described test fixture one end is provided with 4 differential pairs to be measured, the other end is provided with cable interface, the end that described test fixture is provided with differential pair is connected with described oscilloscope, described test fixture is provided with the other end of cable interface and is connected with interface end on the described equipment under test, and the serial ports of described computer is connected with serial ports on the described equipment under test by data wire; Wherein:
Press following collocation method test interface signal:
Step S1, described computer is linked to each other by serial ports with described equipment under test, the tested interface of described equipment under test is linked to each other by connecting line with cable interface on the described test fixture, described oscilloscope is linked to each other by connecting line with differential pair on the described test fixture;
Step S2, under the computer test environment, read the numerical value in the current equipment under test physical layer register;
Step S3, change the numerical value of described register, the currency of the register that reads is converted to 16 bits, and the Senior Three position of described 16 bits is arranged to different numerical value, represent respectively different test patterns, be specially: the Senior Three position is set to 001 and represents test pattern 1, the Senior Three position is set to 010 and represents test pattern 2, the Senior Three position is set to 011 and represents test pattern 3, the Senior Three position is set to 100 and represents test pattern 4, amended 16 bits are converted into 4 hexadecimal numbers, form to revise and order configures physical layer chip, physical chip is operated under the test mode;
Step S4, operation have connected each equipment of finishing, select the gigabit Ethernet test event to test at described oscilloscope.
To the method for testing of network terminal gigabit ethernet interface signal, wherein, described test pattern 1 is the transmitted signal waveform testing in the described EPON system; Described test pattern 2 is the jitter test of host clock; Described test pattern 3 is the jitter test of slave clock; Described test pattern 4 is the test of transmitted signal wave distortion.
To the method for testing of network terminal gigabit ethernet interface signal, wherein, described oscilloscope is 6GHz bandwidth oscilloscope in the described EPON system.
To the method for testing of network terminal gigabit ethernet interface signal, wherein, 4 differential pairs that described test fixture is provided with are provided with numbering in the described EPON system, and the tested interface of all of described equipment under test all needs test one by one described 4 differential pairs.
Technique scheme has following advantage or beneficial effect:
The inventive method so that equipment under test carries out the ethernet signal integrity test, can improve ethernet port compatibility and consistency by test by revising the value of physical layer register inside counting device in the Devices to test, guarantees good intercommunication between various distinct devices.
Description of drawings
Fig. 1 be a kind of ethernet network terminal of the present invention gigabit ethernet interface signal method of testing based on the test system structure block diagram.
Embodiment
The invention will be further described below in conjunction with the drawings and specific embodiments, but not as limiting to the invention.
The method of testing of a kind of ethernet network terminal interface of the present invention signal is particularly useful for the network terminating interface method of testing of gigabit Ethernet.The present invention is by the value of corresponding counts device in the physical layer register in the change equipment under test, thereby the state of change physical chip is operated under the different test patterns it equipment under test is tested.
As shown in Figure 1, the present invention is based on a kind of test macro realizes, test macro comprise by the test fixture equipment under test and oscilloscope are linked together, one end of test fixture is provided with 4 differential pairs to be measured, differential pair is connected with oscilloscope by connecting line, wherein, oscilloscope is 6GHz bandwidth oscilloscope, the other end of test fixture is provided with the RJ45 cable interface, the RJ45 cable interface is connected with the interface end of equipment under test by connecting line, and the serial ports on the equipment under test links to each other with the computer serial ports by data wire.
Finish as follows the configuration of the present invention's test:
Step 1: Devices to test, oscilloscope, testing making apparatus and computer are connected above-mentioned connected mode connect;
Step 2: the initial value that obtains physical chip register 9 by initial command, be specially input command sw port phyreg-get 0 0x09 under serial ports, wherein 0 numbering that represents equipment under test the corresponding interface, be tested interface 0,0x09 represents the register 9 of equipment under test;
Step 3: the initial value of the physical chip register 9 that obtains before the change as follows obtains amended numerical value:
1. suppose that the initial value that reads the 0th interface register 9 is the 0xe00(hexadecimal number);
2. convert this hexadecimal number to 16 bits by computing, be 0000111000000000;
3. the corresponding numerical value in its Senior Three position is made amendment, make amendment for the 15th, 14,13 that is physical chip register 9, wherein, the Senior Three bit value of test pattern 1 correspondence is 001, the Senior Three position of before 16 bits is replaced, and namely amended binary number is 0010111000000000;
4. amended binary number is converted to 4 hexadecimal numbers, is 0x2e00;
5. the order of revising is sw port phyreg-set 0 0x09 0x2e00;
Step 4: move each equipment that has connected, and select the gigabit Ethernet test event to test at oscilloscope.
Interface testing of the present invention comprises test pattern 1: the transmitted signal waveform testing; Test pattern 2: the jitter test of host clock; Test pattern 3: the jitter test of slave clock; Test pattern 4: transmitted signal wave distortion test.Above-mentioned step is the collocation method of test pattern 1, and the test configuration method of all the other test patterns is for revising the 3rd in the above-mentioned step 3,4,5 steps, and its concrete test configuration method is as follows:
The collocation method of test pattern 2 (jitter test of host clock):
Step 1: Devices to test, oscilloscope, testing making apparatus and computer are connected above-mentioned connected mode connect;
Step 2: the initial value that obtains physical chip register 9 by initial command, be specially input command sw port phyreg-get 0 0x09 under serial ports, wherein 0 numbering that represents equipment under test the corresponding interface, be tested interface 0,0x09 represents the register 9 of equipment under test;
Step 3: the initial value of the physical chip register 9 that obtains before the change as follows obtains amended numerical value:
1. suppose that the initial value that reads register 9 in the 0th interface register is the 0xe00(hexadecimal number);
2. convert this hexadecimal number to 16 bits by computing, be 0000111000000000;
3. the corresponding numerical value in its Senior Three position is made amendment, make amendment for the 15th, 14,13 that is physical chip register 9, wherein, the Senior Three bit value of test pattern 2 correspondences is 010, the Senior Three position of before 16 bits is replaced, and namely amended binary number is 0100111000000000;
4. amended binary number is converted to 4 hexadecimal numbers, is 0x4e00;
5. the order of revising is sw port phyreg-set 0 0x09 0x4e00;
Step 4: move each equipment that has connected, and select the gigabit Ethernet test event to test at oscilloscope.
The collocation method of test pattern 3 (jitter test of slave clock):
Step 1: Devices to test, oscilloscope, testing making apparatus and computer are connected above-mentioned connected mode connect;
Step 2: the initial value that obtains physical chip register 9 by initial command, be specially input command sw port phyreg-get 0 0x09 under serial ports, wherein 0 numbering that represents equipment under test the corresponding interface, be tested interface 0,0x09 represents the register 9 of equipment under test;
Step 3: the initial value of the physical chip register 9 that obtains before the change as follows obtains amended numerical value:
1. suppose that the initial value that reads the 0th interface register 9 is the 0xe00(hexadecimal number);
2. convert this hexadecimal number to 16 bits by computing, be 0000111000000000;
3. the corresponding numerical value in its Senior Three position is made amendment, make amendment for the 15th, 14,13 that is physical chip register 9, wherein, the Senior Three bit value of test pattern 3 correspondences is 011, the Senior Three position of before 16 bits is replaced, and namely amended binary number is 0110111000000000;
4. amended binary number is converted to 4 hexadecimal numbers, is 0x6e00;
5. the order of revising is sw port phyreg-set 0 0x09 0x6e00;
Step 4: move each equipment that has connected, and select the gigabit Ethernet test event to test at oscilloscope.
The collocation method of test pattern 4 (test of transmitted signal wave distortion):
Step 1: Devices to test, oscilloscope, testing making apparatus and computer are connected above-mentioned connected mode connect;
Step 2: the initial value that obtains physical chip register 9 by initial command, be specially input command sw port phyreg-get 0 0x09 under serial ports, wherein 0 numbering that represents equipment under test the corresponding interface, be tested interface 0,0x09 represents the register 9 of equipment under test;
Step 3: the initial value of the physical chip register 9 that obtains before the change as follows obtains amended numerical value:
1. suppose that the initial value that reads the 0th interface register 9 is the 0xe00(hexadecimal number);
2. convert this hexadecimal number to 16 bits by computing, be 0000111000000000;
3. the corresponding numerical value in its Senior Three position is made amendment, make amendment for the 15th, 14,13 that is physical chip register 9, wherein, the Senior Three bit value of test pattern 4 correspondences is 100, the Senior Three position of before 16 bits is replaced, and namely amended binary number is 1000111000000000;
4. amended binary number is converted to 4 hexadecimal numbers, is 0x8e00;
5. the order of revising is sw port phyreg-set 0 0x09 0x8e00;
Step 4: move each equipment that has connected, and select the gigabit Ethernet test event to test at oscilloscope.
The above is only for preferred embodiment of the present invention, is not so limits claim of the present invention, so the equivalent structure that all utilizations specification of the present invention and diagramatic content have been done changes, all is included in protection scope of the present invention.
Claims (4)
- In the EPON system to the method for testing of network terminal gigabit ethernet interface signal, realize based on a kind of test macro, described test macro comprises computer, equipment under test, oscilloscope and test fixture, described test fixture one end is provided with 4 differential pairs to be measured, the other end is provided with cable interface, the end that described test fixture is provided with differential pair is connected with described oscilloscope, described test fixture is provided with the other end of cable interface and is connected with interface end on the described equipment under test, and the serial ports of described computer is connected with serial ports on the described equipment under test by data wire; It is characterized in that:Press following collocation method test interface signal:Step S1, described computer is linked to each other by serial ports with described equipment under test, the tested interface of described equipment under test is linked to each other by connecting line with cable interface on the described test fixture, described oscilloscope is linked to each other by connecting line with differential pair on the described test fixture;Step S2, under the computer test environment, read the numerical value in the current equipment under test physical layer register;Step S3, change the numerical value of described register, the currency of the register that reads is converted to 16 bits, and the Senior Three position of described 16 bits is arranged to different numerical value, represent respectively different test patterns, be specially: the Senior Three position is set to 001 and represents test pattern 1, the Senior Three position is set to 010 and represents test pattern 2, the Senior Three position is set to 011 and represents test pattern 3, the Senior Three position is set to 100 and represents test pattern 4, amended 16 bits are converted into 4 hexadecimal numbers, form to revise and order configures physical layer chip, physical chip is operated under the test mode;Step S4, operation have connected each equipment of finishing, select the gigabit Ethernet test event to test at described oscilloscope.
- As claimed in claim 1 in the EPON system to the method for testing of network terminal gigabit ethernet interface signal, it is characterized in that described test pattern 1 is the transmitted signal waveform testing; Described test pattern 2 is the jitter test of host clock; Described test pattern 3 is the jitter test of slave clock; Described test pattern 4 is the test of transmitted signal wave distortion.
- As claimed in claim 1 in the EPON system to the method for testing of network terminal gigabit ethernet interface signal, it is characterized in that described oscilloscope is 6GHz bandwidth oscilloscope.
- As claimed in claim 1 in the EPON system to the method for testing of network terminal gigabit ethernet interface signal, it is characterized in that, 4 differential pairs that described test fixture is provided with are provided with numbering, and the tested interface of all of described equipment under test all needs described 4 differential pairs are tested one by one.
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| CN201210548382.2A CN103036740B (en) | 2012-12-17 | 2012-12-17 | To the method for testing of network terminal gigabit ethernet interface signal in a kind of EPON system |
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Cited By (8)
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| CN103701660A (en) * | 2013-12-20 | 2014-04-02 | 上海斐讯数据通信技术有限公司 | Ethernet equipment connection device and testing system and method applied thereby |
| CN103955418A (en) * | 2014-04-10 | 2014-07-30 | 龙芯中科技术有限公司 | Method and system for testing network card chip |
| CN105391603A (en) * | 2015-12-17 | 2016-03-09 | 迈普通信技术股份有限公司 | A system and method for testing 10-gigabit electrical signals |
| CN107426118A (en) * | 2017-07-24 | 2017-12-01 | 西安微电子技术研究所 | A kind of gigabit Ethernet switched circuit access mechanism based on MDC/MDIO interfaces |
| CN109194537A (en) * | 2018-08-02 | 2019-01-11 | 郑州云海信息技术有限公司 | A kind of Ethernet is given out a contract for a project test method and device |
| CN110798383A (en) * | 2019-11-04 | 2020-02-14 | 中国铁道科学研究院集团有限公司 | Ethernet test system and method |
| CN111060772A (en) * | 2019-12-31 | 2020-04-24 | 瑞斯康达科技发展股份有限公司 | Test system and test method |
| CN116257398A (en) * | 2023-05-11 | 2023-06-13 | 中星联华科技（北京）有限公司 | Serial port testing method and system |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103701660A (en) * | 2013-12-20 | 2014-04-02 | 上海斐讯数据通信技术有限公司 | Ethernet equipment connection device and testing system and method applied thereby |
| CN103701660B (en) * | 2013-12-20 | 2018-01-02 | 上海斐讯数据通信技术有限公司 | A kind of ethernet device attachment means and its test system and method for application |
| CN103955418A (en) * | 2014-04-10 | 2014-07-30 | 龙芯中科技术有限公司 | Method and system for testing network card chip |
| CN105391603A (en) * | 2015-12-17 | 2016-03-09 | 迈普通信技术股份有限公司 | A system and method for testing 10-gigabit electrical signals |
| CN105391603B (en) * | 2015-12-17 | 2019-06-21 | 迈普通信技术股份有限公司 | A kind of system and method for testing 10,000,000,000 electric signals |
| CN107426118A (en) * | 2017-07-24 | 2017-12-01 | 西安微电子技术研究所 | A kind of gigabit Ethernet switched circuit access mechanism based on MDC/MDIO interfaces |
| CN109194537A (en) * | 2018-08-02 | 2019-01-11 | 郑州云海信息技术有限公司 | A kind of Ethernet is given out a contract for a project test method and device |
| CN110798383A (en) * | 2019-11-04 | 2020-02-14 | 中国铁道科学研究院集团有限公司 | Ethernet test system and method |
| CN111060772A (en) * | 2019-12-31 | 2020-04-24 | 瑞斯康达科技发展股份有限公司 | Test system and test method |
| CN116257398A (en) * | 2023-05-11 | 2023-06-13 | 中星联华科技（北京）有限公司 | Serial port testing method and system |
| CN116257398B (en) * | 2023-05-11 | 2023-10-03 | 中星联华科技（北京）有限公司 | Serial port testing method and system |
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