CN103166698A - 10*10 Giga-bits per second (G) signal source code pattern generator - Google Patents
10*10 Giga-bits per second (G) signal source code pattern generator Download PDFInfo
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- CN103166698A CN103166698A CN2013100613881A CN201310061388A CN103166698A CN 103166698 A CN103166698 A CN 103166698A CN 2013100613881 A CN2013100613881 A CN 2013100613881A CN 201310061388 A CN201310061388 A CN 201310061388A CN 103166698 A CN103166698 A CN 103166698A
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Abstract
The invention discloses a 10*10 Giga-bits per second (G) signal source code pattern generator. The 10*10 G signal source code pattern generator comprises a signal element generating unit which is capable of generating 10 routes of 10 Giga-bits per second (Gbps) data signals and one route of clock signals, an external signal input unit which is used for transmitting external signals to the signal element generating unit, a clock signal output unit which is used for generating the clock signals and transmitting the clock signals to the signal element generating unit, and a signal output unit which is connected with the signal element generating unit and is used for outputting the 10 routes of the 10 Gbps data signals. The 10*10G signal source code pattern generator has the advantages of being small in size, simple in circuit, good in signal quality, good in code pattern effect, rapid in response speed, stable and reliable in work, simple in use, and the like, and being good in temperature stability, and long in service life.
Description
Technical field
The present invention relates to the optical communication technique field, be specifically related to a kind of 10*10G signal source pattern generator.
Background technology
Optical communication network is just fast-developing towards the direction that scale is constantly expanded, capacity rapid growth, business become increasingly abundant, use further flexibly, demand becomes more diverse.
Tradition 10G transmission network need to be used a large amount of 40G, 100G optical device and optical module to the 40G/100G network transition, and the electrical signal rate of 40G optical module, 100G optical module is the 10G signal of telecommunication, therefore need to use in a large number the signal of telecommunication code element of 10G when test 40G optical module, 100G optical module.
And general 10G signal source pattern generator is all the instrument type, has that equipment is large, a limited number of defectives of interface, and only has at most 4 10G signal elements.
Summary of the invention
The technical problem to be solved in the present invention is, a kind of 10*10G signal source pattern generator is provided, and can produce the homology signal element of 10G, for 10G optical module, device provide the signal of telecommunication, as its test code element; Also can be used for the test of 40G optical module, be its signal of telecommunication code element that 4 road 10G are provided, also can be used for the test of 100G optical module, the signal of telecommunication code element of 10 road 10G is provided for the 100G optical module.
In order to solve the problems of the technologies described above, the invention provides a kind of 10*10G signal source pattern generator, comprising:
Can produce the signal element generation unit of 10 road 10Gbps data-signals and 1 tunnel clock signal;
External signal is transferred to the external signal input unit of signal element generation unit;
Clocking also is transferred to clock signal the clock signal output unit of signal element generation unit; And
Be connected and export the signal output unit of 10 road 10Gbps data-signals with the signal element generation unit.
Further, also include the Single-chip Controlling unit that the signal element generation unit is controlled.
Further, be provided with level transferring chip between described signal element generation unit and Single-chip Controlling unit.
Further, described Single-chip Controlling unit also connects external equipment.
Further, also include voltage source unit, described voltage source unit is connected with the Single-chip Controlling unit with signal element generation unit, clock signal output unit respectively.
Further, described signal element generation unit comprises:
Recovering clock signals is become the clock data recovery device of clock; And
External signal is demultiplexed into the demodulation multiplexer of 10 road 10Gbps data-signals.
Further, the clock signal of described clock signal output unit output is variable clock signal, and the output speed of described clock signal output unit is 622M-697M.
Further, the output speed of described signal output unit is 16 times of clock signal output unit output speed.
Further, described external signal is 4 road 28.3Gbps serial data bit streams.
10*10G signal source pattern generator of the present invention has flexibly and to build, and can provide corresponding electrical interface to optical device, the optical module of different rates, has very large flexibility, is the ideal tools of analyzing the 10G/40G/100G optical module.
And the present invention also has wide bandwidth, and low noise advantage can realize quick switching between the signal of different mode, and supports the length of User Defined PRBS (Pseudo Random Binary Sequence, pseudo-random binary sequence) pattern.
In sum, it is little that 10*10G signal source pattern generator has a volume, simple circuit, and signal quality is good, pattern is effective, and fast response time, working stability is reliable and the advantage such as easy to use, and temperature stability and long working life are preferably arranged.
Description of drawings
Fig. 1 is the structure chart of 10*10G signal source pattern generator of the present invention;
Fig. 2 is the structure connection layout of clock signal output unit of the present invention and signal element generation unit;
Fig. 3 is the structure connection layout of monolithic control unit of the present invention and signal element generation unit;
Fig. 4 is the function diagram of signal element generation unit of the present invention;
Fig. 5 is the function diagram of voltage source unit of the present invention;
Fig. 6 is the structure chart of signal element generation unit of the present invention.
In figure, 10. clock signal output unit, 20. Single-chip Controlling unit, 30. signal element generation unit, 301. clock data recovery device, 302.10 demodulation multiplexers, 303. frame controllers, 40. voltage source unit, 401. filter circuit, 402. filter circuits, 403. filter circuits, 50. the external signal input unit, 60. signal output units.
Embodiment
The invention will be further described below in conjunction with the drawings and specific embodiments, can be implemented so that those skilled in the art can better understand the present invention also, but illustrated embodiment is not as a limitation of the invention.
As shown in Figure 1, the structure chart for 10*10G signal source pattern generator of the present invention comprises:
Can produce the signal element generation unit 30 of 10 road 10Gbps data-signals and 1 tunnel clock signal;
External signal is transferred to the external signal input unit 50 of signal element generation unit 30;
Clocking also is transferred to clock signal the clock signal output unit 10 of signal element generation unit 30;
The Single-chip Controlling unit 20 that signal element generation unit 30 is controlled; And
Be connected and export the signal output unit 60 of 10 road 10Gbps data-signals with signal element generation unit 30.
As shown in Figure 2, clock signal output unit 10: clocking, and clock signal is exported to signal element generation unit 30, and this clock signal is variable clock signal, the clock signal output speed is 622M-697M.
Change the output speed of clock signal output unit 10, the output speed of signal output unit 60 also changes thereupon, and in the present embodiment, the output speed of signal output unit 60 is 16 times of output speed of clock signal output unit 10.
As shown in Figure 3, be provided with level transferring chip between described signal element generation unit 30 and Single-chip Controlling unit 20.
Communicating by letter between Single-chip Controlling unit 20 and signal element generation unit 30 changed by level transferring chip, Single-chip Controlling unit 20 comes the register information in read-write code element generation unit 30, for signal element generation unit 30 provides stable, normal condition of work.
Single-chip Controlling unit 20 can directly utilize USB to be connected with external equipment (for example computer).Thereby utilize external equipment to control Single-chip Controlling unit 20, and then the work of control signal code element generation unit 30.
As shown in Figure 5, required operating voltage when guaranteeing unit of the present invention work, the present invention also is provided with voltage source unit 40, for Single-chip Controlling unit 20, clock signal output unit 10 and signal element generation unit 30 provide operating voltage.
The filter circuit 401 of voltage source unit 40 is connected with clock signal output unit 10, and filter circuit 402 is connected with signal element generation unit 30, filter circuit 403 is connected with Single-chip Controlling unit 20.It is noise section for the high and low frequency of filtering Voltage-output port that the present invention is preferably filter circuit.
As shown in Figure 6, structure chart for signal element generation unit 30, the core of this functional block is 100G demultiplexing chip, comprise clock data recovery circuit, and have the cable end offset correction function for CAUI or MLD application, and compatible OIF defines the optional precompile pattern of SFI-S interface.
The function of 100G demultiplexing chip is 4 road 28.3Gbps serial data bit streams that receive single-ended or difference, then this data code flow is resolved into 10 paths, and chip internal integrated a clock data recovery circuit, be used for recovered clock and data.
Its internal structure mainly comprises clock data recovery device 301,10 demodulation multiplexers 302 and frame controller 303.Realize again regularly through clock data recovery circuit, simultaneously through demultiplexing into 10 tunnel parallel 10Gb/s differential electric signal, one road 10G differential data clock signal and one tunnel important alignment reference data signals after serial/parallel conversion shape.
4 road 28.3bps signals that receive realize regularly restoring 100Gb/s data and clock by clock data recovery device 301 again, then through serial/parallel conversion output 10 tunnel 10Gbps level data and one tunnel difference 3.125GHz parallel clock signals than low rate.
Also can spontaneous generation PRBS(Pseudo Random Binary Sequence, pseudo-random binary sequence) pattern, output 10 tunnel is than low rate 10Gbps level data and one tunnel difference 3.125GHz parallel clock or export 10 the tunnel than low rate 10Gbps level data and one tunnel difference 3GHz parallel clock.
Idiographic flow: high-speed electrical signals is input to the demultiplexing chip and recovers data and clock signal through clock data recovery device 301, be recycled solution through 10 demodulation multiplexers and become 10 road receive data buses, the first via that receives is write into and RXDATA[9] be associated more regularly in buffer, last road enters and RXDATA[0] be associated more regularly in buffer; 10 demodulation multiplexers 302 can demultiplex into 4 road 28.3Gbps serial data bit streams 10 road 10Gbps telecommunication signal passages; Also can select the PRBS pattern can spontaneous generation 10 road 10Gbps telecommunication signal passages.
For external signal input unit 50: the data wire of 4 tunnel 28.3 Gbps high-speed electrical signals of input carries out single-ended cabling, and resistance value is controlled at 50O coupling, the isometric coupling of data signal line.
Signal output unit 60: 10 tunnel data signal line and clock data signal lines than low rate 10Gbps of output carry out single-ended cabling, and resistance value is controlled at 50O coupling, the isometric coupling of data signal line.
Clock signal frequency is higher, for avoiding transmission line effect, requires the difference wiring, exact matching differential pair cabling.The impedance Control of high-speed data signal line, clock data holding wire is the emphasis of signal quality quality.
The present invention has reduced the length of high-speed transmission line, has reduced the transmission line effect of holding wire; Eliminated the hidden danger of crosstalking; Also reduced interacting between the various power supplys in the system.
The above embodiment is the preferred embodiment that proves absolutely that the present invention lifts, and protection scope of the present invention is not limited to this.Being equal to that those skilled in the art do on basis of the present invention substitutes or conversion, all within protection scope of the present invention.Protection scope of the present invention is as the criterion with claims.
Claims (9)
1. a 10*10G signal source pattern generator, is characterized in that, comprising:
Can produce the signal element generation unit of 10 road 10Gbps data-signals and 1 tunnel clock signal;
External signal is transferred to the external signal input unit of signal element generation unit;
Clocking also is transferred to clock signal the clock signal output unit of signal element generation unit; And
Be connected and export the signal output unit of 10 road 10Gbps data-signals with the signal element generation unit.
2. 10*10G signal source pattern generator according to claim 1, is characterized in that, also includes the Single-chip Controlling unit that the signal element generation unit is controlled.
3. 10*10G signal source pattern generator according to claim 2, is characterized in that, is provided with level transferring chip between described signal element generation unit and Single-chip Controlling unit.
4. 10*10G signal source pattern generator according to claim 3, is characterized in that, described Single-chip Controlling unit also connects external equipment.
5. 10*10G signal source pattern generator according to claim 2, is characterized in that, also includes voltage source unit, and described voltage source unit is connected with the Single-chip Controlling unit with signal element generation unit, clock signal output unit respectively.
6. 10*10G signal source pattern generator according to claim 1, is characterized in that, described signal element generation unit comprises:
Recovering clock signals is become the clock data recovery device of clock; And
External signal is demultiplexed into the demodulation multiplexer of 10 road 10Gbps data-signals.
7. 10*10G signal source pattern generator according to claim 1, is characterized in that, the clock signal of described clock signal output unit output is variable clock signal, and the output speed of described clock signal output unit is 622M-697M.
8. 10*10G signal source pattern generator according to claim 7, is characterized in that, the output speed of described signal output unit is 16 times of clock signal output unit output speed.
9. 10*10G signal source pattern generator according to claim 1, is characterized in that, described external signal is 4 road 28.3Gbps serial data bit streams.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105281714A (en) * | 2015-11-10 | 2016-01-27 | 华东师范大学 | Square wave generating device and method capable of editing code element |
| CN106059723A (en) * | 2016-08-03 | 2016-10-26 | 索尔思光电（成都）有限公司 | Signal source, error code tester, signal generation method and error code test method |
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| CN1317187A (en) * | 1999-07-06 | 2001-10-10 | 三星电子株式会社 | Rate matching device and method for data communication system |
| CN1761181A (en) * | 2005-11-04 | 2006-04-19 | 清华大学 | Device for testing time characteristic of outburst and error rate in outburst optical fiber transmission system |
| CN102833004A (en) * | 2012-08-23 | 2012-12-19 | 武汉电信器件有限公司 | 100G form-factor pluggable (CFP) optical module with transmission distance larger than 40 kilometers |
| CN102882592A (en) * | 2012-09-26 | 2013-01-16 | 烽火通信科技股份有限公司 | 2M optical signal transparent transmission device and 2M optical signal transparent transmission method applied to SDH (synchronous digital hierarchy) network |
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2013
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1317187A (en) * | 1999-07-06 | 2001-10-10 | 三星电子株式会社 | Rate matching device and method for data communication system |
| CN1761181A (en) * | 2005-11-04 | 2006-04-19 | 清华大学 | Device for testing time characteristic of outburst and error rate in outburst optical fiber transmission system |
| CN102833004A (en) * | 2012-08-23 | 2012-12-19 | 武汉电信器件有限公司 | 100G form-factor pluggable (CFP) optical module with transmission distance larger than 40 kilometers |
| CN102882592A (en) * | 2012-09-26 | 2013-01-16 | 烽火通信科技股份有限公司 | 2M optical signal transparent transmission device and 2M optical signal transparent transmission method applied to SDH (synchronous digital hierarchy) network |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105281714A (en) * | 2015-11-10 | 2016-01-27 | 华东师范大学 | Square wave generating device and method capable of editing code element |
| CN105281714B (en) * | 2015-11-10 | 2018-09-04 | 华东师范大学 | A kind of square-wave device and method of editable symbol |
| CN106059723A (en) * | 2016-08-03 | 2016-10-26 | 索尔思光电（成都）有限公司 | Signal source, error code tester, signal generation method and error code test method |
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Application publication date: 20130619 |
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