CN218825512U - Embedded logic analyzing system, logic device, and device analyzing apparatus - Google Patents

Abstract

The embodiment of the application discloses an embedded logic analysis system, a corresponding logic device and device analysis equipment. The embedded logic analysis system comprises: the SPI interface comprises an SPI interface input/output circuit, a configuration control circuit, a test access port control circuit and a logic analysis circuit; the SPI interface input and output circuit comprises a serial shift clock signal end, a chip selection signal end, a master input slave output signal end, a master output slave input signal end and a plurality of selectors; the configuration control circuit is connected with the control ends of the selectors; the test access port control circuit is connected with the serial shift clock signal end, the chip selection signal end, the master input slave output signal end and the master output slave input signal end through a plurality of selectors; the logic analysis circuit is connected with the test access port control circuit. According to the embodiment of the application, the slave SPI interface is adopted, the JTAG interface is not used as a test access port, loading and function debugging are carried out by means of the slave SPI interface, IO resources can be saved, and a part of hardware design can be simplified.

Description

Embedded logic analyzing system, logic device, and device analyzing apparatus

Technical Field

The present application relates to the field of integrated circuit technology, and in particular, to an embedded logic analysis system, a logic device, and a device analysis apparatus.

Background

An embedded Logic Analyzer of a Logic device having a boundary scan function, such as an FPGA (Field Programmable Gate Array) device, is an important tool for developing and debugging the FPGA device, and samples internal signals or IO (Input Output) states of the FPGA device in real time at a preset clock frequency, stores the internal signals or IO (Input Output) states in a RAM (Random Access Memory) inside the FPGA device, and then performs data analysis and processing through a Logic Analyzer (LA). When the preset trigger condition is satisfied, the logic analysis circuit transmits the data cache stored in the internal RAM to a PC (Personal Computer) through a Joint Test Action Group (JTAG) interface. And after the PC obtains the JTAG interface return data, displaying the corresponding logic analysis result through local calculation.

Currently, the data acquisition and reporting of an embedded logic analyzer of an FPGA device are completed through JTAG. JTAG includes a Test Access Port, a Boundary Scan Cell (Boundary Scan Cell), a Test Access Port Controller (Test Access Port Controller), an Instruction Register (IR), a Test Data Register (TDR), and the like. The test access port is a conventional JTAG interface, and generally includes a test clock input (TCK) pin, a test mode select input (TMS) pin, a Test Data Output (TDO) pin, and a Test Data Input (TDI) pin, and further includes an optional test reset input (TRST) pin.

The JTAG interface is generally used in the development, debugging and maintenance phases, and mostly exists on a multi-IO device, but for a mature FPGA product, it is a waste to use the JTAG interface.

Disclosure of Invention

Therefore, in order to save IO resources, embodiments of the present application provide an embedded logic analysis system, a logic device, and a device analysis apparatus.

An embedded logic analysis system provided by the embodiment of the application comprises: the SPI interface comprises an SPI interface input/output circuit, a configuration control circuit, a test access port control circuit and a logic analysis circuit; the SPI interface input and output circuit comprises a serial shift clock signal end, a chip selection signal end, a master input slave output signal end, a master output slave input signal end and a plurality of selectors; the configuration control circuit is connected with the control ends of the selectors; the test access port control circuit is connected with the serial shift clock signal end, the chip selection signal end, the master input slave output signal end and the master output slave input signal end through the plurality of selectors; the logic analysis circuit is connected with the test access port control circuit.

Further, the plurality of selectors include four one-out-of-two selectors, the test access port control circuit includes a test clock input terminal, a test mode selection input terminal, a test data output terminal, and a test data input terminal, and the test clock input terminal, the test mode selection input terminal, the test data output terminal, and the test data input terminal are respectively connected to the serial shift clock signal terminal, the chip select signal terminal, the master input slave output signal terminal, and the master output slave input signal terminal through the four one-out-of-two selectors.

Further, the test access port control circuit includes a test access port controller, an instruction register, and a test data register, where the test access port controller is connected to the test clock input terminal and the test mode selection input terminal, and the instruction register and the test data register are connected to the test access port controller and to the test data output terminal and the test data input terminal.

Further, the test data register includes a bypass register and an identification register, the bypass register is connected to the test data output terminal and the test data input terminal, and the identification register is connected to the test data output terminal and the test data input terminal.

In another aspect, a logic device provided in an embodiment of the present application includes: the system comprises an embedded logic analysis system, a configuration memory and a pin group; the embedded logic analysis system comprises: the SPI interface comprises an SPI interface input/output circuit, a configuration control circuit, a test access port control circuit and a logic analysis circuit; the SPI interface input-output circuit comprises a serial shift clock signal end, a chip selection signal end, a master input slave output signal end, a master output slave input signal end and a plurality of selectors, the configuration control circuit is connected with control ends of the selectors, the test access port control circuit is connected with the serial shift clock signal end, the chip selection signal end, the master input slave output signal end and the master output slave input signal end through the selectors, and the logic analysis circuit is connected with the test access port control circuit; the configuration memory is connected with the serial shift clock signal terminal, the chip selection signal terminal, the master input slave output signal terminal and the master output slave input signal terminal through the plurality of selectors, and is used for storing the function configuration information of the logic unit of the logic device; the pin group is connected with the serial shift clock signal end, the chip selection signal end, the main input and slave output signal end and the main output and slave input signal end.

Further, the plurality of selectors include four one-out-of-two selectors, the test access port control circuit includes a test clock input terminal, a test mode selection input terminal, a test data output terminal, and a test data input terminal, and the test clock input terminal, the test mode selection input terminal, the test data output terminal, and the test data input terminal are respectively connected to the serial shift clock signal terminal, the chip select signal terminal, the master input slave output signal terminal, and the master output slave input signal terminal through the four one-out-of-two selectors.

Further, the test access port control circuit includes a test access port controller, an instruction register, and a test data register, where the test access port controller is connected to the test clock input terminal and the test mode selection input terminal, and the instruction register and the test data register are connected to the test access port controller and to the test data output terminal and the test data input terminal.

Further, the test data register includes a bypass register and an identification register, the bypass register is connected to the test data output terminal and the test data input terminal, and the identification register is connected to the test data output terminal and the test data input terminal.

Further, the logic device is a field programmable gate array device.

In another aspect, a device analysis apparatus provided in an embodiment of the present application includes: an upper computer, a converter, and the logic device of any of the foregoing embodiments; the upper computer is connected with the converter through a USB interface, and the converter is connected with the pin group.

According to the embedded logic analysis system, the logic device and the device analysis equipment provided by the embodiment of the application, the slave SPI interface is adopted instead of the JTAG interface as a test access port, 4 IOs of the JTAG interface are not led out in packaging or even are not designed on hardware, and loading and function debugging are carried out by means of the slave SPI interface; the SPI interface can load logic devices such as FPGA devices, and can capture and analyze waveforms, so that IO resources can be saved, and part of hardware design can be simplified.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments, not all embodiments, of the present application. All other embodiments and drawings obtained by a person skilled in the art based on the embodiments of the present application without inventive step are within the scope of the present application.

Fig. 1 is a block diagram of an embedded logic analysis system according to an embodiment of the present disclosure.

Fig. 2 is a schematic diagram of an internal structure of the TAPC in the embedded logic analysis system shown in fig. 1.

Fig. 3 is a schematic architecture diagram of a device analysis apparatus according to an embodiment of the present application.

Fig. 4 is a timing diagram of power-on loading of a logic device and a state change diagram of cfgmode according to an embodiment of the present application.

Fig. 5 is a schematic diagram of a state jump of the state machine of the TAPC in the embedded logic analysis system shown in fig. 1.

Fig. 6 is a timing diagram of an interface of the TAPC in the embedded logic analysis system shown in fig. 1.

Fig. 7 is a schematic diagram of a connection relationship between TAPC and LA in the embedded logic analysis system shown in fig. 1.

Detailed Description

The technical solutions provided by the embodiments of the present application are further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the present application.

Specifically, some FPGA items do not select the JTAG Interface for loading, but select other loading interfaces, such as a Slave Serial Peripheral Interface (Slave Serial Peripheral Interface), which includes a Serial shift clock signal terminal SCLK, a chip select signal terminal CS, a master-input Slave-output signal terminal MISO, and a master-output Slave-input signal terminal MOSI. In order to fully utilize the slave SPI interface and save IO resources, 4 IOs of the JTAG interface are not led out in a package or even are not designed on hardware, and the slave SPI interface is used for loading and function debugging, so that the slave SPI interface is used as an interface of the embedded logic analysis system to become a new solution. The FPGA device can be loaded from the SPI interface, and the waveform can be captured and analyzed, so that IO (input/output) resources can be saved, and part of hardware design can be simplified.

In view of the above, the embedded logic analysis system using the slave SPI interface does not use the JTAG interface as the test access port, but a test access port control circuit including a test access port controller, an instruction register, and a test data register is necessary. In logic devices such as FPGA device hardware, each IO circuit needs to support a boundary scan cell, which has become a standard configuration of the FPGA device; the test access port controller, instruction register and test data register may then be implemented in logic code. Boundary Scan cells herein generally refer to a shift Register placed between the Internal Logic (Internal Logic) of the IC and each Pin (Pin), which allows the user to control and observe each IO state, and which are connected together to form a Boundary Scan Register (BSR).

The slave SPI interface replaces the JTAG interface as a test access port, which needs to be designed as a multiplexed IO. After the FPGA device is powered on, the FPGA device can be in two states, namely a loading state and a user state. When the FPGA device is in a loadable state, a user can load data streams to the FPGA device through the SPI interface so as to realize corresponding functions, and at the moment, 4 IOs of the SPI interface are used as special configuration IOs; after the data stream is loaded, the FPGA device enters a user state, the FPGA device is endowed with functions expected by a user, and in order to realize a debugging function, 4 IOs of the SPI interface are used as user IOs, so that the logic function of the control circuit of the test access port is adapted.

The test access port control circuit is a bridge connecting the slave SPI interface and the logic analysis circuit. Inside the control circuit of the test access port, the JTAG protocol is still followed, and various timings and modes required by the transformation of TMS signal are selected according to the test clock TCK and the test mode, the Instruction Register (IR) and the Test Data Register (TDR) are output, and the control signals for capturing, shifting and updating the IR and TDR are generated. The instruction register is used for receiving and decoding an instruction and generating a control signal; the test data registers are placed on the Test Data Input (TDI) to Test Data Output (TDO) scan chains and control the load sources and drive targets of the test data registers. The test data Register contains a series of registers that use, for example, an identification Register (IDCODE Register) and a BYPASS Register (BYPASS Register) in-line logic analysis system.

In order to make the embedded logic analyzing system, the logic device, and the device analyzing apparatus of the embodiments of the present application more clearly understood, the following description will be made in more detail with reference to fig. 1 to 7.

As shown in fig. 1, an embedded logic analysis system 110 according to an embodiment of the present application includes: an SPI interface input output circuit 111, a configuration control circuit CCS, a test access port control circuit TAPC, and a logic analysis circuit LA.

The SPI input/output circuit 111 includes a serial shift clock signal terminal SCLK, a chip select signal terminal CS, a master-input slave-output signal terminal MISO, a master-output slave-input signal terminal MOSI, and a plurality of selectors 112. The configuration control circuit CCS is connected to control terminals of the plurality of selectors 112. The test access port control circuit TAPC is connected to the serial shift clock signal terminal SCLK, the chip select signal terminal CS, the master-input-slave-output signal terminal MISO, and the master-output-slave-input signal terminal MOSI through the plurality of selectors 112. The logic analysis circuit LA is connected to the test access port control circuit TAPC.

More specifically, the plurality of selectors 112 include four one-out-of-two selectors, and the test access port control circuit TAPC includes a test clock input terminal TCK, a test mode selection input terminal TMS, a test data output terminal TDO, and a test data input terminal TDI, which are respectively connected to the serial shift clock signal terminal SCLK, the chip select signal terminal CS, the master-input slave-output signal terminal MISO, and the master-output slave-input signal terminal MOSI through the four one-out-of-two selectors.

As shown in fig. 2, test access port control circuit TAPC comprises, for example, a test access port controller connected to test clock input TCK and test mode select input TMS, an instruction register and a test data register connected to the test access port controller and to test data output TDO and test data input TDI. Further, the test data registers include, for example, a bypass register connecting the test data output terminal TDO and the test data input terminal TDI, and an identification register connecting the test data output terminal TDO and the test data input terminal TDI.

As shown in fig. 1 and 3, a device analysis apparatus provided in an embodiment of the present application includes: a logic device 11, a converter 13 and an upper computer 15.

The logic device 11 includes the embedded logic analysis system 110, the configuration memory CRAM, and the pin group 113. The configuration memory CRAM is connected to the serial shift clock signal terminal SCLK, the chip select signal terminal CS, the master-input slave-output signal terminal MISO, and the master-output slave-input signal terminal MOSI through a plurality of selectors 111, and the configuration memory CRAM includes, for example, a plurality of configuration storage units, which are distributed in each logic unit of the logic device 11, for example, the FPGA device, and store the function configuration information of each logic unit, and configure the logic units into the functions desired by the user. The pin set 113 includes, for example, four pins, which are connected to the serial shift clock signal terminal SCLK, the chip select signal terminal CS, the master-input slave-output signal terminal MISO, and the master-output slave-input signal terminal MOSI of the embedded logic analysis system 110. Converter 13 is, for example, a USB-SPI converter, which is connected to pin set 113 via an SPI interface. The host computer 15 is connected to the converter 13, which is a Personal Computer (PC), for example, via a USB interface.

More specifically, as can be seen from fig. 3, in one embodiment of the present application, 4 IO cells of SPI input output circuit 111 are designed to multiplex IO. Each IO unit is additionally provided with a control terminal for receiving a control signal cfgmode, and the control terminal is used for controlling a serial shift clock signal terminal SCLK, a chip select signal terminal CS, a main input and slave output signal terminal MISO and a main output and slave input signal terminal MOSI to be used as a special IO or a user IO. The power-up load timing diagram and the state change of cfgmode for a logic device 11, such as an FPGA device, are shown in fig. 4, for example. The signal description in fig. 4 is tabulated as follows:

the general workflow of an FPGA device includes powering up (omitted from fig. 4), initializing, loading a data stream, waking up, and entering a user state. For user IO, after glen is pulled high, the glen is output by logic driving; the multiplexing IO, such as SCLK, CS, MOSI, and MISO, is controlled by cfgmode.

In a certain design, before the FPGA device enters a user state, cfgmode may be always low, and at this time, 4 IO units of the SPI input/output circuit 111 are all used as dedicated configuration IO, and are connected to the configuration memory CRAM through the alternative selector to load the configuration memory CRAM; when the data stream is loaded and the data stream enters the wake-up stage, the state signals are pulled up one by one, and when the external signal DONE is not pulled down artificially, the cfgmode is also pulled up accordingly, and 4 IO units of the SPI input and output circuit 111 are connected with the test access port control circuit TAPC through the alternative selector, so that the functions of waveform acquisition and analysis are realized.

In another design, cfgmode may be assigned an arbitrary value by overwriting a register in the configuration control circuit CCS, the value of this register being readable by the configuration control circuit CCS during the initialization phase; there may then be a combination of:

	configurable state	User status
			Combination
1	cfgmode =0, spi interface as dedicated IO	cfgmode =0, spi interface as dedicated IO
			Combination 2	cfgmode =0, spi interface as dedicated IO	cfgmode =1,spi interface as user IO
Combination 3	cfgmode＝1, SPI interface as user IO	cfgmode =0, spi interface as dedicated IO
			Combination 4	cfgmode =1,spi interface as user IO	cfgmode =1,spi interface as user IO

In the exemplary embodiment of the present application, combination 2 is used.

As mentioned above, the test access port control circuit TAPC contains, for example, an Instruction Register (IR), a Test Data Register (TDR), and 1 synchronous finite state machine (corresponding to the test access port controller) for generating data and control signals for interaction with the logic analysis circuit LA. The logic analysis circuit LA returns data according to the received different status indication signals, and the test access port control circuit TAPC receives the data returned by the logic analysis circuit LA, and reports the data to the upper computer 15, such as a PC, through the SPI input/output circuit 111. The state machine of the test access port control circuit TAPC typically contains 3 basic actions: stimulus (data update state), execute (test/idle state), response (data capture state). The different types of instructions are subsets of these 3 actions. The state jumps of the state machine are shown in figure 5.

(1) Test-Logic-Reset Test Logic Reset state

In this state, the test logic is disabled to allow normal operation of the chip and reading the identification register disables the test logic. Regardless of the state of the Test access port controller, the Test access port controller will enter the Test-Logic-Reset state as long as the TMS signal is held high at a rising edge of 5 consecutive TCK signals by "1", and will remain in the Test-Logic-Reset state if the TMS signal is always high. And if the TMS signal is at low level 0 at the rising edge of the next TCK signal, the Test access port controller in the Test-Logic-Reset state is switched to a Run-Test-Idle state.

(2) Run-Test/Idle Run Test Idle state

Run-Test/Idle is the Idle state of the scan operation of the Test access port controller, and if the TMS signal is always at a low level, the Test access port controller will remain in the Run-Test/Idle state. When the TMS signal is at a high level on the rising edge of the TCK signal, the test access port controller will enter the Select-DR-Scan state.

(3) Select-DR-Scan Select data register Scan State

Select-DR-Scan is a temporary state of the test access port controller, and the Boundary Scan Register (BSR) maintains its previous state. When the TMS signal is at low level at the next rising edge of the TCK signal, the test access port controller enters a Capture-DR state, and the scanning operation of a boundary scan register is initialized at the same time. If the TMS signal is high on the next rising TCK signal edge, the test access port controller will enter the Select-IR-Scan state.

(4) Capture-DR Capture data register State

If the test access port controller is in the Capture-DR state and the current instruction is a SAMPLE/PRELOAD instruction, the Boundary Scan Register (BSR) captures data at the input on the rising edge of the TCK signal. If it is not a SAMPLE/PRELOAD instruction at this time, the Boundary Scan Register (BSR) holds its previous value and the value of the Boundary Scan Register (BSR) is additionally placed in a shift register connected between TDI and TDO. In the Capture-DR state, the instruction is not changed. If the TMS signal is at a high level at the next rising edge of the TCK signal, the test access port controller enters the Exit1-DR state. If the TMS signal is at a low level on the next rising edge of the TCK signal, the test access port controller enters the Shift-DR state.

(5) Shift-DR Shift data register State

In the Shift-DR state, at each rising edge of the TCK signal, the TDI-Shift register-TDO serial channel shifts to the right by one bit, the data of TDI shifts into the Shift register, and the Shift register shifts onto TDO closest to TDO. In the Shift-DR state, the instruction is not changed. If the TMS signal is at a high level at the next rising edge of the TCK signal, the test access port controller enters the Exit1-DR state. If the TMS signal is at a low level, the test access port controller always performs a shift operation.

(6) Exit1-DR Exit data register State 1

Exit1-DR is a temporary state of the test access port controller, and if the TMS signal is at a high level at the rising edge of the next TCK signal, the test access port controller enters an Update-DR state; if the TMS signal is at a low level on the next rising edge of the TCK signal, the test access port controller enters the Pause-DR state. In the Exit1-DR state, the instruction is not changed.

(7) Pause data register state for Pause-DR

The Pause-DR state allows the test access port controller to temporarily halt the shift operation of the TDI-shift register-TDO serial channel. In the Pause-DR state, the instruction is not changed. If the TMS signal is at a high level at the rising edge of the next TCK signal, the test access port controller enters an Exit2-DR state; if the TMS signal is at a low level, the test access port controller remains in a suspended state.

(8) Exit2-DR Exit data register State 2

The Exit2-DR is also a temporary state of the test access port controller, if the TMS signal is at a high level at the rising edge of the next TCK signal, the test access port controller enters an Update-DR state, and the scanning operation is finished; if the TMS signal is at a low level on the next rising TCK signal edge, the test access port controller reenters the Shift-DR state. In the Exit2-D state, the instruction is not changed.

(9) Update-DR data register State

Under normal conditions, the value of the Boundary Scan Register (BSR) is latched in the parallel output pins to avoid changing the value of the Boundary Scan Register (BSR) when a shift operation is performed under the EXTEST or SAMPLE/PRELOAD command. When the boundary scan register is selected when in the Update-DR state, the value in the shift register will be latched into the parallel output pin of the boundary scan register on the falling edge of the TCK signal. In the Update-DR state, the instruction is not changed. If the TMS signal is at a high level at the rising edge of the next TCK signal, the test access port controller enters a Select-DR-Scan state; if the TMS signal is at a low level on the next rising edge of the TCK signal, the Test access port controller enters a Run-Test/Idle state.

(10) Select-IR-Scan Select instruction register Scan State

Select-IR-Scan is a temporary state of the test access port controller. If the TMS signal is at a low level on the next rising edge of the TCK signal, the test access port controller enters the Capture-IR state and a scan operation to the command register is simultaneously initiated. If the TMS signal is at a high level on the next rising edge of the TCK signal, the Test access port controller will enter the Test-Logic-Reset state. In the Select-IR-Scan state, the instruction is not changed.

(11) Capture-IR Capture instruction register State

In the Capture-IR state, the value in the instruction register is fixed set to 0b0000001 and put into a shift register connected between TDI and TDO. In the Capture-DR state, the instruction is not changed. If the TMS signal is at a high level at the rising edge of the next TCK signal, the test access port controller enters an Exit1-IR state; if the TMS signal is low on the next rising TCK signal edge, the test access port controller enters the Shift-IR state.

(12) Shift-IR Shift instruction register State

In the Shift-IR state, on each rising edge of the TCK signal, the TDI-Shift register-TDO serial channel shifts one bit to the right, instructions are shifted bit-by-bit from TDI into the Shift register, and 0b0000001 in the Shift register is shifted bit-by-bit from TDO. In the Shift-IR state, the instruction is not changed. If the TMS signal is at a high level at the rising edge of the next TCK signal, the test access port controller enters an Exit1-IR state; if the TMS signal is at a low level, the test access port controller always performs a shift operation.

(13) Exit1-IR Exit instruction register State 1

The Exit1-IR is a temporary state of the test access port controller, and if the TMS signal is at a high level at the rising edge of the next TCK signal, the test access port controller enters an Update-IR state; if the TMS signal is low on the next rising TCK signal edge, the test access port controller enters the Pause-IR state. In the Exit1-IR state, the instruction is not changed.

(14) Pause-IR instruction register State

The Pause-IR state allows the test access port controller to temporarily halt the shift operation of the TDI-shift register-TDO serial channel. In the Pause-IR state, the instruction is not changed. If the TMS signal is at a high level at the rising edge of the next TCK signal, the test access port controller enters an Exit2-IR state; if the TMS signal is at a low level, the test access port controller is always in a suspended state.

(15) Exit2-IR Exit instruction register State 2

The Exit2-IR is also a temporary state of the test access port controller, if the TMS signal is at a high level at the rising edge of the next TCK signal, the test access port controller enters an Update-IR state, and the scanning operation is finished; if the TMS signal is at low level on the next rising edge of the TCK signal, the test access port controller re-enters the Shift-IR state. In the Exit2-D state, the instruction is not changed.

(16) Update instruction register state with Update-IR

In the Update-IR state, the value in the shift register will be latched into the instruction register on the falling edge of the TCK signal, and once latched successfully, the new instruction will become the current instruction. If the TMS signal is at a high level at the rising edge of the next TCK signal, the test access port controller enters a Select-DR-Scan state; if the TMS signal is at a level on the next rising edge of the TCK signal, the Test access port controller enters a Run-Test/Idle state.

As can be seen from fig. 5, this state machine is divided into 3 columns corresponding to a reset operation, a test data register operation and an instruction register operation. The data on the state switch line is the TMS signal level. On the rising edge of the TCK signal, the state of the test access port controller is switched; loading test data of TDI at the rising edge of the TCK signal; on the falling edge of the TCK signal, the test data output is sent to TDO. An interface timing chart of the test access port control circuit TAPC is shown in fig. 6, for example.

Fig. 7 shows an example of the connection relationship between the test access port control circuit TAPC and the logic analysis circuit LA. The signal description in fig. 7 is tabulated as follows: :

signal name	I/O	Description of the Signal
			jrst	O	Reset signal to LA, high active
capturedr	O	Indication signal in Capture-DR state, high indicates that the state machine jumps to this state
			shiftdr	O	An indication signal in the Shift-DR state, high indicates that the state machine jumps to the state
updatedr	O	UpdaIndication signal in te-DR state, high indicating state machine jumping to this state
			sel	O	Chip select signal of LA, high effective
tdo_user	I	Data returned by LA

The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the embodiments of the present application, and they should be construed as being included in the present application.

Claims (10)

1. An embedded logic analysis system, comprising: the SPI interface comprises an SPI interface input/output circuit, a configuration control circuit, a test access port control circuit and a logic analysis circuit;

the SPI interface input and output circuit comprises a serial shift clock signal end, a chip selection signal end, a master input slave output signal end, a master output slave input signal end and a plurality of selectors;

the configuration control circuit is connected with the control ends of the selectors;

the test access port control circuit is connected with the serial shift clock signal end, the chip selection signal end, the master input slave output signal end and the master output slave input signal end through the plurality of selectors;

the logic analysis circuit is connected with the test access port control circuit.

2. The embedded logic analysis system of claim 1, wherein the plurality of selectors comprises four alternative selectors; the test access port control circuit comprises a test clock input end, a test mode selection input end, a test data output end and a test data input end; the test clock input end, the test mode selection input end, the test data output end and the test data input end are respectively connected with the serial shift clock signal end, the chip selection signal end, the master input slave output signal end and the master output slave input signal end through the four alternative selectors.

3. The embedded logic analysis system of claim 2, wherein the test access port control circuitry includes a test access port controller, an instruction register, and a test data register, the test access port controller coupled to the test clock input and the test mode select input, the instruction register and the test data register coupled to the test access port controller and to the test data output and the test data input.

4. The embedded logic analysis system of claim 3, wherein the test data register includes a bypass register and an identification register, the bypass register connecting the test data output and the test data input, the identification register connecting the test data output and the test data input.

5. A logic device, comprising: the system comprises an embedded logic analysis system, a configuration memory and a pin group;

the embedded logic analysis system comprises: the SPI interface comprises an SPI interface input/output circuit, a configuration control circuit, a test access port control circuit and a logic analysis circuit;

the SPI interface input-output circuit comprises a serial shift clock signal end, a chip selection signal end, a master input slave output signal end, a master output slave input signal end and a plurality of selectors, the configuration control circuit is connected with control ends of the selectors, the test access port control circuit is connected with the serial shift clock signal end, the chip selection signal end, the master input slave output signal end and the master output slave input signal end through the selectors, and the logic analysis circuit is connected with the test access port control circuit;

the configuration memory is connected with the serial shift clock signal terminal, the chip selection signal terminal, the master input slave output signal terminal and the master output slave input signal terminal through the plurality of selectors, and is used for storing the function configuration information of the logic unit of the logic device;

the pin group is connected with the serial shift clock signal end, the chip selection signal end, the main input and slave output signal end and the main output and slave input signal end.

6. The logic device of claim 5, wherein the plurality of selectors comprises four one-out-of-two selectors, the test access port control circuit comprises a test clock input, a test mode select input, a test data output, and a test data input, the test clock input, the test mode select input, the test data output, and the test data input are respectively connected to the serial shift clock signal terminal, the chip select signal terminal, the master input slave output signal terminal, and the master output slave input signal terminal through the four one-out-of-two selectors.

7. The logic device of claim 6, wherein the test access port control circuitry includes a test access port controller, an instruction register, and a test data register, the test access port controller connecting the test clock input and the test mode select input, the instruction register and the test data register connecting the test access port controller and connecting the test data output and the test data input.

8. The logic device of claim 7, wherein the test data register includes a bypass register and an identification register, the bypass register connecting the test data output and the test data input, the identification register connecting the test data output and the test data input.

9. A logic device as claimed in any one of claims 5 to 8, wherein the logic device is a field programmable gate array device.

10. A device analysis apparatus, comprising: an upper computer, a converter, and a logic device according to any one of claims 5 to 9; the upper computer is connected with the converter through a USB interface, and the converter is connected with the pin group.

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