CN101865976A - Boundary scanning test system and test method - Google Patents
Boundary scanning test system and test method Download PDFInfo
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- CN101865976A CN101865976A CN200910301527A CN200910301527A CN101865976A CN 101865976 A CN101865976 A CN 101865976A CN 200910301527 A CN200910301527 A CN 200910301527A CN 200910301527 A CN200910301527 A CN 200910301527A CN 101865976 A CN101865976 A CN 101865976A
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Abstract
The invention discloses a boundary scanning test system, which comprises test equipment, an external interface, a microprocessor, a gating circuit, a plurality of I/O (Input/Output) driving interfaces and a plurality of JTAG (Joint Test Action Group) bus interfaces used for connecting devices to be tested. The test equipment is connected with the microprocessor through the external interface, the microprocessor is connected with the plurality of I/O driving interfaces through the gating circuit, each I/O driving interface is correspondingly connected with one JTAG bus interface, and the microprocessor is connected with the plurality of I/O driving interfaces. The invention also provides a boundary scanning test method. The boundary scanning test system and the boundary scanning test method can simultaneously test a plurality of devices to be tested so as to improve the test efficiency.
Description
Technical field
The present invention relates to the electronic equipment field tests, particularly a kind of test macro and method of testing of printed circuit board (PCB) being tested by JTAG (Joint Test Action Group, joint test behavior tissue) technology.
Background technology
At present, usually need the hardware of printed circuit board (PCB) is tested, to judge whether chip on the printed circuit board (PCB) is qualified, whether damage or to occur machining failure for example short circuit or rosin joint etc. in the integrated circuit testing field of electronic equipment.Boundary scan testing is a kind of important integrated circuit testing means, its general JTAG technology that adopts is tested the chip on the printed circuit board (PCB), and ultimate principle is by the jtag interface that visit is arranged on the printed circuit board (PCB) internal node of printed circuit board (PCB), device etc. to be tested.
But general boundary scan and test system mostly passes through the parallel interface or PCI (the Peripheral ComponentInterconnect of computing machine, peripheral component interconnection) interface etc. links to each other with transceive data with printed circuit board (PCB), thereby makes test speed slower.On the other hand, present test macro often has only drive test examination bus, once can only connect single printed circuit board tests, can not carry out the test of many printed circuit board (PCB)s simultaneously, when to many printed circuit board tests, will spend the more test duration or need to buy more testing apparatus.
Summary of the invention
In view of above content, be necessary to provide a kind of boundary scan and test system and method for testing that improves testing efficiency.
A kind of boundary scan and test system, comprise a testing apparatus, a Peripheral Interface, a microprocessor, a gating circuit, some I/O driving interface and some jtag bus interfaces that is used for interface unit, described testing apparatus links to each other with described microprocessor by described Peripheral Interface, described microprocessor links to each other with described some I/O driving interface by described gating circuit, the corresponding jtag bus interface that connects of each I/O driving interface, described microprocessor also links to each other with described some I/O driving interface; Described testing apparatus setting also sends test instruction and test data and send described microprocessor to by described Peripheral Interface, described microprocessor is to described test instruction and test data is resolved and be the test instruction and the test data of JTAG form with described test instruction and test data conversion, and control the I/O driving interface that described gating circuit gating links to each other with described device and be in effective status, described microprocessor is by the I/O driving interface of effective status, the jtag bus interface that is driven by described I/O driving interface carries out boundary scan testing to device, the test results of devices index was by corresponding jtag bus interface after test was finished, the I/O driving interface sends described microprocessor to, and described microprocessor sends the test result index to described testing apparatus by Peripheral Interface.
A kind of boundary scanning test method, whether qualified, may further comprise the steps if being used to test at least one measured device:
One testing apparatus sends test instruction and test data to a microprocessor by a Peripheral Interface;
Described microprocessor is resolved test instruction and test data, and be the test instruction and the test data of JTAG form with test instruction and test data conversion, control the I/O driving interface that a gating circuit gating links to each other with the institute test component and be in effective status, by the I/O driving interface of effective status, the jtag bus interface that is driven by the I/O driving interface measured device is carried out boundary scan testing again;
When test was finished, described microprocessor was by the I/O driving interface of effective status, the test result index that the jtag bus interface receives measured device;
Described microprocessor sends the test result index to described testing apparatus by described Peripheral Interface; And
Described testing apparatus is compared the default normal index of test result index and described measured device, if the test result index equates with the normal index of presetting of measured device, it is qualified then to be judged as measured device, otherwise it is defective then to be judged as measured device.
Boundary scan and test system of the present invention and method of testing send test instruction and test data to described microprocessor by described testing apparatus, described microprocessor is controlled I/O driving interface that described gating circuit gating links to each other with described measured device and measured device is carried out boundary scan testing according to described test instruction and test data, the test result index of measured device sent described microprocessor to and sends described testing apparatus again to after test was finished, testing apparatus compares the default normal index of test result index and described measured device to judge whether measured device is qualified, thereby realize carrying out simultaneously the test of many printed circuit board (PCB)s, improve testing efficiency, saved the time of test.
Description of drawings
Fig. 1 is the module map that the better embodiment of boundary scan and test system of the present invention links to each other with some measured devices.
Fig. 2 is the process flow diagram of the better embodiment of boundary scanning test method of the present invention.
Embodiment
Please refer to Fig. 1, whether boundary scan and test system 10 of the present invention is used to test some measured device 112 qualified, its better embodiment comprises for example for example usb 1 02, a microprocessor 104, a gating circuit 106, some I/O (Input/Output, I/O) driving interface 108 and some jtag bus interface 110 of computing machine 100, a Peripheral Interface of a testing apparatus.Described measured device 112 is for supporting the printed circuit board (PCB) of JTAG technology.Described gating circuit 106 can comprise one or more gating chips, and to realize the multi channel selecting function, concrete quantity can be tested the quantity of measured device 112 according to actual needs and be set.
Described computing machine 100 links to each other with described microprocessor 104 by described usb 1 02, described microprocessor 104 also links to each other with described some I/O driving interface 108 by described gating circuit 106, described microprocessor 104 also links to each other with described some I/O driving interface 108, each I/O driving interface 108 a corresponding jtag bus interface 110, measured device 112 of each jtag bus interface 110 corresponding connection of connecting.Described boundary scan and test system 10 can be tested a plurality of measured devices 112 simultaneously, specifically can decide according to test request.For example described jtag bus interface 110 can connect one or more measured devices 112 to be tested.
Described computing machine 100 is used to be provided with test instruction (for example testing which measured device 112) and test data (is for example tested the level of certain node of measured device 112, the function of pin, parameter informations such as the model of chip), after setting is finished described test instruction and test data are sent to described microprocessor 104 by usb 1 02, also be used for receiving from described microprocessor 104 the test result index of measured device 112 by usb 1 02, and the storage and the index that shows test results, compare test is the default normal index of index and measured device 112 as a result, if the test result index equates with the default normal index of measured device 112, it is qualified then to be judged as measured device 112, otherwise it is defective then to be judged as measured device 112.When the level of the node of the measured device of for example being tested 112 was high level, the test result index can be with 1 expression.
Described microprocessor 104 is used for described test instruction and test data are resolved and be converted into the test instruction and the test data of JTAG form, also be used to control the road I/O driving interface 108 that described gating circuit 106 gatings link to each other with measured device 112 and be in effective status, also be used for I/O driving interface 108 by effective status, the 110 pairs of measured devices of jtag bus interface 112 that driven by the I/O driving interface 108 of effective status carry out boundary scan testing, and after finishing, test receives measured device 112 by jtag bus interface 110, the test result index that the I/O driving interface 108 of effective status transmits, and send the test result index to described computing machine 100 by usb 1 02.
When the some measured device 112 of boundary scan and test system 10 test, need some measured devices 112 are plugged in different jtag bus interfaces 110 respectively, described computing machine 100 settings and transmission test instruction (for example testing some measured devices 112) and test data (are for example tested the node A of some measured devices 112, the level of B) sends described microprocessor 104 to by described usb 1 02, the test instruction and the test data of JTAG form resolved and be converted into to 104 pairs of described test instructions of described microprocessor and test data, control described gating circuit 106 gatings and be in effective status with the measured device 112 corresponding described I/O driving interface 108 that link to each other, then microprocessor 104 is by described some I/O driving interface 108, the 110 pairs of some measured devices 112 of some jtag bus interfaces that driven by described I/O driving interface 108 carry out boundary scan testing, test finish the some measured devices 112 in back the test result index (as the level of node A be low level then the test result index represent with 0, the level of Node B be high level then the test result index with 1 expression) by corresponding jtag bus interface 110, I/O driving interface 108 sends described microprocessor 104 to, described microprocessor 104 sends the test result index to described computing machine 100 by described usb 1 02, computing machine 100 store test results indexs are also compared the default normal index of test result index and described each measured device 112, whether qualified to judge each measured device 112, even the test result index equates with the default normal index of each measured device 112, judge that then measured device 112 is qualified for this reason, otherwise judge that then measured device 112 is defective for this reason.
In other embodiments, the test result index in the computing machine 100 can also need not store and show according to actual conditions.
As shown in Figure 2, boundary scanning test method of the present invention, whether be used to test some measured device 112 qualified, and its better embodiment may further comprise the steps:
Step S300, computing machine 100 sends test instruction (for example testing certain measured device 112) by described usb 1 02 and test data (for example testing the level of certain node of measured device 112, the function of pin, the parameter informations such as model of chip) is given described microprocessor 104;
Step S302,104 pairs of test instructions of microprocessor and test data are resolved, and be converted into the test instruction and the test data of JTAG form, and control the I/O driving interface 108 that described gating circuit 106 gatings link to each other with measured device 112 and be in effective status, carry out boundary scan testing by I/O driving interface 108,110 pairs of measured devices of jtag bus interface 112 of being driven by I/O driving interface 108 again;
Step S304, when test was finished, microprocessor 104 received the test result index of measured device 112 by the I/O driving interface 108 of effective status, described jtag bus interface 110;
Step S306, microprocessor 104 sends the test result index to described computing machine 100 by usb 1 02, computing machine 100 storage and the indexs that show test results; And
Step S308, computing machine 100 is compared the default normal index of test result index and described measured device 112, whether qualified to judge measured device 112, if the test result index equates with the default normal index of measured device 112, it is qualified then to be judged as measured device 112, otherwise it is defective then to be judged as measured device 112.
In other embodiments, can also save the storage among the step S306 and the index step that shows test results as required.
Boundary scan and test system of the present invention and method of testing can be carried out the test of many printed circuit board (PCB)s simultaneously, thereby improved testing efficiency, have saved the time of test.
Claims (10)
1. boundary scan and test system, comprise a testing apparatus, a Peripheral Interface, a microprocessor, a gating circuit, some I/O driving interface and some jtag bus interfaces that is used to connect measured device, described testing apparatus links to each other with described microprocessor by described Peripheral Interface, described microprocessor links to each other with described some I/O driving interface by described gating circuit, the corresponding jtag bus interface that connects of each I/O driving interface, described microprocessor also links to each other with described some I/O driving interface; Described testing apparatus setting also sends test instruction and test data and send described microprocessor to by described Peripheral Interface, described microprocessor is to described test instruction and test data is resolved and be the test instruction and the test data of JTAG form with described test instruction and test data conversion, and control the I/O driving interface that described gating circuit gating links to each other with described measured device and be in effective status, described microprocessor is by the I/O driving interface of effective status, the jtag bus interface that is driven by described I/O driving interface carries out boundary scan testing to measured device, the test result index of measured device was by corresponding jtag bus interface after test was finished, the I/O driving interface sends described microprocessor to, and described microprocessor sends the test result index to described testing apparatus by Peripheral Interface.
2. boundary scan and test system as claimed in claim 1 is characterized in that: described measured device is for supporting the printed circuit board (PCB) of JTAG technology.
3. boundary scan and test system as claimed in claim 1 is characterized in that: described Peripheral Interface is a USB interface.
4. boundary scan and test system as claimed in claim 1 is characterized in that: described testing apparatus is a computing machine.
5. boundary scan and test system as claimed in claim 1 is characterized in that: described gating circuit comprises some gating chips, is used for described some I/O driving interface are carried out the gating operation.
6. boundary scan and test system as claimed in claim 1 is characterized in that: described testing apparatus also is used for storing or the index that shows test results.
7. boundary scanning test method, whether qualified, may further comprise the steps if being used to test at least one measured device:
One testing apparatus sends test instruction and test data to a microprocessor by a Peripheral Interface;
Described microprocessor is resolved test instruction and test data, and be the test instruction and the test data of JTAG form with test instruction and test data conversion, control the I/O driving interface that a gating circuit gating links to each other with the test measured device and be in effective status, by the I/O driving interface of effective status, the jtag bus interface that is driven by the I/O driving interface measured device is carried out boundary scan testing again;
When test was finished, described microprocessor was by the I/O driving interface of effective status, the test result index that the jtag bus interface receives measured device;
Described microprocessor sends the test result index to described testing apparatus by described Peripheral Interface; And
Described testing apparatus is compared the default normal index of test result index and described measured device, if the test result index equates with the normal index of presetting of measured device, it is qualified then to be judged as measured device, otherwise it is defective then to be judged as measured device.
8. boundary scanning test method as claimed in claim 7, it is characterized in that: described microprocessor sends the test result index to the step of described testing apparatus by described Peripheral Interface after and before described testing apparatus the step that the default normal index of test result index and described measured device is compared, also comprise step: the described testing apparatus storage and the index that shows test results.
9. boundary scanning test method as claimed in claim 7 is characterized in that: described Peripheral Interface is a USB interface.
10. boundary scanning test method as claimed in claim 7 is characterized in that: described testing apparatus is a computing machine, and described measured device is for supporting the printed circuit board (PCB) of JTAG technology.
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| CN200910301527A CN101865976A (en) | 2009-04-14 | 2009-04-14 | Boundary scanning test system and test method |
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| CN200910301527A CN101865976A (en) | 2009-04-14 | 2009-04-14 | Boundary scanning test system and test method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102645609A (en) * | 2012-03-30 | 2012-08-22 | 上海斐讯数据通信技术有限公司 | Joint test action group (JTAG) link circuit test device and test method of JTAG chain circuit test device |
| CN103226506A (en) * | 2013-04-28 | 2013-07-31 | 杭州士兰微电子股份有限公司 | Chip-embedded USB to JTAG debugging device and debugging method |
| CN103675576A (en) * | 2012-09-18 | 2014-03-26 | 英业达科技有限公司 | Chip connection test system and method based on boundary scan |
| CN103778967A (en) * | 2012-10-17 | 2014-05-07 | 南亚科技股份有限公司 | Boundary scan test interface circuit |
| CN104730395A (en) * | 2015-04-03 | 2015-06-24 | 上海航天测控通信研究所 | Novel component testing method based on FPGA |
| CN105607925A (en) * | 2015-12-16 | 2016-05-25 | 深圳市科陆电子科技股份有限公司 | Processor on-chip FLASH program burning method and burning system |
| CN105891657A (en) * | 2016-04-25 | 2016-08-24 | 万高(杭州)科技有限公司 | Method and apparatus for detecting chip bonding conditions of printed circuit board |
| CN110568341A (en) * | 2019-08-30 | 2019-12-13 | 深圳三基同创电子有限公司 | System for automatically testing welding state of IO (input/output) interface function of PCBA (printed circuit board assembly) mainboard |
| CN111579974A (en) * | 2020-06-09 | 2020-08-25 | 中国电子科技集团公司第十四研究所 | Tested module, embedded system and test method for realizing boundary scan test |
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Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102645609B (en) * | 2012-03-30 | 2014-12-10 | 上海斐讯数据通信技术有限公司 | Joint test action group (JTAG) link circuit test device and test method of JTAG chain circuit test device |
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| CN103675576A (en) * | 2012-09-18 | 2014-03-26 | 英业达科技有限公司 | Chip connection test system and method based on boundary scan |
| CN103778967B (en) * | 2012-10-17 | 2017-04-12 | 南亚科技股份有限公司 | Boundary scan test interface circuit |
| CN103778967A (en) * | 2012-10-17 | 2014-05-07 | 南亚科技股份有限公司 | Boundary scan test interface circuit |
| CN103226506A (en) * | 2013-04-28 | 2013-07-31 | 杭州士兰微电子股份有限公司 | Chip-embedded USB to JTAG debugging device and debugging method |
| CN104730395A (en) * | 2015-04-03 | 2015-06-24 | 上海航天测控通信研究所 | Novel component testing method based on FPGA |
| CN105607925A (en) * | 2015-12-16 | 2016-05-25 | 深圳市科陆电子科技股份有限公司 | Processor on-chip FLASH program burning method and burning system |
| CN105607925B (en) * | 2015-12-16 | 2019-06-18 | 深圳市科陆电子科技股份有限公司 | Processor in-chip FLASH burning program method and programming system |
| CN105891657A (en) * | 2016-04-25 | 2016-08-24 | 万高(杭州)科技有限公司 | Method and apparatus for detecting chip bonding conditions of printed circuit board |
| CN110568341A (en) * | 2019-08-30 | 2019-12-13 | 深圳三基同创电子有限公司 | System for automatically testing welding state of IO (input/output) interface function of PCBA (printed circuit board assembly) mainboard |
| CN111579974A (en) * | 2020-06-09 | 2020-08-25 | 中国电子科技集团公司第十四研究所 | Tested module, embedded system and test method for realizing boundary scan test |
| CN111579974B (en) * | 2020-06-09 | 2021-09-03 | 中国电子科技集团公司第十四研究所 | Embedded system for realizing boundary scan test and test method |
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Application publication date: 20101020 |