CN111008102B - FPGA accelerator card high-speed interface SI test control device, system and method - Google Patents
FPGA accelerator card high-speed interface SI test control device, system and method Download PDFInfo
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Abstract
The invention provides an SI test control device, a system and a method for a high-speed interface of an FPGA accelerator card, wherein the SI test control device for the high-speed interface of the FPGA accelerator card based on an SOC device comprises a user interaction interface and a high-speed interface controller, wherein the user interaction interface is connected with a code pattern switching processing unit through a code pattern selection unit; the code pattern switching processing unit is connected with the high-speed interface controller; the high-speed interface controller is also connected with a high-speed interface mode configuration unit; the code pattern switching processing unit is used for generating configuration information of a corresponding code pattern according to the judgment of the code pattern selection unit and outputting the configuration information to the high-speed interface controller; the high-speed interface controller is used for working in a corresponding mode according to configuration information from the high-speed interface mode configuration unit and the code type switching processing unit to realize the receiving and sending of high-speed interface data.
Description
Technical Field
The invention relates to the technical field of signal integrity test, in particular to a device, a system and a method for controlling an SI test of an FPGA accelerator card high-speed interface.
Background
The FPGA accelerator card based on the SOC device has high performance computing capability and is widely applied to the field of artificial intelligence, and the programmable SOC device integrating processor software and FPGA hardware provides powerful support for realizing the artificial intelligence technology. The SOC device effectively improves the integration level, performance, flexibility and expandability of the system, and allows a designer to flexibly add different peripherals and hardware accelerators according to different application scenes, thereby achieving the goals of optimization and difference. The abundance of peripheral and high-speed interface advantages also means that there is an increasing demand for FPGA accelerator card hardware design and signal integrity.
Signal integrity is a series of metrics for electronic signal quality, and generally refers to a phenomenon that signals are distorted and distorted finally due to interaction of multiple factors such as high-speed signal wiring, component layout, power quality and the like in a high-speed PCB. The high-speed interface of the FPGA accelerator card generally includes DDR, USB, PCIE, ethernet port, and the like. USB is used as an external bus standard to standardize the connection and communication between computers and external devices. The high-speed development of computer technology promotes the improvement of bus standard, and the transmission rate of the current ultra-high-speed interface USB3.0 can reach 5Gbps. For such a high-speed interface, signal integrity testing is an important link for ensuring the quality of hardware products.
In the conventional method, the signal integrity of the USB interface is tested by an oscilloscope, and an oscilloscope probe is connected to the USB interface to be tested by a fixture. The USB3.0 TX test requires a USB interface to be tested to send a plurality of code type packets (at least comprising three patterns of CP0, CP1 and LFPS) which meet the standard, and then the test is completed by testing an eye pattern through an oscilloscope. In the prior art, the SI test of the USB interface of a server product can be realized by customizing a BIOS configuration package code pattern, while for an FPGA accelerator card, no specific package sending control tool aiming at the SI test of the USB interface exists at present, and the test is finished by writing a configuration package of an internal register of an SOC chip in the existing method. The method for writing the configuration of the USB controller in the internal register of the SOC device to send the packet adopts complete manual operation, and has low automation degree. Because the tester is not familiar with the internal structure of the chip and the configuration of the register, the operation is complex and the error is easy to occur, and the project testing progress is seriously influenced. And research and development personnel are often required to conduct on-site guidance, so that the labor cost is increased.
Disclosure of Invention
The method for writing the USB controller packet of the internal register configuration of the SOC device adopts complete manual operation and has low automation degree. Because the tester is not familiar with the internal structure of the chip and the configuration of the register, the operation is complex and the error is easy to occur, and the project testing progress is seriously influenced. The invention provides a device, a system and a method for controlling the high-speed interface SI test of an FPGA accelerator card, and aims to solve the problems that field guidance of research personnel is often needed and the labor cost is increased.
The technical scheme provided by the invention is as follows:
on one hand, the technical scheme of the invention provides an SI test control device of a high-speed interface of an FPGA accelerator card based on an SOC device, which comprises a user interaction interface and a high-speed interface controller, wherein the user interaction interface is connected with a code pattern switching processing unit through a code pattern selection unit; the code pattern switching processing unit is connected with the high-speed interface controller; the high-speed interface controller is also connected with a high-speed interface mode configuration unit;
the user exchange interface is a debugging interface of the FPGA accelerator card, and a test is started and a pretest code pattern is input through the user exchange interface;
the high-speed interface mode configuration unit is used for generating different mode configuration information to carry out sending test;
the code type selection unit is connected with the user interaction interface and the code type switching processing unit; the code pattern type input by an operator through the user interaction interface is identified; the code pattern processing unit is also used for entering a corresponding code pattern processing link after the judgment and the verification of the selected code pattern are carried out;
the code pattern switching processing unit is used for generating configuration information of a corresponding code pattern according to the judgment of the code pattern selection unit and outputting the configuration information to the high-speed interface controller;
the high-speed interface controller is used for working in a corresponding mode according to configuration information from the high-speed interface mode configuration unit and the code type switching processing unit to realize the receiving and sending of high-speed interface data.
Preferably, the high-speed interface is a USB interface, the high-speed interface controller is a USB controller, and the high-speed interface mode configuration unit is a USB mode configuration unit.
Preferably, the device realizes the output of the code pattern packet and the configuration of the USB mode required by the integrity test of the USB interface signal based on an ARM processor built in the SOC device.
Preferably, the USB mode configuration unit is configured to generate mode configuration information, and set the USB controller to a host mode with different mode interface rates for performing a transmission test;
the user exchange interface is also used for printing a log to know the package sending state information of the test code pattern through the interface;
the code type selection unit is connected with the user interaction interface and the code type switching processing unit; the code pattern type is used for identifying the code pattern type input by an operator through the user interaction interface; the code pattern processing unit is also used for entering a corresponding code pattern processing link after the judgment and the verification of the selected code pattern are carried out;
the code pattern switching processing unit is used for generating configuration information of a corresponding code pattern according to the judgment of the code pattern selection unit and outputting the configuration information to the USB controller;
and the USB controller is used for working in a corresponding mode according to the configuration information from the USB mode configuration unit and the code pattern switching processing unit to realize the transceiving of USB interface data.
In a second aspect, the technical scheme of the invention provides an SI test system for a high-speed interface of an FPGA accelerator card, which comprises a SI test control device for the high-speed interface and an interface link to be tested; the high-speed interface SI test control device is in communication connection with an interface link to be tested, and the interface link to be tested is used for being connected to an oscilloscope; the high-speed interface SI test control device is the FPGA accelerator card high-speed interface SI test control device of the first aspect.
Preferably, the interface link to be tested comprises a USB physical layer transceiver and a USB connector, and the USB physical layer transceiver is connected with the USB connector; the USB connector is connected to the oscilloscope;
the USB physical layer transceiver is connected with the USB controller and used for realizing transceiving interconnection with an interface link to be tested through the USB controller in the ARM processor built in the SOC device and completing a sending code pattern test of the USB interface through the oscilloscope.
Preferably, the interface link to be tested comprises a first interface link to be tested and a second interface link to be tested;
the first interface link to be tested comprises a first USB physical layer transceiver and a first USB controller, and the first USB physical layer transceiver is connected with the first USB controller;
the second interface link to be tested comprises a second USB physical layer transceiver and a second USB controller, and the second USB physical layer transceiver is connected with the second USB controller;
the first USB physical layer transceiver and the second USB physical layer transceiver are both connected to the USB controller.
In a third aspect, the technical solution of the present invention further provides a method for testing an SI test system for an FPGA accelerator card high-speed interface, which is based on the test method for the SI test system for an FPGA accelerator card high-speed interface provided in the second aspect, and includes the following steps:
step 1: starting a test through a user interaction interface, entering a test mode, and selecting a first interface link to be tested or a second interface link to be tested;
and 2, step: the USB mode configuration unit configures the USB controller into a USB3.0 host mode to perform host end sending test;
and step 3: inputting code pattern information corresponding to the test code pattern through a user interaction interface;
and 4, step 4: the code pattern selection unit outputs an instruction to enter a corresponding code pattern processing link after judging and checking according to the code pattern information input by the user interaction interface;
and 5: the code pattern switching processing unit generates configuration information of a corresponding code pattern according to the instruction of the code pattern selection unit and the working mechanism of the code pattern skip state machine and outputs the configuration information to the USB controller to complete code pattern switching processing;
step 6: the USB controller works in a corresponding mode according to configuration information from the USB mode configuration unit and the code pattern switching processing unit, and outputs the code pattern corresponding to the configuration information to the interface link to be tested selected in the step 1 through the sending port;
and 7: outputting a standard code pattern to an oscilloscope by the interface link to be tested, and completing the integrity test of the USB3.0 TX signal by a test eye pattern;
and 8: and (4) after the input code pattern test is finished, jumping back to the step 3 to perform the next code pattern test.
According to the technical scheme, the invention has the following advantages: aiming at an FPGA accelerator card based on an SOC device, the system and the method for testing the signal integrity of the USB interface based on the SOC built-in ARM system are provided, the USB3.0 test code pattern can be automatically output, and the problems of unclear packet issuing method, poor operability and the like in the link of testing the signal integrity of the USB interface of the accelerator card are solved. The method adopts an internal processor, fully utilizes the advantage of flexibility of an SOC device without hardware layout pressure, is realized on the basis of the existing hardware platform, and does not need to increase an external control chip; the switching of various standard code patterns (nine CPO-CP8 patterns in total) can be realized, the operation is convenient, errors are not easy to occur, the operation redundancy of a testing link is effectively reduced, and the testing efficiency is improved.
In addition, the invention has reliable design principle, simple structure and very wide application prospect.
Therefore, compared with the prior art, the invention has prominent substantive features and remarkable progress, and the beneficial effects of the implementation are also obvious.
Drawings
In order to more clearly illustrate the embodiments or prior art solutions of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a connection block diagram of an SI test control device for an FPGA accelerator card high-speed interface according to an embodiment of the present invention.
Fig. 2 is a connection block diagram of an SI test control system for an FPGA accelerator card high-speed interface according to a second embodiment of the present invention.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example one
As shown in fig. 1, an embodiment of the present invention provides an SI test control device for a high-speed interface of an FPGA accelerator card, which is based on an SOC device, and includes a user interaction interface and a high-speed interface controller, where the user interaction interface is connected to a code pattern switching processing unit through a code pattern selection unit; the code pattern switching processing unit is connected with the high-speed interface controller; the high-speed interface controller is also connected with a high-speed interface mode configuration unit;
the user exchange interface is a debugging interface of the FPGA accelerator card, and starts testing and inputs a pretest code pattern through the user exchange interface; it should be noted that the user exchange interface is used as a debugging interface of the FPGA accelerator card, which is usually a serial port, and during the SI test of the interface, an operator can start a test and input a pre-test code pattern through the interface, and can also print a log through the interface to know information such as a package sending state of the test code pattern.
The high-speed interface mode configuration unit is used for generating different mode configuration information to carry out sending test;
the code type selection unit is connected with the user interaction interface and the code type switching processing unit; the code pattern type input by an operator through the user interaction interface is identified; the code pattern processing unit is also used for entering a corresponding code pattern processing link after the judgment and the verification of the selected code pattern are carried out;
the code pattern switching processing unit is used for generating configuration information of a corresponding code pattern according to the judgment of the code pattern selection unit and outputting the configuration information to the high-speed interface controller;
the high-speed interface controller is used for working in a corresponding mode according to configuration information from the high-speed interface mode configuration unit and the code type switching processing unit to realize the receiving and sending of high-speed interface data.
Example two
The embodiment of the invention provides an SI test control device of a high-speed interface of an FPGA accelerator card based on an SOC device, which comprises a user interaction interface and a high-speed interface controller, wherein the user interaction interface is connected with a code pattern switching processing unit through a code pattern selection unit; the code pattern switching processing unit is connected with the high-speed interface controller; the high-speed interface controller is also connected with a high-speed interface mode configuration unit;
the user exchange interface is a debugging interface of the FPGA accelerator card, and a test is started and a pretest code pattern is input through the user exchange interface; it should be noted that the user exchange interface is used as a debugging interface of the FPGA accelerator card, which is usually a serial port, and during the SI test of the interface, an operator can start a test and input a pre-test code pattern through the interface, and can also print a log through the interface to know information such as a package sending state of the test code pattern.
The high-speed interface mode configuration unit is used for generating different mode configuration information to carry out sending test;
the code type selection unit is connected with the user interaction interface and the code type switching processing unit; the code pattern type is used for identifying the code pattern type input by an operator through the user interaction interface; the code pattern processing unit is also used for entering a corresponding code pattern processing link after the judgment and the verification of the selected code pattern are carried out;
the code pattern switching processing unit is used for generating configuration information of a corresponding code pattern according to the judgment of the code pattern selection unit and outputting the configuration information to the high-speed interface controller;
the high-speed interface controller is used for working in a corresponding mode according to the configuration information from the high-speed interface mode configuration unit and the code type switching processing unit to realize the receiving and sending of the high-speed interface data.
In this embodiment, the high-speed interface is a USB interface, the high-speed interface controller is a USB controller, and the high-speed interface mode configuration unit is a USB mode configuration unit. The device realizes code pattern packet output and USB mode configuration required by USB interface signal integrity test based on an ARM processor built in an SOC device.
Preferably, the USB mode configuration unit is configured to generate mode configuration information, and set the USB controller to a host mode with different mode interface rates for performing a transmission test;
and the code type selection unit is connected with the user interaction interface and the code type switching processing unit. On one hand, the code type input by an operator through the user interaction interface is identified, and the code type selection unit can provide selection of nine standard code types according to the corresponding test standard of the USB; on the other hand, after the judgment and the verification of the selected code pattern are carried out, the corresponding code pattern processing link is entered. And the code pattern switching processing unit generates configuration information of a corresponding code pattern according to the judgment of the code pattern selection unit and outputs the configuration information to the USB controller.
The USB controller is used for realizing the receiving and sending of USB interface data. According to the configuration information from the USB mode configuration unit and the code pattern switching processing unit, the USB interface test device works in a corresponding mode, outputs the code pattern corresponding to the configuration information through the sending port, and simultaneously connects a USB interface link to be tested, which is formed by a USB physical layer transceiver and a USB connector, wherein the USB connector can be a USB3.0 connector, so that the sending code pattern test of the USB3.0 interface can be completed through an oscilloscope.
EXAMPLE III
As shown in fig. 2, the technical solution of the present invention provides an SI test system for a high-speed interface of an FPGA accelerator card, which includes a SI test control device for a high-speed interface and a link of an interface to be tested; the high-speed interface SI test control device is in communication connection with an interface link to be tested, and the interface link to be tested is used for being connected to an oscilloscope; the high-speed interface SI test control device is the FPGA accelerator card high-speed interface SI test control device of the first aspect.
The interface link to be tested comprises a USB physical layer transceiver and a USB connector, wherein the USB physical layer transceiver is connected with the USB connector; when the system is tested, the USB connector is connected to an oscilloscope; the USB physical layer transceiver is connected with the USB controller and used for realizing transceiving interconnection with an interface link to be tested through the USB controller in the ARM processor built in the SOC device and completing a sending code pattern test of the USB interface through the oscilloscope. The interface link to be tested comprises a first interface link to be tested and a second interface link to be tested; the first interface link to be tested comprises a first USB physical layer transceiver and a first USB controller, and the first USB physical layer transceiver is connected with the first USB controller; the second interface link to be tested comprises a second USB physical layer transceiver and a second USB controller, and the second USB physical layer transceiver is connected with the second USB controller; the first USB physical layer transceiver and the second USB physical layer transceiver are both connected to the USB controller.
The USB physical layer transceiver and the USB3.0 connector form a USB interface link to be tested, and the connector of the interface is connected to the oscilloscope through the jig so as to establish a complete signal integrity test environment. The test control system is connected with the two USB physical layer transceivers through the USB controller in the SOC processor to realize the transceiving interconnection with the interface link to be tested, thereby forming a complete USB channel to ensure the normal transceiving communication of the USB interface. When the SI test is not started, the interface to be tested is a standard USB interface, can be configured to support USB2.0 or USB3.0, and can be used as a host end and a device end; if SI test is needed, starting test and starting corresponding code pattern sending test, and after test is stopped or power is lost, the normal USB mode can be recovered, and normal use of the USB interface is not affected. In addition, the user interaction interface of the test control system adopts a serial port of the SOC system, and the SOC system is used as a standard debugging port when the test is not started.
The whole working process of the FPGA accelerator card USB3.0 interface SI test control system comprises the following steps:
starting a test through a user interaction interface, entering a test mode, and selecting an interface link to be tested; the USB mode configuration unit configures the USB controller into a USB3.0 mode, a host mode, so as to carry out host end sending test, and if necessary, the unit can also use corresponding commands to adjust parameters such as driving capability, aggravation and the like; inputting a code corresponding to the test code pattern by the user interaction interface, and selecting any one of nine standard code patterns CP0-CP8 according to actual test requirements; the code pattern selection unit enters a corresponding code pattern processing link after judging and checking according to the code pattern information input by the interactive interface; the code pattern switching processing unit generates configuration information of a corresponding code pattern according to the instruction of the code pattern selection unit and the working mechanism of the code pattern skip state machine, outputs the configuration information to the USB controller and completes code pattern switching processing; the USB controller works in a corresponding mode according to configuration information from the USB mode configuration unit and the code pattern switching processing unit, outputs a code pattern corresponding to the configuration information through the sending port and outputs the code pattern to the interface to be tested; and the interface to be tested outputs the standard code pattern to the oscilloscope, and the test eye pattern completes the integrity test of the USB3.0 TX signal.
Example four
The technical scheme of the invention also provides an SI test method of the high-speed interface of the FPGA accelerator card, which is based on the test method of the SI test system of the high-speed interface of the FPGA accelerator card provided by the third embodiment and comprises the following steps:
step 1: starting a test through a user interaction interface, entering a test mode, and selecting a first interface link to be tested or a second interface link to be tested;
and 2, step: the USB mode configuration unit configures the USB controller into a USB3.0 host mode to perform host end sending test;
and step 3: inputting code pattern information corresponding to the test code pattern through a user interaction interface;
and 4, step 4: the code type selection unit outputs an instruction to enter a corresponding code type processing link after judging and checking according to the code type information input by the user interaction interface;
and 5: the code pattern switching processing unit generates configuration information of a corresponding code pattern according to the instruction of the code pattern selection unit and the working mechanism of the code pattern skip state machine and outputs the configuration information to the USB controller to complete code pattern switching processing;
step 6: the USB controller works in a corresponding mode according to configuration information from the USB mode configuration unit and the code pattern switching processing unit, and outputs the code pattern corresponding to the configuration information to the interface link to be tested selected in the step 1 through the sending port;
and 7: outputting a standard code pattern to an oscilloscope by the interface link to be tested, and completing the integrity test of the USB3.0 TX signal by a test eye pattern;
and step 8: and after the input code pattern test is finished, jumping back to the step 3 to carry out the next code pattern test.
And (3) annotation:
although the present invention has been described in detail in connection with the preferred embodiments with reference to the accompanying drawings, the present invention is not limited thereto. Various equivalent modifications or substitutions can be made on the embodiments of the present invention by those skilled in the art without departing from the spirit and scope of the present invention, and these modifications or substitutions should be within the scope of the present invention/any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure and the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (6)
1. The SI test control device of the high-speed interface of the FPGA accelerator card is characterized by comprising a user interaction interface and a high-speed interface controller, wherein the user interaction interface is connected with a code pattern switching processing unit through a code pattern selection unit; the code pattern switching processing unit is connected with the high-speed interface controller; the high-speed interface controller is also connected with a high-speed interface mode configuration unit;
the user interaction interface is a debugging interface of the FPGA accelerator card, and a test is started and a pretest code pattern is input through the user interaction interface;
the high-speed interface mode configuration unit is used for generating different mode configuration information to carry out sending test;
the code type selection unit is connected with the user interaction interface and the code type switching processing unit; the code pattern type input by an operator through the user interaction interface is identified; the code pattern processing unit is also used for entering a corresponding code pattern processing link after the judgment and the verification of the selected code pattern are carried out;
the code pattern switching processing unit is used for generating configuration information of a corresponding code pattern according to the judgment of the code pattern selection unit and outputting the configuration information to the high-speed interface controller;
the high-speed interface controller is used for working in a corresponding mode according to configuration information from the high-speed interface mode configuration unit and the code type switching processing unit to realize the receiving and sending of high-speed interface data;
the high-speed interface is a USB interface, the high-speed interface controller is a USB controller, and the high-speed interface mode configuration unit is a USB mode configuration unit;
the USB mode configuration unit is used for generating mode configuration information and setting the USB controller into a host mode with different mode interface rates so as to carry out sending test;
the user interaction interface is also used for printing logs through the interface to know the package sending state information of the test code pattern;
the code pattern switching processing unit is used for generating configuration information of a corresponding code pattern according to the judgment of the code pattern selection unit and outputting the configuration information to the USB controller;
and the USB controller is used for working in a corresponding mode according to the configuration information from the USB mode configuration unit and the code pattern switching processing unit to realize the transceiving of USB interface data.
2. The device as claimed in claim 1, wherein the device is configured to implement output of a code pattern packet and configuration of a USB mode required for testing signal integrity of a USB interface based on an ARM processor built in the SOC device.
3. A kind of FPGA accelerates the high-speed interface SI test system of the card, characterized by including high-speed interface SI test controlling device and interface link to be measured; the high-speed interface SI test control device is in communication connection with an interface link to be tested, and the interface link to be tested is used for being connected to an oscilloscope; the high-speed interface SI test control device is the FPGA accelerator card high-speed interface SI test control device of any one of claims 1-2.
4. The system according to claim 3, wherein the interface link to be tested comprises a USB physical layer transceiver and a USB connector, the USB physical layer transceiver being connected to the USB connector; the USB connector is connected to the oscilloscope;
the USB physical layer transceiver is connected with the USB controller and used for realizing transceiving interconnection with an interface link to be tested through the USB controller in the ARM processor built in the SOC device and completing a sending code pattern test of the USB interface through the oscilloscope.
5. The FPGA accelerator card high-speed interface SI test system according to claim 4, wherein the interface link to be tested comprises a first interface link to be tested and a second interface link to be tested;
the first interface link to be tested comprises a first USB physical layer transceiver and a first USB controller, and the first USB physical layer transceiver is connected with the first USB controller;
the second interface link to be tested comprises a second USB physical layer transceiver and a second USB controller, and the second USB physical layer transceiver is connected with the second USB controller;
the first USB physical layer transceiver and the second USB physical layer transceiver are both connected to the USB controller.
6. A method for testing an SI (field programmable gate array) high-speed interface of an FPGA (field programmable gate array) accelerator card is characterized by comprising the following steps of:
step 1: starting a test through a user interaction interface, entering a test mode, and selecting a first interface link to be tested or a second interface link to be tested;
and 2, step: the USB mode configuration unit configures the USB controller into a USB3.0 host mode to perform host end sending test;
and step 3: inputting code pattern information corresponding to the test code pattern through a user interaction interface;
and 4, step 4: the code type selection unit outputs an instruction to enter a corresponding code type processing link after judging and checking according to the code type information input by the user interaction interface;
and 5: the code pattern switching processing unit generates configuration information of a corresponding code pattern according to the instruction of the code pattern selection unit and the working mechanism of the code pattern skip state machine and outputs the configuration information to the USB controller to complete code pattern switching processing;
step 6: the USB controller works in a corresponding mode according to configuration information from the USB mode configuration unit and the code pattern switching processing unit, and outputs the code pattern corresponding to the configuration information to the interface link to be tested selected in the step 1 through the sending port;
and 7: the interface link to be tested outputs a standard code pattern to an oscilloscope, and the test eye diagram completes the integrity test of the USB3.0 TX signal;
and 8: and after the input code pattern test is finished, jumping back to the step 3 to carry out the next code pattern test.
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| CN113204452B (en) * | 2021-04-23 | 2023-01-10 | 山东英信计算机技术有限公司 | Method, system and medium for measuring high-speed signal |
| CN114185603B (en) * | 2021-11-08 | 2024-01-05 | 深圳云天励飞技术股份有限公司 | Control method of intelligent accelerator card, server and intelligent accelerator card |
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