CN101770417B - Hardware fault injection system and fault injection method based on JTAG - Google Patents
Hardware fault injection system and fault injection method based on JTAG Download PDFInfo
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- CN101770417B CN101770417B CN 201010300340 CN201010300340A CN101770417B CN 101770417 B CN101770417 B CN 101770417B CN 201010300340 CN201010300340 CN 201010300340 CN 201010300340 A CN201010300340 A CN 201010300340A CN 101770417 B CN101770417 B CN 101770417B
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- 230000003139 buffering effect Effects 0.000 claims abstract description 8
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Abstract
The invention provides a hardware fault injection system and a fault injection method based on JTAG, which relate to a fault injection system and a fault injection method. The invention solves the problems that various protocols and various chips can not be effectively supported in the existing fault injection device and the fault injection method. The hardware fault injection system comprises a host computer, a USB interface module, a protocol conversion module and a hardware fault injection module. The fault injection method comprises the following processes: an application layer software module in the host computer generates fault data to be injected and protocol conversion control data and sends the fault data to be injected and the protocol conversion control data to the protocol conversion module through the USB interface module after combining the fault data to be injected and the protocol conversion control data; the protocol conversion module carries out USB buffering and USB protocol analysis on the combined data, and then carries out ITP protocol package; and finally, the hardware fault injection module injects the JTAG fault data into the target chip from a JTAG port after carrying out the ITP protocol analysis on the data. The invention overcomes the defects in the prior art, and can be used in the technical filed of fault injection of different chips supported by different regulation protocols.
Description
Technical field
The present invention relates to a kind of hardware fault injected system and fault filling method.
Background technology
It is the important technical of carrying out product test and system verification that fault is injected, and comes the accelerated test process by conscious to system's injection fault.Hardware fault is injected the fault generally be the pin level and is injected, and reaches to system by the curtage that changes pin and injects fault, has a time precision high, is easy to the advantages such as control.Lack in the market can effective support various protocols various chips fault injector.
Summary of the invention
The objective of the invention is to solve in present fault injector and the fault filling method can not the effective support various protocols, the problem of various chips, and a kind of hardware fault injected system and fault filling method based on JTAG is provided.
Hardware fault injected system based on JTAG, it comprises host computer, usb interface module, protocol conversion module and hardware fault injection module, described host computer is connected with protocol conversion module by usb interface module, and the ITP port of described protocol conversion module is connected with the hardware fault injection module.
Fault filling method based on JTAG, it utilizes the hardware fault injected system based on JTAG to realize, described hardware fault injected system based on JTAG comprises host computer, usb interface module, protocol conversion module and hardware fault injection module, described host computer is connected with protocol conversion module by usb interface module, the ITP port of described protocol conversion module is connected with the hardware fault injection module, and host computer is embedded in and is useful on the application layer software module that generates fault data to be injected and protocol conversion control data;
Based on the fault filling method of JTAG, its detailed process is:
The application layer software module that is embedded with in step 1, the host computer generates fault data to be injected and protocol conversion control data, and according to protocol analysis and conversion order fault data described to be injected and protocol conversion control data are made up, the data communication device after then will making up is crossed usb interface module and is sent to protocol conversion module;
Fault injector of the present invention and the method for carrying out the fault injection have advantages of the various protocols of support and various chips.
Description of drawings
Fig. 1 is the structural representation of the hardware fault injected system of embodiment one; Fig. 2 is the structural representation of the hardware fault injected system of embodiment two; Fig. 3 is the structural representation of the hardware fault injected system of embodiment three; Fig. 4 is the schematic block circuit diagram of the hardware fault injected system of embodiment four; Fig. 5 is the process flow diagram of the fault filling method of embodiment five; Fig. 6 is the process flow diagram of step 2 in the embodiment six.
Embodiment
Embodiment one: present embodiment is described in conjunction with Fig. 1, the hardware fault injected system based on JTAG of present embodiment, it comprises host computer 1, usb interface module 2, protocol conversion module 3 and hardware fault injection module 4, described host computer 1 is connected connection by usb interface module 2 with protocol conversion module, the ITP port of described protocol conversion module 3 is connected with hardware fault injection module 4.
Host computer 1 is embedded in and is useful on the application layer software module that generates fault data to be injected and protocol conversion control data.
Protocol conversion module in the present embodiment can adopt the CPLD chip to realize.
Hardware fault injection module 4 is used for the data that receive are carried out obtaining JTAG fault data and order data behind the ITP protocol analysis, and is used for according to described order data the JTAG fault data being exported from jtag port.
Described protocol conversion control data comprise: protocol conversion module and ITP port communication control data, ITP agreement control data and standard JTAG agreement control data.Described protocol conversion control data are used for the command type data that prompting protocol conversion module 3 and 4 pairs of data of hardware fault injection module are carried out respective handling, and it is the control type data.
Objective chip is Pentium IV processor chips.Carry out because fault is injected to be under the running status in objective chip, therefore on the basis of mainboard commonly used, connect outside with objective chip pin line, adopt hardware to realize operation and debugging module, be used for the JTAG data input under the ITP agreement.The fault injecting data comprises 4 classes: protocol conversion module and ITP port communication control data, ITP agreement control data, standard JTAG agreement control data and based on the JTAG fault injecting data of pin level.Wherein, protocol conversion module and ITP port communication control data are used for the 8 bit parallel data of inputting from the USB buffer chip are controlled, and serial sends to the ITP port; ITP agreement control data are used for passing on the control order that jtag port is carried out or interrupted to objective chip JTAG debugging end; Standard JTAG agreement control data are used for sending order to the JTAG debugging interface, control JTAG data transfer; Based on the JTAG fault injecting data of pin level, under JTAG order control in the input hardware chip pin.
Hardware fault injection module 4, comprise the ITP interface that is connected with protocol conversion module and the CPU base that lays respectively at the circuit board front and back, the front base inserts CPU, by circuit pin is connected to back side base, and back side base inserts in the CPU socket of general mainboard by contact pin.
Wherein, ITP is the abbreviation abbreviation of In-Target Probe; JTAG is that the abbreviation of Joint Test Action Group is called for short.
In the present embodiment, the ITP agreement can also be other debugging agreements based on JTAG of this area, so the fault injector of present embodiment is capable of supporting several protocols and various chips.
The present invention is by the setting of host computer end software parameter and carry out protocol conversion by FPGA (Field Programmable Gate Array) in protocol conversion module, has realized the pin level fault injector of a universal flexible.
Embodiment two: in conjunction with Fig. 2 present embodiment is described, different from embodiment one is that the protocol conversion module 3 of present embodiment is comprised of crystal oscillator 31, the first chip 32, the second chip 33 and ITP interface unit 34;
The clock signal output terminal of described crystal oscillator 31 connects the clock signal input terminal of the first chip 32, the usb data serial port of described the first chip 32 is connected with the usb data serial port of usb interface module 2, the parallel data port of the first chip 32 is connected with the parallel data port of the second chip 33, and the second chip 33 is connected with hardware fault injection module 4 by ITP interface unit 34.
Described crystal oscillator 31 is used for providing reference clock; The first chip 32 is used for finishing buffering and protocol analysis to usb data; The second chip 33 be used for the data that obtain after the usb protocol parsing are carried out the ITP protocol packing, and the data after will packing is exported to hardware fault injection module 4.
The first chip 32 in the present embodiment is explained chip for usb protocol.
The second chip 33 in the present embodiment can be selected the CPLD chip for can weave into logic chip.
Embodiment three: present embodiment is described in conjunction with Fig. 3, different from embodiment two is, present embodiment also comprises JTAG download interface module 5, and the data input/output end port of described JTAG download interface module 5 is connected with the JTAG data download port of protocol conversion module 3.
Embodiment four: in conjunction with Fig. 4 present embodiment is described, present embodiment is a specific embodiment of embodiment three, and the present embodiment also comprises reset circuit 6.
Present embodiment also comprises power supply, and described power supply is used to each circuit that working power is provided.In the present embodiment, the first chip 32 is selected the FT245R chip, and the second chip 33 is selected EPM240 type CPLD.
Embodiment five: present embodiment is described in conjunction with Fig. 5, the fault filling method based on JTAG of present embodiment, it utilizes the hardware fault injected system based on JTAG to realize, described hardware fault injected system based on JTAG comprises host computer 1, usb interface module 2, protocol conversion module 3 and hardware fault injection module 4, described host computer 1 is connected connection by usb interface module 2 with protocol conversion module, the ITP port of described protocol conversion module 3 is connected with hardware fault injection module 4, and host computer 1 is embedded in and is useful on the application layer software module that generates fault data to be injected and protocol conversion control data;
Based on the fault filling method of JTAG, its detailed process is:
The application layer software module that is embedded with in step 1, the host computer 1 generates fault data to be injected and protocol conversion control data, and according to protocol analysis and conversion order fault data described to be injected and protocol conversion control data are made up, the data communication device after then will making up is crossed usb interface module 2 and is sent to protocol conversion module 3;
Data after step 2,3 pairs of combinations of protocol conversion module are carried out the USB buffering and usb protocol is resolved, and the data that obtain after then usb protocol being resolved are carried out the ITP protocol packing, and the data after will packing are again exported to hardware fault injection module 4;
Described objective chip is Pentium IV processor chips.Debugging module in the objective chip carries out the ITP protocol analysis to the data that receive, and the data behind the ITP protocol analysis is processed again.Objective chip utilizes the JTAG debug port to control the injection of fault data and result's recovery, wherein as a result removal process and above process contrary, finally inject result data by host computer end application layer software module 1 read failure from usb interface module 2, carry out again analyzing and processing.
Embodiment six: present embodiment is described in conjunction with Fig. 6, present embodiment be to embodiment five based on the further specifying of the fault filling method of JTAG, described protocol conversion module 3 is by crystal oscillator 31, the first chip 32, the second chip 33 and ITP interface unit 34;
The detailed process of the described content of step 2 is:
Data transmission between described the first chip 32 and the second chip 33 realizes by the mode of shaking hands.
Embodiment seven: present embodiment be to embodiment five or six based on the further specifying of the fault filling method of JTAG, described protocol conversion control data comprise: protocol conversion module 3 and ITP port communication control data, ITP agreement control data and standard JTAG agreement control data.Wherein, protocol conversion module 3 and ITP port communication control data are used for the 8 bit parallel data of inputting from the USB buffer chip are controlled, and serial sends to the ITP port; ITP agreement control data are used for passing on the control order that jtag port is carried out or interrupted to objective chip JTAG debugging end; Standard JTAG agreement control data are used for sending order to the JTAG debugging interface, control JTAG data transfer.
Claims (5)
1. based on the hardware fault injected system of JTAG, it is characterized in that it comprises host computer (1), usb interface module (2), protocol conversion module (3) and hardware fault injection module (4), described host computer (1) is connected 3 by usb interface module (2) with protocol conversion module) connect, the ITP interface unit of described protocol conversion module (3) is connected with hardware fault injection module (4);
Based on the fault filling method of JTAG, its detailed process is:
The application layer software module that is embedded with in step 1, the host computer (1) generates fault data to be injected and protocol conversion control data, and according to protocol analysis and conversion order fault data described to be injected and protocol conversion control data are made up, the data communication device after then will making up is crossed usb interface module (2) and is sent to protocol conversion module (3);
Step 2, protocol conversion module (3) carry out USB buffering and usb protocol parsing to the data after making up, and the data that obtain after then usb protocol being resolved are carried out the ITP protocol packing, and the data after will packing are again exported to hardware fault injection module (4);
Step 3, hardware fault injection module (4) carry out obtaining JTAG fault data and order data behind the ITP protocol analysis to the data that receive, and according to described order data the JTAG fault data are injected objective chip from jtag port.
2. the hardware fault injected system based on JTAG according to claim 1 is characterized in that described protocol conversion module (3) is comprised of crystal oscillator (31), the first chip (32), the second chip (33) and ITP interface unit (34);
The clock signal output terminal of described crystal oscillator (31) connects the clock signal input terminal of the first chip (32), the usb data serial port of described the first chip (32) is connected with the usb data serial port of usb interface module (2), the parallel data port of the first chip (32) is connected with the parallel data port of the second chip (33), and the second chip (33) is connected with hardware fault injection module (4) by ITP interface unit (34);
The detailed process of the described content of step 2 is:
Step 2 one, the first chip (32) are finished USB buffering and the usb protocol of the data after the described combination are resolved, then take byte as unit, take the clock of crystal oscillator (31) as beat and in the mode of 8 bit parallels, the data that obtain after usb protocol resolved are sent to the second chip (33);
Step 2 two, the second chip (33) carry out the ITP protocol packing to the data that receive, and the data communication device after will packing is crossed ITP interface unit (34) and sent to hardware fault injection module (4).
3. the hardware fault injected system based on JTAG according to claim 2, it is characterized in that it also comprises JTAG download interface module (5), the data input/output end port of described JTAG download interface module (5) is connected with the JTAG data download port of protocol conversion module (3).
4. based on the fault filling method of JTAG, it is characterized in that it utilizes the hardware fault injected system based on JTAG to realize, described hardware fault injected system based on JTAG comprises host computer (1), usb interface module (2), protocol conversion module (3) and hardware fault injection module (4), described host computer (1) is connected 3 by usb interface module (2) with protocol conversion module) connect, the ITP interface unit of described protocol conversion module (3) is connected with hardware fault injection module (4), and host computer (1) is embedded in and is useful on the application layer software module that generates fault data to be injected and protocol conversion control data;
Based on the fault filling method of JTAG, its detailed process is:
The application layer software module that is embedded with in step 1, the host computer (1) generates fault data to be injected and agreement turns
Change the control data, and according to protocol analysis and conversion order fault data described to be injected and protocol conversion control data are made up, the data communication device after then will making up is crossed usb interface module (2) and is sent to protocol conversion module (3);
Step 2, protocol conversion module (3) carry out USB buffering and usb protocol parsing to the data after making up, then to USB
The data that obtain behind the protocol analysis are carried out the ITP protocol packing, and the data after will packing are again exported to hardware fault injection module (4);
Step 3, hardware fault injection module (4) carry out obtaining JTAG fault data and order data behind the ITP protocol analysis to the data that receive, and according to described order data the JTAG fault data are injected objective chip from jtag port.
5. the fault filling method based on JTAG according to claim 4 is characterized in that described protocol conversion control data comprise: protocol conversion module (3) and ITP interface unit communication control data, ITP agreement control data and standard JTAG agreement control data.
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Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102412909B (en) * | 2010-09-26 | 2014-04-02 | 北京旋极信息技术股份有限公司 | Fault injection equipment |
| CN102769456B (en) * | 2011-05-06 | 2015-03-18 | 北京旋极信息技术股份有限公司 | Fault injection circuit capable of isolating input/output interface |
| CN102270173A (en) * | 2011-07-21 | 2011-12-07 | 哈尔滨工业大学 | Fault injection tool based on SCSI (small computer system interface) driver layer |
| CN103001818B (en) * | 2011-09-16 | 2015-09-02 | 北京旋极信息技术股份有限公司 | A kind of fault filling method and system |
| CN102624581B (en) * | 2011-12-15 | 2015-02-18 | 上海卫星工程研究所 | Connecting device of ground testing equipment of aircraft |
| CN102594589B (en) * | 2012-02-01 | 2014-05-07 | 北京经纬恒润科技有限公司 | Ethernet fault injection method, device and system |
| CN103685292A (en) * | 2013-12-20 | 2014-03-26 | 哈尔滨工业大学 | Universal device and method for protocol conversion |
| CN103913701B (en) * | 2014-04-18 | 2016-05-18 | 北京航空航天大学 | A kind of testability hookup board manufacturing method of supporting that fault is directly injected |
| CN106383303A (en) * | 2016-08-26 | 2017-02-08 | 哈尔滨工业大学 | Observation point and concurrence based fault injection simulation method and device |
| CN107526351A (en) * | 2017-07-27 | 2017-12-29 | 中国航空综合技术研究所 | A kind of universal fault filling method and its device based on JTAG |
| CN108107351A (en) * | 2017-12-06 | 2018-06-01 | 西安智多晶微电子有限公司 | Adjustment method, debugger and the system of JTAG debuggers |
| CN109033891B (en) * | 2018-06-21 | 2020-05-19 | 北京智芯微电子科技有限公司 | Equipment for security attack test of SPI interface chip and security attack test method thereof |
| CN112307695B (en) * | 2020-09-22 | 2024-03-08 | 北京九天翱翔科技有限公司 | FPGA-based universal digital circuit fault simulation injection system and method |
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| CN101334754A (en) * | 2008-08-05 | 2008-12-31 | 浙江大学 | Fault infusion based embedded system evaluation method |
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| CN100351638C (en) * | 2003-05-01 | 2007-11-28 | 中兴通讯股份有限公司 | Boundary scan testing device for integrated circuit |
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| CN101334754A (en) * | 2008-08-05 | 2008-12-31 | 浙江大学 | Fault infusion based embedded system evaluation method |
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