CN221007786U - Chip testing device - Google Patents

Abstract

The embodiment of the application provides a chip testing device. The chip testing device comprises: the testing machine comprises a power output port and a first signal output port; the switch chip is integrated with a plurality of switch circuits, one end of each switch circuit is connected to the power output port, and the other end of each switch circuit is used for connecting a chip to be tested; the switch chip comprises a first controlled port for controlling the on-off of the multi-path switch circuit, and the first controlled port is connected with a first signal output port of the testing machine. The technical scheme of the embodiment of the application can effectively reduce the occupation of tester resources on the premise of ensuring that the chips have higher same test number during testing.

Description

Chip testing device

Technical Field

The application relates to the technical field of semiconductor chips, in particular to a chip testing device.

Background

Integrated circuit semiconductor chips require Chip testing, i.e., testing of various functions of the Chip, such as CP (i.e., chip Probe) testing and FT (i.e., FINAL TEST) testing, before production, shipment, or use. Because the number of chips to be tested is huge, the same test number (i.e. the number of chips tested at the same time) is generally required to be expanded, so that the test time of the chips is saved, but the number of resources of the tester is limited.

Disclosure of utility model

The embodiment of the application provides a chip testing device which can effectively reduce the occupation of tester resources on the premise of ensuring that the chips have higher same test number during testing.

Other features and advantages of the application will be apparent from the following detailed description, or may be learned by the practice of the application.

The embodiment of the application provides a chip testing device, which comprises: the testing machine comprises a power output port and a first signal output port; the switch chip is integrated with a plurality of switch circuits, one end of each switch circuit is connected to the power output port, and the other end of each switch circuit is used for connecting a chip to be tested; the switch chip comprises a first controlled port for controlling the on-off of the multi-path switch circuit, and the first controlled port is connected with a first signal output port of the testing machine.

In some embodiments of the present application, based on the foregoing solution, the switch chip further includes a second controlled port, and the testing machine further includes a second signal output port; the second controlled port of the switch chip is connected with the second signal output port of the testing machine, and the second signal output port of the testing machine is used for transmitting clock signals to the second controlled port of the switch chip.

In some embodiments of the application, based on the foregoing, the multiple switching circuits integrated in the switching chip are connected to the same power output port on the tester.

In some embodiments of the present application, based on the foregoing solutions, the switch chip further includes a data output port, where the data output port is configured to output a synchronization signal obtained by performing shift processing on a control signal input by the first controlled port; the chip testing device comprises a plurality of switch chips, wherein the switch chips are connected through a cascade mode; the first controlled ports of the first-stage switch chips in the switch chips are connected with the first signal output port of the testing machine, and the first controlled ports of the other switch chips except the first-stage switch chips in the switch chips are connected with the data output port of the previous-stage switch chip.

In some embodiments of the present application, based on the foregoing solution, the switch chip further includes a second controlled port, and the testing machine further includes a second signal output port; the second controlled ports of the switch chips are connected to the same second signal output port of the tester, and the second signal output port is used for transmitting clock signals to the second controlled ports of the switch chips.

In some embodiments of the present application, based on the foregoing solution, the multiple switching circuits integrated in each of the switching chips are connected to the same power output port on the testing machine, and the power output ports to which the switching circuits integrated in different switching chips are connected are different.

In some embodiments of the present application, based on the foregoing solution, the test machine further includes a third signal output port, and the switch chip further includes a third controlled port; the third controlled ports of the switch chips are connected to the same third signal output port of the testing machine, and the third signal output port of the testing machine is used for transmitting enabling signals to the third controlled ports of the switch chips.

In some embodiments of the present application, based on the foregoing solution, the testing machine further includes a fourth signal output port, and the switch chip further includes a fourth controlled port; the fourth controlled ports of the switch chips are connected to the same fourth signal output port of the testing machine, and the fourth signal output port of the testing machine is used for transmitting reset signals to the fourth controlled ports of the switch chips.

In some embodiments of the present application, based on the foregoing solutions, the chip testing device includes a plurality of switch chips, where first controlled ports of the switch chips are respectively connected to different first signal output ports on the testing machine, so as to respectively receive control signals output by corresponding first signal output ports.

In some embodiments of the present application, based on the foregoing, the switch chip is disposed on a probe card disposed on a head of the tester, the probe card being configured to make contact with the chip to be tested to connect the switch circuit to the chip to be tested.

In the technical scheme provided by some embodiments of the present application, a plurality of switch circuits are integrated in a switch chip, one end of each switch circuit is connected to a power output port of a testing machine, and the other end of each switch circuit is used for connecting a chip to be tested, meanwhile, the switch chip includes a first controlled port for controlling on-off of the plurality of switch circuits, and the first controlled port is connected with a first signal output port of the testing machine, so that a control signal output by the first signal output port of the testing machine can control a designated switch circuit in the switch chip to be conducted, so that electric energy is transmitted to the chip to be tested, which is connected with the designated switch circuit, through the power output port, to perform test control on a plurality of chips to be tested, thereby ensuring that the chips have higher same test number during test, and meanwhile, because the first controlled port of the switch chip is connected with the first signal output port of the testing machine to perform control on the plurality of switch circuits, the test processing on the plurality of chips to be tested can be performed by occupying less resources of the testing machine (i.e. the signal output port of the testing machine).

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application as claimed.

Drawings

FIG. 1 shows a schematic diagram of signal transmission between a tester and a chip to be tested;

FIG. 2 shows a schematic diagram of a chip test scenario;

FIG. 3 shows a schematic diagram of a chip test scheme;

FIG. 4 shows a schematic diagram of a switching device used by the chip test scheme shown in FIG. 3;

FIG. 5 shows a signal control schematic of the chip test scheme shown in FIG. 3;

FIG. 6 shows a block diagram of a chip test apparatus according to one embodiment of the application;

FIG. 7 shows a cascading structural diagram of a multi-switch chip according to one embodiment of the application;

FIG. 8 illustrates a schematic diagram of a chip test scheme according to one embodiment of the application;

FIG. 9 shows a schematic diagram of a chip test scheme according to one embodiment of the application;

Fig. 10 shows a signal control schematic of a chip test scheme according to one embodiment of the application.

Detailed Description

Example embodiments are now described in a more complete manner with reference being made to the figures. However, the illustrated embodiments may be embodied in various forms and should not be construed as limited to only these examples; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art.

Furthermore, the described features, structures, or characteristics of the application may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the application. However, it will be recognized by one skilled in the art that the present inventive arrangements may be practiced without all of the specific details of the embodiments, that one or more specific details may be omitted, or that other methods, elements, devices, steps, etc. may be used.

The block diagrams depicted in the figures are merely functional entities and do not necessarily correspond to physically separate entities. That is, the functional entities may be implemented in software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.

It should be noted that: references herein to "a plurality" means two or more. A "chip" refers to a generic term for semiconductor device products, specifically, electronic components, circuits (especially, integrated circuits ICs, or INTEGRATED CIRCUIT), systems, etc. are integrated on a small semiconductor wafer surface to implement the functions of electronic devices.

The embodiment of the application mainly relates to a testing process of a semiconductor chip, and particularly can be applied to a CP testing process or an FT testing process of the chip. The CP test refers to a process of connecting bare chip pins with a tester through probes on a whole wafer after the wafer is manufactured and before packaging is performed, so as to perform a chip test. The main purpose of the CP test is to test the electrical performance parameters of the crystal grains, maintain the production quality and the qualification rate, improve the yield and reduce the subsequent sealing and testing cost.

The FT test is the final test of the chip after the packaging is completed, and the FT test is the test of the performance of the function and the electrical parameter of the packaged chip, so that the function and the performance index of each chip delivered from the factory can reach the design specification standard.

The chip is tested using a tester including a PEM (Pin Electronic Module, pin electronics module) board and a PSM (Power Supply Module ) board as shown in fig. 1. Wherein, PPS (Programmable Power Supply ) pin and GND pin are integrated on PSM board. Various Input and Output pins, such as a DRV (Driver) pin, an IO (Input/Output) pin, an MCW (Macro Control Work, macro control word) pin, and a High Current DRV (High Current DRV) pin, are integrated on the PEM board. The DRV pin is used for generating and outputting a digital signal, the IO pin is used for generating and receiving a digital signal, the MCW pin can be switched between two states of 0V and 5V, and the High Current DRV pin is used for providing a power supply and a measuring function. Typically, a PEM board card of the tester includes 128 DRV pins, 160 IO pins, 40 MCW pins, and 64 High Current DRV pins.

When the chip is tested by using the tester, the tester can not directly measure the chip, but as shown in fig. 2, the Probe (Probe) in the Probe Card (Probe Card) is contacted with the Pad or Bump (Bump) on the wafer of the chip to be tested to form electrical contact, and then the test signal measured by the Probe is sent to the automatic testing equipment for analysis and judgment, so as to obtain the electrical characteristic test result of each die on the wafer.

Referring to fig. 3, a schematic diagram of a chip test scheme is shown, where a probe card includes a plurality of switching devices, each corresponding to a chip to be tested (Device Under Test, DUT for short), and each controlled using an MCW pin on a tester. As shown in fig. 4, the MCW1 controls the switching device connected to the chip 1 to be tested, the MCW2 controls the switching device connected to the chip 2 to be tested, the MCW3 controls the switching device connected to the chip 3 to be tested, and the MCW4 controls the switching device connected to the chip 4 to be tested. If the control signal output by a certain MCW pin turns on the switching device, a power supply on the testing machine is output to the chip to be tested, and then the chip to be tested starts working, so that the testing work of various performances of the chip to be tested can be started.

In the test scheme shown in fig. 3, one MCW pin on the tester controls one switching device, and the multiple chips to be tested share the power output pins of the tester, if there are x chips to be tested, and y pins of the tester (such as the power output pins or other pins for outputting corresponding resources when testing) need to be shared, then the need for the tester to generate x×y MCW signals will arise. For example, in the example shown in fig. 5, if there are 8 chips to be tested, 8 MCW pins are required to output control signals, respectively.

In an actual chip test scenario, the number of chips to be tested is very huge, and if 1280 chips need to be tested and the 1280 chips need to share 4 pins of the tester, 1280×4=5120 MCW signals are needed to control, but as can be seen from fig. 1, the number of resources of the tester is limited, only 40 MCW pins are on each PEM board, and the current tester can only install 32 PEM boards at most, only 1280 MCW pins are needed when the tester is full. Therefore, the test scheme shown in fig. 3 can cause excessive occupation of the resources of the tester when increasing the number of chips tested simultaneously, and further can cause fewer chips tested simultaneously by the tester, thereby reducing the test efficiency.

Based on the above, the technical scheme of the embodiment of the application provides a new chip testing scheme, which can effectively reduce the occupation of tester resources on the premise of ensuring that the chips have higher same test number during testing so as to improve the efficiency of chip testing.

The implementation details of the technical scheme of the embodiment of the application are described in detail below:

Referring to fig. 6, a chip testing apparatus according to an embodiment of the present application includes a tester 601 and a switching chip 602. The tester 601 comprises a power output port and a first signal output port; the switch chip 602 includes a first controlled port, which may be used to control on/off of the multi-way switch circuit, and the first controlled port may be an SDI (SERIAL DATA Input ) port shown in fig. 6.

The switch chip 602 has multiple switch circuits integrated therein (fig. 6 illustrates that the switch chip 602 has 8 switch circuits integrated therein, and in other embodiments of the present application, the switch chip 602 may have more switch circuits integrated therein), one end (i.e., the S-terminal shown in fig. 6) of each switch circuit is connected to the power output port of the tester 601, and the other end (i.e., the D-terminal shown in fig. 6) is used to connect to the chip to be tested. The first controlled port of the switch chip 602 is connected with the first signal output port of the testing machine 601, and the control signal output by the first signal output port of the testing machine 601 is used for controlling the conduction of a specified switch circuit in the switch chip 602 so as to transmit electric energy to the chip to be tested connected with the specified switch circuit through the power output port for testing. For example, if the switch circuit between the S1 and the D1 is controlled to be turned on, the power output port will transmit electric energy to the chip to be tested connected to the switch circuit, and then the chip to be tested starts to work, so that the test work of each performance of the chip to be tested can be started.

It should be noted that the specified switch circuit may be one switch circuit in the switch chip 602, or may be a plurality of switch circuits, that is, the switch circuits in the switch chip 602 may be turned on by 0, 1, multiple or all at the same time. The multiple switching circuits integrated in the switching chip 602 may be connected to the same power output port on the tester 601 as shown in fig. 6, so that excessive occupation of the tester ports can be saved, and in other embodiments of the present application, if the power output ports of the tester are more idle, multiple switching circuits integrated in the switching chip 602 may be connected to different power output ports.

In the chip testing apparatus shown in fig. 6, the switch chip 602 is used to implement test control on multiple chips to be tested, so that a higher number of identical tests is ensured during chip testing, and meanwhile, as the first controlled port of the switch chip 602 is connected with the first signal output port of the tester to implement control on multiple switch circuits, occupation of tester resources (i.e., signal output ports of the tester) can be reduced, and further, efficiency of chip testing can be improved.

In some alternative embodiments, with continued reference to fig. 6, the tester 601 may further include a second signal output port, and the switch chip 602 may further include a second controlled port, which may be the CLK (Clock) port shown in fig. 6. And the second controlled port of the switching chip 602 may be connected to the second signal output port of the tester 601, and the second signal output port of the tester 601 may transmit a clock signal to the second controlled port of the switching chip 602.

In some alternative embodiments, with continued reference to FIG. 6, the tester 601 may also include a third signal output port, and the switch chip 602 may also include a third controlled port, which may be the CS port shown in FIG. 6. And the third controlled port of the switching chip 602 may be connected to the third signal output port of the tester 601, and the third signal output port of the tester 601 may transmit an enable signal to the third controlled port of the switching chip 602. The switch chip 602 does not operate until the enable signal is active (e.g., may be set active low).

In some alternative embodiments, with continued reference to FIG. 6, the tester 601 may also include a fourth signal output port, and the switch chip 602 may also include a fourth controlled port, which may be the V _L port shown in FIG. 6. And the fourth controlled port of the switch chip 602 may be connected to the fourth signal output port of the testing machine 601, and further the fourth signal output port of the testing machine 601 may transmit a reset signal to the fourth controlled port of the switch chip 602, where the reset signal is used to perform a hardware reset process on the switch chip 602, and after the hardware reset process is performed on the switch chip 602, all the switch circuits may be in an off state.

In some alternative embodiments, as shown in fig. 6, the switch chip 602 includes an SPI (SERIAL PERIPHERAL INTERFACE ) that can provide the various controlled ports described above to connect with corresponding ports of the tester 601.

In some alternative embodiments, the switch chip 602 may further include a data Output port, which may be an SDO (SERIAL DATA Output) port as shown in fig. 6. The data output port is configured to output a synchronization signal obtained by shifting a control signal input from the first controlled port of the switch chip 602. Specifically, the switching chip 602 may perform a shift process on a control signal input from a first controlled port (i.e., SDI port), and then output a synchronization signal obtained after the shift process through a data output port (i.e., SDO port), and may shift 8 bits or 16 bits or the like when performing the shift process.

Based on the technical solutions of the foregoing embodiments, in some optional embodiments of the present application, the cascade connection of multiple switch chips may be implemented by using the data output ports of the switch chips 602, so that the purpose of testing more chips by using fewer tester resources may be implemented. Specifically, the first controlled port of the first stage switch chip among the plurality of switch chips is connected to the first signal output port of the tester 601 (for example, the switch chip 602 shown in fig. 6 is referred to as the first stage switch chip), and the first controlled ports (i.e., SDI ports) of the other switch chips among the plurality of switch chips except for the first stage switch chip are connected to the data output port (i.e., SDO ports) of the preceding stage switch chip. Two switch chips 602a and 602b are described below with reference to fig. 7.

As shown in fig. 7, the switch chip 602a is a first-stage switch chip, the switch chip 602b is a second-stage switch chip, and then the connection manner of the switch chip 602a and the tester 601 is as shown in fig. 6, that is, the first controlled port (i.e., SDI port) of the switch chip 602a is connected to the first signal output port (denoted as DRV1 in fig. 7) of the tester 601, the second controlled port (i.e., CLK port) of the switch chip 602a is connected to the second signal output port (denoted as DRV2 in fig. 7) of the tester 601, and the third controlled port (i.e., CS port) of the switch chip 602a is connected to the third signal output port (denoted as CS in fig. 7) of the tester 601, and the fourth controlled port (i.e., V _L port) of the switch chip 602a is connected to the fourth signal output port (denoted as V _L in fig. 7) of the tester 601.

Since the switching chip 602b is a second stage switching chip, the first controlled port (i.e., SDI port) of the switching chip 602b is connected to the data output port (i.e., SDO port) of the first stage switching chip (i.e., switching chip 602 a). In this case, since the signal output by the SDO port of the switch chip 602a is a synchronization signal obtained by shifting the control signal input by the SDI port of the switch chip 602a, the switch chip 602b may also control the switch circuit included in the switch chip 602b according to the synchronization signal obtained by shifting, thereby controlling the corresponding chip to be tested.

In some alternative embodiments, if the chip test apparatus includes a plurality of switch chips, the second controlled ports (i.e., CLK ports) of the plurality of switch chips may be connected to the same second signal output port of the tester 601, and thus the second signal output port of the tester 601 may simultaneously transmit clock signals to the second controlled ports of the plurality of switch chips, which may reduce the occupation of tester resources. As shown in fig. 7 in particular, the CLK ports of the switch chips 602a and 602b are connected and then connected to one port of the tester (shown as DRV2 in fig. 7).

In some alternative embodiments, if the chip test apparatus includes a plurality of switch chips, the third controlled ports (i.e., CS ports) of the plurality of switch chips may be connected to the same third signal output port of the tester 601, and thus the third signal output port of the tester 601 may simultaneously transmit the enable signal to the third controlled ports of the plurality of switch chips, which may reduce the occupation of tester resources. As shown in fig. 7 in particular, the CS ports of the switch chips 602a and 602b are connected and then connected to one port (denoted CS in fig. 7) of the tester.

In some alternative embodiments, if the chip testing apparatus includes a plurality of switch chips, the fourth controlled ports (i.e., V _L ports) of the plurality of switch chips may be connected to the same fourth signal output port of the tester 601, and thus the fourth signal output port of the tester 601 may simultaneously transmit the reset signal to the fourth controlled ports of the plurality of switch chips, which may reduce the occupation of tester resources. As shown in fig. 7 in particular, the V _L ports of the switch chips 602a and 602b are connected and then connected to one port of the tester (denoted as V _L in fig. 7).

In some alternative embodiments, if the chip test apparatus includes multiple switch chips, the multiple switch circuits integrated in each switch chip may be connected to the same power output port on the tester 601 as shown in fig. 6, which may save excessive occupation of the tester ports, and the power output ports to which the switch circuits integrated in different switch chips are connected may be different, which may be connected to different switch chips using different power output ports of the tester 601. Of course, in other embodiments of the present application, if the power output ports of the tester are more idle, then multiple switch circuits integrated in the switch chip may also be connected to different power output ports.

In one embodiment of the present application, if the chip testing apparatus includes a plurality of switch chips, the plurality of switch chips may be connected in a cascade manner as shown in fig. 7, but may be separately connected to the testing machine 601 in a manner similar to that shown in fig. 6, in which case the plurality of switch chips are independent from each other, and the testing machine may separately control the plurality of switch chips. The technical scheme of the embodiment can reduce the occupation of tester resources (namely the signal output port of the tester) on the premise of ensuring that the chips have higher same test number during testing, and further can improve the efficiency of testing the chips.

In some alternative embodiments, the switch chip in the present application may be disposed on a probe card as shown in fig. 2, where the probe card is disposed on a machine head of the testing machine, and after the probe card contacts with the chip to be tested, a switch circuit in the switch chip may be connected to the chip to be tested, so that control over the switch circuit may be implemented by the control manner in the foregoing embodiments, and further, test processing of the chip to be tested is implemented.

In order to further highlight the advantages of the technical solution according to the embodiment of the present application, the technical solution according to the preferred embodiment of the present application will be described again with reference to fig. 8 to 10 by comparing the technical solution according to the embodiment shown in fig. 3.

As shown in fig. 8, the probe card includes a plurality of switch chips, which may be connected in a cascade mode as shown in fig. 7, each of the switch chips includes a plurality of switch circuits, and each of the switch circuits is connected to one chip to be tested, so that each of the switch chips corresponds to one chip set to be tested. Two signal output ports (namely DRV1 and DRV 2) can be used in the testing machine to provide clock signals and control signals for the first-stage switch chip, so that the first-stage switch chip can shift the control signals and output the control signals to the second-stage switch chip, the second-stage switch chip shifts the received signals again and outputs the signals to the third-stage switch chip, and the like, so that the control of a plurality of switch chips through a small amount of testing machine resources (namely signal output ports) can be realized, and each switch chip is connected to a plurality of chips to be tested, and then the test control of a plurality of chips can be realized.

Specifically, as shown in fig. 9, 5 switch chips (i.e., switch chip 902, switch chip 903, switch chip 904, switch chip 905, and switch chip 906) are exemplified. The switch chip 902 is a first-stage switch chip, the switch chip 903 is a second-stage switch chip, the switch chip 904 is a third-stage switch chip, the switch chip 905 is a fourth-stage switch chip, and the switch chip 906 is a fifth-stage switch chip. The connection between the switch chip 902 and the tester 901 is that the SDI port of the switch chip 902 is connected to the first signal output port (denoted as DRV1 in fig. 9) of the tester 901, the CLK port of the switch chip 902 is connected to the second signal output port (denoted as DRV2 in fig. 9) of the tester 901, and the CS port of the switch chip 902 is connected to the third signal output port (denoted as MCW1 in fig. 9) of the tester 901; while each of the switching circuits included in the switching chip 902 has one end connected to a power output port (denoted by PPS1 in fig. 9) of the tester 901 and the other end connected to a chip to be tested.

It should be noted that, in fig. 9, other controlled ports of the switch chip, such as the V _L port, may refer to the technical solution of the foregoing embodiment for the connection mode of the port not shown, or may be set according to actual needs, for example, the V _L port of the switch chip 902 may be connected to a signal output port of the tester 901.

The switching chip 903 shown in fig. 9 is a second stage switching chip, and thus the SDI port of the switching chip 903 is connected to the SDO port of the first stage switching chip (i.e., switching chip 902). In this case, since the signal output from the SDO port of the switch chip 902 is a synchronization signal obtained by shifting the control signal input from the SDI port of the switch chip 902, the switch chip 903 may control the switch circuit included in the switch chip 903 according to the synchronization signal obtained by shifting, thereby controlling the corresponding chip to be tested.

The switching chip 904 shown in fig. 9 is a third stage switching chip, and thus the SDI port of the switching chip 904 is connected to the SDO port of the second stage switching chip (i.e., the switching chip 903). In this case, since the signal output from the SDO port of the switch chip 903 is a synchronization signal obtained by shifting the control signal input from the SDI port of the switch chip 903, the switch chip 904 may control the switching circuit included in the switch chip 904 according to the synchronization signal obtained by shifting, thereby controlling the corresponding chip to be tested.

The switching chip 905 shown in fig. 9 is a fourth stage switching chip, and thus the SDI port of the switching chip 905 is connected to the SDO port of the third stage switching chip (i.e., the switching chip 904). In this case, since the signal output from the SDO port of the switch chip 904 is a synchronization signal obtained by shifting the control signal input from the SDI port of the switch chip 904, the switch chip 905 may control the switch circuit included in the switch chip 905 according to the shifted synchronization signal, thereby controlling the corresponding chip to be tested.

The switching chip 906 shown in fig. 9 is a fifth-stage switching chip, and thus the SDI port of the switching chip 906 is connected to the SDO port of the fourth-stage switching chip (i.e., switching chip 905). In this case, since the signal output from the SDO port of the switch chip 905 is a synchronization signal obtained by shifting the control signal input from the SDI port of the switch chip 905, the switch chip 906 can also control the switching circuit included in the switch chip 906 according to the synchronization signal obtained by shifting, thereby controlling the corresponding chip to be tested.

Meanwhile, in the embodiment shown in fig. 9, the CLK ports of the 5 switch chips may be connected and then connected to one port (represented as DRV2 in fig. 9) of the tester. And the CS ports of the 5 switch chips may be connected and then connected to one port of the tester (denoted MCW1 in fig. 9). In addition, the power output ports of the test machine to which the integrated switching circuits in the 5 switching chips are connected may be different, for example, the power output port to which the integrated switching circuits in the switching chip 902 are connected is PPS1, the power output port to which the integrated switching circuits in the switching chip 903 are connected is PPS2, the power output port to which the integrated switching circuits in the switching chip 904 are connected is PPS3, the power output port to which the integrated switching circuits in the switching chip 905 are connected is PPS4, and the power output port to which the integrated switching circuits in the switching chip 906 are connected is PPS5 in fig. 9.

In the test schemes shown in fig. 8 and 9, a plurality of switch chips are connected in a cascade mode, each switch chip includes a plurality of switch circuits, and each switch chip corresponds to a chipset to be tested, and if 5 switch chips are used and each switch chip includes 8 switch circuits, test control of 5×8=40 chips can be achieved through two DRV ports of the tester. If the test control is performed on 8 chips to be tested, as shown in fig. 10, only two DRV ports of the tester need to be used to output clock signals and control signals under the condition of not considering the power output ports, and compared with the technical scheme shown in fig. 3, the occupation of tester resources is effectively reduced.

In performing the chip test using the embodiments shown in fig. 6 to 10, the first signal output port of the tester may output a control signal of a multi-bit command, each of which is used to control one switching circuit. After the first signal output port transmits the control signal to the first controlled port of the switch chip, a designated switch circuit in the switch chip can be controlled to be conducted, and then electric energy can be transmitted to the chip to be tested connected with the designated switch circuit through the power output port of the testing machine so as to test the chip to be tested.

It should be noted that, the number of bit commands in the control signal is consistent with the number of switch circuits included in the switch chip, for example, the switch chip includes 8 switch circuits, and then the control signal includes 8 bit commands, each bit command is used for controlling one switch circuit.

Alternatively, the command in the control signal may be to control the switching circuit to be on at a high level and to control the switching circuit to be off at a low level; conversely, the command in the control signal may be to control the switching circuit to be on at a low level and to control the switching circuit to be off at a high level.

Alternatively, when the chip to be tested is tested, the CP test may be performed, or the FT test may be performed.

Therefore, the chip testing scheme provided by the embodiment of the application can reduce the occupation of tester resources (namely the signal output port of the tester) on the premise of ensuring that the chips have higher same test number during testing, thereby improving the efficiency of chip testing. And because the switch chip can use serial signals to control, compared with parallel signals, a large number of control signal wires in the probe card can be reduced, so that the degree of mutual crosstalk of signals can be reduced, the design period of the probe card can be shortened, and the development cost of the probe card can be reduced.

It should be understood that other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the embodiments disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. The application is not limited to the precise construction which has been described above and shown in the drawings, and various modifications and changes may be made without departing from the scope thereof.

Claims (10)

1. A chip testing apparatus, comprising:

The testing machine comprises a power output port and a first signal output port;

The switch chip is integrated with a plurality of switch circuits, one end of each switch circuit is connected to the power output port, and the other end of each switch circuit is used for connecting a chip to be tested;

The switch chip comprises a first controlled port for controlling the on-off of the multi-path switch circuit, and the first controlled port is connected with a first signal output port of the testing machine.

2. The chip test apparatus of claim 1, wherein the switch chip further comprises a second controlled port, and the tester further comprises a second signal output port;

The second controlled port of the switch chip is connected with the second signal output port of the testing machine, and the second signal output port of the testing machine is used for transmitting clock signals to the second controlled port of the switch chip.

3. The chip test apparatus of claim 1, wherein the multiple switching circuits integrated in the switching chip are connected to the same power output port on the tester.

4. The chip testing device according to claim 1, wherein the switch chip further comprises a data output port, and the data output port is configured to output a synchronization signal obtained by shifting the control signal input by the first controlled port;

The chip testing device comprises a plurality of switch chips, wherein the switch chips are connected through a cascade mode; the first controlled ports of the first-stage switch chips in the switch chips are connected with the first signal output port of the testing machine, and the first controlled ports of the other switch chips except the first-stage switch chips in the switch chips are connected with the data output port of the previous-stage switch chip.

5. The chip testing device of claim 4, wherein the switch chip further comprises a second controlled port, and the tester further comprises a second signal output port;

The second controlled ports of the switch chips are connected to the same second signal output port of the tester, and the second signal output port is used for transmitting clock signals to the second controlled ports of the switch chips.

6. The chip test apparatus of claim 4, wherein the multiple switching circuits integrated in each of the switching chips are connected to a same power output port on the tester, and the power output ports to which the switching circuits integrated in different switching chips are connected are different.

7. The chip test apparatus of claim 4, wherein the tester further comprises a third signal output port, and the switch chip further comprises a third controlled port;

The third controlled ports of the switch chips are connected to the same third signal output port of the testing machine, and the third signal output port of the testing machine is used for transmitting enabling signals to the third controlled ports of the switch chips.

8. The chip test apparatus of claim 4, wherein the tester further comprises a fourth signal output port, and the switch chip further comprises a fourth controlled port;

The fourth controlled ports of the switch chips are connected to the same fourth signal output port of the testing machine, and the fourth signal output port of the testing machine is used for transmitting reset signals to the fourth controlled ports of the switch chips.

9. The device according to claim 1, wherein the device comprises a plurality of switch chips, and the first controlled ports of the switch chips are respectively connected with different first signal output ports of the tester to respectively receive the control signals output by the corresponding first signal output ports.

10. The chip testing apparatus according to any one of claims 1 to 9, wherein the switch chip is provided on a probe card provided on a head of the tester, the probe card being for making contact with the chip to be tested to connect the switch circuit to the chip to be tested.