CN114740339A - Rapid integrated test method of integrated circuit based on independent instrument - Google Patents

Rapid integrated test method of integrated circuit based on independent instrument Download PDF

Info

Publication number
CN114740339A
CN114740339A CN202210567119.1A CN202210567119A CN114740339A CN 114740339 A CN114740339 A CN 114740339A CN 202210567119 A CN202210567119 A CN 202210567119A CN 114740339 A CN114740339 A CN 114740339A
Authority
CN
China
Prior art keywords
circuit
test
digital
driving
upper computer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210567119.1A
Other languages
Chinese (zh)
Inventor
赵臣龙
张超
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lima Optoelectronic Technology Beijing Co ltd
Original Assignee
Lima Optoelectronic Technology Beijing Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lima Optoelectronic Technology Beijing Co ltd filed Critical Lima Optoelectronic Technology Beijing Co ltd
Priority to CN202210567119.1A priority Critical patent/CN114740339A/en
Publication of CN114740339A publication Critical patent/CN114740339A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

The invention relates to a rapid integrated test method of an integrated circuit based on an independent instrument, which tests a DUT (device under test) by controlling a test system through an upper computer, wherein the test system comprises the upper computer, a signal generator, an oscilloscope, a universal meter, a program control power supply, a lower computer, a digital drive circuit, a relay circuit and an interface board. According to the invention, through designing the digital driving circuit, the relay circuit and the interface board, the digital driving circuit, the relay circuit and the interface board are matched with the upper computer, the lower computer and various instruments for use, so that abundant testing functions can be realized, automatic testing of ATE can be realized quickly and at low cost through the external instruments, the automatic testing device is flexible and convenient, and different types of instruments can be configured quickly according to actual testing requirements.

Description

Rapid integrated test method of integrated circuit based on independent instrument
Technical Field
The invention relates to the field of integrated circuit testing, in particular to a rapid integrated testing method of an integrated circuit based on an independent instrument.
Background
At present, the integrated circuit Test usually uses ATE Equipment, which is an abbreviation of Automatic Test Equipment, and the semiconductor industry means an Integrated Circuit (IC) Automatic tester for detecting the integrity of the IC function. However, the types of integrated circuit chips are various, and the parameters to be tested are not enumerated, so that the types of corresponding ATE devices are also more. However, there are not small differences in the performance of different types, brands, and home and foreign ATE equipment, and the price of ATE equipment is generally expensive. Therefore, in the integrated circuit test, for some types of chips and parameters, sometimes no ten-branch appropriate and reliable ATE equipment exists, or when the comparison with the ATE test result is needed, a special test platform needs to be built by using an instrument. However, the manual construction of the test platform has high requirements on the technical capability of technicians, and a slightly complex circuit can cause more lapping cables, errors are easy to occur, the test is complex, the data recording is inconvenient, and the efficiency is extremely low during batch test.
Disclosure of Invention
The invention aims to provide a rapid integrated test method of an integrated circuit based on an independent instrument.
The invention realizes the purpose through the following technical scheme: a rapid integrated test method of an integrated circuit based on an independent instrument is characterized in that a test system is controlled by an upper computer to test a DUT;
the test system comprises an upper computer, a signal generator, an oscilloscope, a universal meter, a program control power supply, a lower computer, a digital drive circuit, a relay circuit and an interface board;
the upper computer is connected with the signal generator, the oscilloscope, the universal meter and the program control power supply, and controls the relevant equipment to perform specified actions through a standard VISA instrument control instruction;
the upper computer is connected with the serial port of the lower computer to realize the control of the relay circuit; the upper computer sends a self-defined digital logic driving signal by controlling the digital driving circuit;
the signal generator, the oscilloscope, the universal meter, the programmable power supply and the digital driving circuit are all connected into a relay circuit, and the relay circuit is opened or closed by receiving a control instruction of a lower computer;
controlling the output waveform of the signal generator, the output voltage amplitude of the programmable power supply and the driving signal of the digital driving circuit through the upper computer, and reading back and storing test data and graphs of the oscilloscope and the voltage and current test results of the universal meter;
the interface board collects all the test signals on the relay circuit board, and the interface board is connected with the DUT.
Furthermore, the upper computer is connected with the signal generator, the oscilloscope, the universal meter and the program control power supply through the USB cable.
Further, the digital driving circuit sends digital control signals of IIC and SPI protocols or customized digital logic driving signals within 32 paths.
Further, the interface board comprises a top plate and 14 slots.
Furthermore, the relay circuit realizes that any channel in the 32 channels is respectively connected to two common points, and a universal meter, an oscilloscope, a signal generator and a programmable power supply are connected to the common points.
Furthermore, the digital driving circuit realizes that any 32 channels are switched to the corresponding 32 channels of driving circuits through a built-in relay switching circuit and a driving signal, and the programmed control driving level is 3.3V or 5V.
Furthermore, the digital driving circuit realizes waveform logic required by rapid driving through built-in RAM resources.
Compared with the prior art, the rapid integrated test method of the integrated circuit based on the independent instrument has the advantages that: through designing digital drive circuit, relay circuit, interface board, the cooperation is used to host computer, next computer and various instruments, can realize abundanter test function, can be through external instrument, the automatic test of the realization ATE of quick low-cost, and nimble convenience, the test demand according to the reality that can be quick disposes the instrument of different grade type.
Drawings
Fig. 1 is an architecture diagram of a test system.
Fig. 2 is a schematic diagram of a hardware configuration.
Fig. 3 is a schematic diagram of a relay master control circuit.
Fig. 4 is a schematic diagram of a relay circuit on-board voltage and current test circuit.
Fig. 5 is a schematic diagram of a relay circuit interface.
Fig. 6 is a schematic diagram of a single relay circuit.
Fig. 7 is a 16-way relay drive circuit.
Fig. 8 is a schematic diagram of a digital drive circuit master control circuit.
FIG. 9 is a schematic diagram of a slave chip and RAM circuitry of the digital driver circuit.
Fig. 10 is a single relay circuit schematic of a digital driver circuit.
Fig. 11 is a schematic diagram of a 32-way digital driving circuit.
FIG. 12 is a schematic diagram of a top plate master control circuit.
FIG. 13 is a schematic diagram of a top plane board serial communications circuit.
FIG. 14 is a schematic view of a top plate meter interface.
Fig. 15 is a schematic view of the socket 1 interface.
Detailed Description
Referring to fig. 1, the test system includes an upper computer, a signal generator, an oscilloscope, a multimeter, a programmable power supply, a lower computer, a digital driving circuit, a relay circuit, and an interface board; one or more signal generators, oscilloscopes, universal meters and programmable power supplies,
the upper computer is connected with the signal generator, the oscilloscope, the universal meter and the program control power supply through a USB cable, and controls the relevant equipment to perform specified actions through a standard VISA instrument control instruction;
the upper computer is connected with the serial port of the lower computer to realize the control of the relay circuit; for some special digital signals, the upper computer sends digital control signals of IIC and SPI protocols or customized digital logic driving signals within 32 channels by controlling a digital driving circuit, and the hardware structure is shown in FIG. 2, wherein slots 1-7 can realize the test of channels 1-32, and slots 8-14 can realize the test of channels 33-64.
The signal generator, the oscilloscope, the universal meter, the programmable power supply and the digital driving circuit are all connected into a relay circuit, and the relay circuit is opened or closed by receiving a control instruction of a lower computer; thereby realizing the required hardware test circuit structure;
controlling the output waveform of the signal generator, the output voltage amplitude of the programmable power supply and the driving signal of the digital driving circuit through the upper computer, and reading back and storing test data and graphs of the oscilloscope and the voltage and current test results of the universal meter; thereby achieving the required testing requirements.
The interface board collects all the test signals on the relay circuit board, and the interface board is connected with a DUT (device under test).
The interface board comprises a top plate and slots, the number of the slots is 14, the functional board card corresponding to each slot is shown in figure 2, slot 1 is a relay circuit multimeter channel 1-32, slot 2 is a relay circuit oscilloscope channel 1-32, slot 3 is a relay circuit signal generator channel 1-32, slot 4 is a digital drive circuit channel 1-32, slot 5 is a relay circuit current detection channel 1-16, slot 6 is a relay circuit current detection channel 17-32, slot 7 is a relay circuit program control power supply channel 1-32, slot 8 is a relay circuit multimeter channel 33-64, slot 9 is a relay circuit oscilloscope channel 33-64, slot 10 is a relay circuit signal generator channel 33-64, slot 11 is a digital drive circuit channel 33-64, and slot 12 is a relay circuit current detection channel 33-48, slot 13 is relay circuit current sense channels 49-64 and slot 14 is relay circuit programmable power channels 33-64. The interface of slot 1 is shown in fig. 15, and other slot principles are similar, so that the illustration is not needed.
And the serial port module is communicated with the upper computer, so that the instruction of the upper computer can be received, and the instruction is analyzed and sent to the relay circuit or the digital driving circuit. And after the action is finished, informing the upper computer to control the corresponding instrument to test or drive. Schematic views of the top plate are shown in fig. 12-14.
The relay circuit can realize that any channel in the 32-channel channels is respectively connected to two common points, and can be connected with a universal meter, an oscilloscope, a signal generator and a program control power supply through the common points. The schematic diagram of the relay circuit is shown in fig. 3 to 7, wherein the main control chip in fig. 3 is responsible for communicating with the top plate main control chip through an interface (fig. 5), receiving instructions, and controlling 64-path relays (fig. 6) through 4 sets of relay driving circuits (fig. 7), so that any 32-path channel can be switched to 2 public ports, and the 32-path voltage can be rapidly tested with lower precision through the voltage and circuit testing circuit (fig. 4) carried by the relay board, and the high-precision test needs to be realized by an external voltmeter.
The digital driving circuit can realize that any 32 channels are switched to the corresponding 32 channels of driving circuits through the built-in relay switching circuit and the driving signals, and can program the driving level to be 3.3V or 5V. The digital driving circuit realizes waveform logic required by rapid driving through built-in RAM resources. Fig. 8 to 11 show schematic diagrams of digital driving circuits, where fig. 8 shows a main control chip on a driving board, which receives a motherboard signal and controls 32 relays (fig. 10), and the 32 relays are controlled to connect or disconnect 32 driving signals (fig. 11) to or from a DUT. Fig. 9 is a slave control chip, which receives the control command from the master control chip (fig. 8), stores the required driving command in the RAM, conveniently and quickly reads and generates a driving signal, and sends the driving signal to the chip to be tested through the relay via the driver (fig. 11).
The invention can realize abundant test functions by designing the digital driving circuit, the relay circuit and the interface board and matching with the upper computer, the lower computer and various instruments, can realize automatic test of ATE quickly and at low cost through the external instrument, is flexible and convenient, and can quickly configure different types of instruments according to actual test requirements.
While there have been shown and described what are at present considered the fundamental principles and essential features of the invention and its advantages, it will be apparent to those skilled in the art that the invention is not limited to the details of the foregoing exemplary embodiments, but is capable of other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.

Claims (7)

1. The rapid integrated test method of the integrated circuit based on the independent instrument is characterized in that: controlling a test system to test the DUT through the upper computer;
the test system comprises an upper computer, a signal generator, an oscilloscope, a universal meter, a program control power supply, a lower computer, a digital drive circuit, a relay circuit and an interface board;
the upper computer is connected with the signal generator, the oscilloscope, the universal meter and the program control power supply, and controls the relevant equipment to perform specified actions through a standard VISA instrument control instruction;
the upper computer is connected with the serial port of the lower computer to realize the control of the relay circuit; the upper computer sends a self-defined digital logic driving signal by controlling the digital driving circuit;
the signal generator, the oscilloscope, the universal meter, the programmable power supply and the digital driving circuit are all connected into a relay circuit, and the relay circuit is opened or closed by receiving a control instruction of a lower computer;
controlling the output waveform of the signal generator, the output voltage amplitude of the programmable power supply and the driving signal of the digital driving circuit through the upper computer, and reading back and storing test data and graphs of the oscilloscope and the voltage and current test results of the universal meter;
the interface board collects all the test signals on the relay circuit board, and the interface board is connected with the DUT.
2. A method for rapid integrated test of an integrated circuit based on a separate instrument and meter according to claim 1, characterized in that: the upper computer is connected with the signal generator, the oscilloscope, the universal meter and the program control power supply through the USB cable.
3. The method for rapid integrated test of an independent instrument based integrated circuit according to claim 1, wherein: the digital driving circuit sends digital control signals of IIC and SPI protocols or digital logic driving signals within 32 self-defined paths.
4. The method for rapid integrated test of an independent instrument based integrated circuit according to claim 1, wherein: the interface board comprises a top plate and 14 slots.
5. The method for rapid integrated test of an independent instrument based integrated circuit according to claim 1, wherein: the relay circuit realizes that any channel in the 32 channels is respectively connected to two common points, and a universal meter, an oscilloscope, a signal generator and a program control power supply are connected to the common points.
6. The method for rapid integrated test of an independent instrument based integrated circuit according to claim 1, wherein: the digital driving circuit realizes that any 32 channels are switched to the corresponding 32 channels of driving circuits through a built-in relay switching circuit and a driving signal, and the program control driving level is 3.3V or 5V.
7. The method for rapid integrated test of an independent instrument based integrated circuit according to claim 1, wherein: the digital driving circuit realizes waveform logic required by rapid driving through built-in RAM resources.
CN202210567119.1A 2022-05-24 2022-05-24 Rapid integrated test method of integrated circuit based on independent instrument Pending CN114740339A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210567119.1A CN114740339A (en) 2022-05-24 2022-05-24 Rapid integrated test method of integrated circuit based on independent instrument

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210567119.1A CN114740339A (en) 2022-05-24 2022-05-24 Rapid integrated test method of integrated circuit based on independent instrument

Publications (1)

Publication Number Publication Date
CN114740339A true CN114740339A (en) 2022-07-12

Family

ID=82286727

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210567119.1A Pending CN114740339A (en) 2022-05-24 2022-05-24 Rapid integrated test method of integrated circuit based on independent instrument

Country Status (1)

Country Link
CN (1) CN114740339A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115792477A (en) * 2023-02-06 2023-03-14 北京京瀚禹电子工程技术有限公司 Automatic test system based on high-precision instrument
CN115792768A (en) * 2023-01-04 2023-03-14 俐玛光电科技(北京)有限公司 Monitoring method and device for integrated circuit test and electronic equipment
CN117607664A (en) * 2024-01-24 2024-02-27 俐玛光电科技(北京)有限公司 Pulse current testing circuit and testing method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104345262A (en) * 2014-10-27 2015-02-11 华南农业大学 Universal circuit board test system
CN107037300A (en) * 2017-06-22 2017-08-11 沈阳工程学院 A kind of power system Multi-channel data acquisition equipment
CN107942175A (en) * 2017-12-21 2018-04-20 深圳市中联宇航科技有限公司 A kind of data collector Auto-Test System
CN113655368A (en) * 2021-08-06 2021-11-16 湖北三江航天万峰科技发展有限公司 Batch detection device for bus interface boards

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104345262A (en) * 2014-10-27 2015-02-11 华南农业大学 Universal circuit board test system
CN107037300A (en) * 2017-06-22 2017-08-11 沈阳工程学院 A kind of power system Multi-channel data acquisition equipment
CN107942175A (en) * 2017-12-21 2018-04-20 深圳市中联宇航科技有限公司 A kind of data collector Auto-Test System
CN113655368A (en) * 2021-08-06 2021-11-16 湖北三江航天万峰科技发展有限公司 Batch detection device for bus interface boards

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115792768A (en) * 2023-01-04 2023-03-14 俐玛光电科技(北京)有限公司 Monitoring method and device for integrated circuit test and electronic equipment
CN115792477A (en) * 2023-02-06 2023-03-14 北京京瀚禹电子工程技术有限公司 Automatic test system based on high-precision instrument
CN117607664A (en) * 2024-01-24 2024-02-27 俐玛光电科技(北京)有限公司 Pulse current testing circuit and testing method
CN117607664B (en) * 2024-01-24 2024-04-02 俐玛光电科技(北京)有限公司 Pulse current testing circuit and testing method

Similar Documents

Publication Publication Date Title
CN114740339A (en) Rapid integrated test method of integrated circuit based on independent instrument
US20240094289A1 (en) Interposer circuit
US7609081B2 (en) Testing system and method for testing an electronic device
US6560739B1 (en) Mechanism for enabling compliance with the IEEE standard 1149.1 for boundary-scan designs and tests
US6642736B2 (en) Tester for semiconductor integrated circuits and method for testing semiconductor integrated circuits
CN101158708B (en) Multiple chips automatic test method based on programmable logic device
US20190346503A1 (en) Method and apparatus for device access port selection
US11041905B2 (en) Combinatorial serial and parallel test access port selection in a JTAG interface
US20110202799A1 (en) Process for making an electric testing of electronic devices
CN115932540B (en) Multi-channel multifunctional chip testing machine and testing method
US6747473B2 (en) Device under interface card with on-board testing
CN107271879B (en) Semiconductor chip aging test device and method
CN109884517B (en) Chip to be tested and test system
EP0535617A2 (en) Method for testing the electrical parameters of inputs and outputs of integrated circuits
CN112345925A (en) Scan chain control circuit
CN115267481A (en) Chip test circuit and chip test device
KR20070045501A (en) Testing device for a plurality of display modules
CN217385736U (en) MCU's ATE equipment and system thereof
EP2093580B1 (en) Supply current based testing of CMOS output stages
KR20100076445A (en) Probe card for testing multi-site chips
US5680407A (en) Device for testing multiple pulling resistor connections using a single test point
CN110780183B (en) Interface circuit for JTAG boundary scan test
US11226372B2 (en) Portable chip tester with integrated field programmable gate array
US7187193B2 (en) MCU test device for multiple integrated circuit chips
CN112345924A (en) Scan chain control circuit

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20220712