CN117607664B - Pulse current testing circuit and testing method - Google Patents
Pulse current testing circuit and testing method Download PDFInfo
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- CN117607664B CN117607664B CN202410097571.5A CN202410097571A CN117607664B CN 117607664 B CN117607664 B CN 117607664B CN 202410097571 A CN202410097571 A CN 202410097571A CN 117607664 B CN117607664 B CN 117607664B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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Abstract
The application provides a pulse current test circuit and a test method, which relate to the field of integrated circuit test, wherein the circuit comprises a first control unit, a second control unit, a first MOS tube, a second MOS tube, a third MOS tube, a first resistor, a second resistor and a controller: the first MOS tube is grounded at the source electrode, the drain electrode is respectively connected with one end of the first resistor and the source electrode of the third MOS tube, the other end of the first resistor is connected with an output pin of the chip to be tested, and the grid electrode of the first MOS tube is connected with the first control unit; the source electrode of the second MOS tube is grounded, the drain electrode of the second MOS tube is respectively connected with one end of the second resistor and the grid electrode of the third MOS tube, the other end of the second resistor is respectively connected with the drain electrode of the third MOS tube and an external power supply, and the grid electrode of the second MOS tube is connected with the second control unit. Through the circuit, an additional special board card is not needed, the pulse current can be tested through the digital channel board card and the voltage acquisition board card, and the additional test cost which is required to be increased for designing the special board card is avoided.
Description
Technical Field
The present application relates to the field of integrated circuit testing, and in particular, to a pulse current testing circuit and a testing method.
Background
In the chip test of the driving type and the gate type, acquisition of parameters such as a short-circuit output current of the chip requires the use of a pulse current. In the process of using the pulse current, since the pulse current is generally large, strict limitation is generally required for the test time, and if the test time is exceeded, heat generated by the large current for a long time may cause the chip to be tested to burn out. That is, in order to secure the safety of the chip under test, a pulse current having a small pulse width needs to be used in the chip test.
In the related art, in order to obtain a pulse current with a smaller pulse width, a special board card is designed by related staff to meet the test requirement, but the special board card can meet the test requirement, but the design of the special board card requires additional test cost, which is not beneficial to chip test.
Disclosure of Invention
The embodiment of the application at least provides a pulse current testing circuit and a testing method, by the circuit, the pulse current in the positive direction and the negative direction can be tested through the digital channel board card and the voltage acquisition board card without an additional special board card, so that the additional testing cost required for designing the special board card is avoided.
In a first aspect, the present application provides a pulse current testing circuit, the circuit includes first control unit, second control unit, first MOS transistor, second MOS transistor, third MOS transistor, first resistor, second resistor and controller:
the first control unit is used for outputting a first control signal; the second control unit is used for outputting a second control signal;
the source electrode of the first MOS tube is grounded, the drain electrode of the first MOS tube is respectively connected with one end of the first resistor and the source electrode of the third MOS tube, the other end of the first resistor is connected with an output pin of a chip to be tested, and the grid electrode of the first MOS tube is connected with the first control unit and is used for controlling the on-off of the first MOS tube according to the first control signal;
the source electrode of the second MOS tube is grounded, the drain electrode of the second MOS tube is respectively connected with one end of the second resistor and the grid electrode of the third MOS tube, the other end of the second resistor is respectively connected with the drain electrode of the third MOS tube and an external power supply, the grid electrode of the second MOS tube is connected with the second control unit and is used for controlling the on-off of the second MOS tube and the third MOS tube according to the second control signal, and the on-off state of the second MOS tube is different from the on-off state of the third MOS tube;
the controller is used for controlling the second control unit to output a high level to conduct the second MOS tube and close the third MOS tube when the chip to be tested outputs the high level, controlling the first control unit to output a square wave signal with a high pulse width being a preset pulse width through the digital channel board card to conduct the first MOS tube, so that pulse current flows into the first resistor from an output pin of the chip to be tested, synchronously acquiring voltage change corresponding to the first resistor through the voltage acquisition board card, and determining a corresponding pulse current value based on the voltage change corresponding to the first resistor; when the chip to be tested outputs a low level, the first control unit is controlled to output the low level to close the first MOS tube, the second control unit is controlled to close the second MOS tube and conduct the third MOS tube by outputting a square wave signal with the low pulse width being a preset pulse width through the digital channel board card, so that pulse current flows into an output pin of the chip to be tested from the first resistor, voltage changes corresponding to the first resistor are synchronously collected through the voltage collecting board card, and corresponding pulse current values are determined based on the voltage changes corresponding to the first resistor.
In one possible implementation, the digital channel card is a DCM card.
In one possible implementation, the voltage acquisition board is a QVMe board.
In one possible implementation, the circuit further includes a third resistor and a fourth resistor:
one end of the third resistor is grounded, and the other end of the third resistor is connected with the grid electrode of the first MOS tube and is used for controlling the default working state of the first MOS tube to be closed;
and one end of the fourth resistor is grounded, and the other end of the fourth resistor is connected with the grid electrode of the second MOS tube and is used for controlling the default working state of the second MOS tube to be closed and controlling the default working state of the third MOS tube to be on.
In one possible implementation, the first resistor is a high-precision sampling resistor.
In one possible implementation, the voltage drop of the first resistor is less than 200mV.
In one possible implementation, the circuit further includes a fifth resistor and a sixth resistor:
the fifth resistor is arranged between the drain electrode of the first MOS tube and the first resistor and is used for ensuring the safety of the circuit;
the sixth resistor is arranged between the drain electrode of the third MOS tube and the external power supply and used for guaranteeing the safety of the circuit.
In one possible implementation, the fifth resistor and the sixth resistor are chip resistors.
In one possible implementation, the circuit further includes a seventh resistor and an eighth resistor:
the seventh resistor is arranged between the source electrode of the second MOS tube and the ground wire, the eighth resistor is arranged between the drain electrode of the second MOS tube and the second resistor, and the ratio between the total resistance value of the seventh resistor and the eighth resistor and the resistance value of the second resistor is smaller than the preset resistance value ratio.
In a second aspect, the present application further provides a test method based on a pulse current test circuit, the method comprising:
when the chip to be tested outputs a high level, the controller controls the second control unit to output a high level to conduct the second MOS tube and close the third MOS tube, controls the first control unit to output a square wave signal with a high pulse width being a preset pulse width through the digital channel board card to conduct the first MOS tube, so that pulse current flows into the first resistor from an output pin of the chip to be tested, synchronously acquires voltage changes corresponding to the first resistor through the voltage acquisition board card, and determines a corresponding pulse current value based on the voltage changes corresponding to the first resistor;
when the chip to be tested outputs a low level, the controller controls the first control unit to output a low level to close the first MOS tube, controls the second control unit to close the second MOS tube and conduct the third MOS tube by outputting a square wave signal with the low pulse width being a preset pulse width through the digital channel board card, so that pulse current flows into an output pin of the chip to be tested from the first resistor, synchronously acquires voltage change corresponding to the first resistor through the voltage acquisition board card, and determines a corresponding pulse current value based on the voltage change corresponding to the first resistor.
In summary, the present application provides a pulse current testing circuit and a testing method, where the circuit includes a first control unit, a second control unit, a first MOS transistor, a second MOS transistor, a third MOS transistor, a first resistor, a second resistor, and a controller: the first control unit is used for outputting a first control signal; the second control unit is used for outputting a second control signal; the source electrode of the first MOS tube is grounded, the drain electrode of the first MOS tube is respectively connected with one end of the first resistor and the source electrode of the third MOS tube, the other end of the first resistor is connected with an output pin of the chip to be tested, and the grid electrode of the first MOS tube is connected with the first control unit and used for controlling the on-off of the first MOS tube according to the first control signal; the source electrode of the second MOS tube is grounded, the drain electrode of the second MOS tube is respectively connected with one end of the second resistor and the grid electrode of the third MOS tube, the other end of the second resistor is respectively connected with the drain electrode of the third MOS tube and an external power supply, the grid electrode of the second MOS tube is connected with the second control unit and used for controlling the on-off of the second MOS tube and the third MOS tube according to the second control signal, and the on-off state of the second MOS tube is different from the on-off state of the third MOS tube; the controller is used for controlling the second control unit to output a high level to turn on the second MOS tube and turn off the third MOS tube when the chip to be tested outputs the high level, controlling the first control unit to output a square wave signal with the high pulse width being a preset pulse width to turn on the first MOS tube through the digital channel board card, so that pulse current flows into the first resistor from the output pin of the chip to be tested, synchronously acquiring voltage change corresponding to the first resistor through the voltage acquisition board card, and determining a corresponding pulse current value based on the voltage change corresponding to the first resistor; when the chip to be tested outputs a low level, the first control unit is controlled to output the low level to close the first MOS tube, the second control unit is controlled to output a square wave signal with the low pulse width being the preset pulse width through the digital channel board card to close the second MOS tube and conduct the third MOS tube, so that pulse current flows into an output pin of the chip to be tested from the first resistor, voltage changes corresponding to the first resistor are synchronously collected through the voltage collecting board card, and corresponding pulse current values are determined based on the voltage changes corresponding to the first resistor. Through the circuit, an additional special board card is not needed, and the pulse current in the positive direction and the negative direction can be tested through the digital channel board card and the voltage acquisition board card, so that the additional test cost required to be increased for designing the special board card is avoided.
Other advantages of the present application will be explained in more detail in connection with the following description and accompanying drawings.
It should be understood that the foregoing description is only an overview of the technical solutions of the present application, so that the technical means of the present application can be generally understood and implemented in accordance with the content of the specification. The following specific embodiments of the present application are illustrated in order to make the above and other objects, features and advantages of the present application more comprehensible.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the technical aspects of the application. It is appreciated that the drawings illustrate only certain embodiments of the application and are therefore not to be considered limiting of its scope, for the invention may admit to other equally relevant drawings without inventive effort to those of ordinary skill in the art. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:
fig. 1 is a schematic circuit diagram of a pulse current testing circuit according to an embodiment of the present disclosure;
fig. 2 is a flow chart of a test method according to an embodiment of the present application.
Detailed Description
Exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the description of embodiments of the present application, it should be understood that terms such as "comprises" or "comprising" are intended to indicate that the disclosed features, numbers, steps, acts, components, portions, or combinations thereof, are present in the specification, and do not preclude the presence or addition of one or more other features, numbers, steps, acts, components, portions, or combinations thereof.
Unless otherwise indicated, "/" means or, e.g., A/B may represent A or B; "and/or" herein is merely an association relationship describing an association object, and means that three relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist together, and B exists alone.
The terms "first," "second," and the like are used merely for convenience of description to distinguish between the same or similar technical features, and are not to be construed as indicating or implying a relative importance or quantity of such technical features. Thus, a feature defined by "first," "second," etc. may explicitly or implicitly include one or more such feature. In the description of embodiments of the present application, the term "plurality" means two or more unless otherwise indicated.
In the chip test of the driving type and the gate type, acquisition of parameters such as a short-circuit output current of the chip requires the use of a pulse current. In the process of using the pulse current, since the pulse current is generally large, strict limitation is generally required for the test time, and if the test time is exceeded, heat generated by the large current for a long time may cause the chip to be tested to burn out. That is, in order to secure the safety of the chip under test, a pulse current having a small pulse width needs to be used in the chip test.
For example, a typical chip such as IR2106 requires a pulse width of less than 10us for both the output of a high-level short-circuit current pulse and the output of a low-level short-circuit pulse, and since the supply voltage is 15V at the time of chip test, the output of a high-level is 15V, i.e., when the output of a low-level short-circuit pulse is tested, a voltage with a pulse width of less than 10us up to 15V needs to be applied, and the corresponding pulse current is tested.
In the related art, in order to obtain a pulse current with a smaller pulse width, a special board card is designed by related staff to meet the test requirement, but the special board card can meet the test requirement, but the design of the special board card requires additional test cost, which is not beneficial to chip test.
In view of this, the application provides a pulse current test circuit and test method, through this circuit, need not extra special integrated circuit board, can realize the test of the pulse current of two positive and negative directions to the chip that awaits measuring through digital channel integrated circuit board and voltage acquisition integrated circuit board to the design special integrated circuit board needs the extra test cost that increases of avoiding.
Referring to fig. 1, fig. 1 is a schematic circuit diagram of a pulse current testing circuit provided in an embodiment of the present application, where the circuit includes a first control unit, a second control unit, a first MOS transistor Q1, a second MOS transistor Q2, a third MOS transistor Q3, a first resistor R1, a second resistor R2, and a controller:
the first control unit is used for outputting a first control signal control1.
The second control unit is used for outputting a second control signal control2.
The source electrode of the first MOS tube Q1 is grounded, the drain electrode of the first MOS tube Q1 is respectively connected with one end of the first resistor R1 and the source electrode of the third MOS tube Q3, the other end of the first resistor R1 is connected with the output pin VOUT of the chip to be tested, and the grid electrode of the first MOS tube Q1 is connected with the first control unit and used for controlling the on-off of the first MOS tube Q1 according to the first control signal control1.
The source electrode of the second MOS tube Q2 is grounded, the drain electrode of the second MOS tube Q2 is respectively connected with one end of the second resistor R2 and the grid electrode of the third MOS tube Q3, the other end of the second resistor R2 is respectively connected with the drain electrode of the third MOS tube Q3 and an external power supply, the grid electrode of the second MOS tube Q2 is connected with the second control unit and used for controlling the on-off of the second MOS tube Q2 and the third MOS tube Q3 according to the second control signal control2, and the on-off state of the second MOS tube Q2 is different from the on-off state of the third MOS tube Q3.
Specifically, in the pulse current test circuit provided by the application, three MOS tubes are adopted, wherein the on-off state of the first MOS tube Q1 is controlled by the first control unit; the on-off state of the second MOS transistor Q2 and the third MOS transistor Q3 is controlled by the second control unit, and the on-off state of the second MOS transistor Q2 is different from the on-off state of the third MOS transistor Q3, when the second MOS transistor Q2 is conducted, the third MOS transistor Q1 is turned off due to the voltage division effect of the second resistor R2, and when the second MOS transistor Q2 is turned off, the third MOS transistor is turned on instead.
It should be noted that, the external power supply is a power supply corresponding to the pulse current testing circuit, and in practical application, the output voltage of the external power supply may be 15V. The voltage of the output pin VOUT of the chip to be tested is limited by an external power supply, the voltage of the output pin VOUT of the chip to be tested needs to be smaller than the voltage of the external power supply, and when the voltage of the external power supply is 15V, the voltage of the output pin VOUT of the chip to be tested is up to 15V.
The controller is used for controlling the second control unit to output a high level to turn on the second MOS transistor Q2 and turn off the third MOS transistor Q3 when the chip to be tested outputs the high level, controlling the first control unit to output a square wave signal with the high pulse width being a preset pulse width to turn on the first MOS transistor Q1 through the digital channel board card, so that pulse current flows into the first resistor R1 from the output pin VOUT of the chip to be tested, so that voltage change corresponding to the first resistor R1 is synchronously acquired through the voltage acquisition board card, and corresponding pulse current value is determined based on the voltage change corresponding to the first resistor R1; when the chip to be tested outputs a low level, the first control unit is controlled to output the low level to close the first MOS tube Q1, the second control unit is controlled to close the second MOS tube Q2 and conduct the third MOS tube Q3 by outputting a square wave signal with the low pulse width being a preset pulse width through the digital channel board card, so that pulse current flows into an output pin VOUT of the chip to be tested from the first resistor R1, voltage changes corresponding to the first resistor R1 are synchronously collected through the voltage collecting board card, and a corresponding pulse current value is determined based on the voltage changes corresponding to the first resistor R1.
Specifically, when the chip to be tested outputs a high level, the controller may be used to control the second control unit to output a high level to turn on the second MOS transistor Q2 and turn off the third MOS transistor Q3, for example, the controller may control the second control unit to output 5V so that the second MOS transistor Q2 is turned on, correspondingly, due to the voltage dividing effect of the second resistor R2, the third MOS transistor Q3 may be turned off, at this time, the controller may be used to control the first control unit to output a square wave signal with a high pulse width being a preset pulse width through the digital channel board to turn on the first MOS transistor Q1, the preset pulse width may be set by a relevant worker according to a test requirement of the chip to be tested, for example, for a typical chip IR2106, the preset pulse width may be 8us, when the preset pulse width is 8us, the controller may be used to control the first control unit to output a square wave signal with a high pulse width being 8us through the digital channel board, at this time, the first MOS transistor Q1 may be turned off after 8us, when the first MOS transistor Q1 is turned on, the third MOS transistor Q3 is turned off, and when the voltage VOUT 1 is turned off, the corresponding to the first voltage is determined to be a corresponding to the current collecting from the first voltage to be measured by the corresponding to the first voltage to the test chip, and the first voltage to be measured, and the current collecting the corresponding to the current value to the first voltage to the test chip has a corresponding to the test voltage value.
When the chip to be tested outputs a low level, the controller may be used to control the first control unit to output a low level to close the first MOS transistor Q1, for example, the controller may control the first control unit to output 0V so that the first MOS transistor Q1 is closed, meanwhile, the controller may be used to control the second control unit to output a square wave signal with a low pulse width being a preset pulse width through the digital channel board card to close the second MOS transistor Q2 and conduct the third MOS transistor Q3, for example, when the preset pulse width is 8us, the controller may be used to control the first control unit to output a square wave signal with a low pulse width being 8us through the digital channel board card, at this time, the second MOS transistor Q2 may be closed 8us, the third MOS transistor may be correspondingly conducted for 8us, when the third MOS transistor Q3 is turned on and the first MOS transistor Q1 is turned off, and the pulse current may flow from the first resistor R1 into the output pin of the chip to be tested, at this time, the first resistor R1 may be collected through the voltage board card and the voltage collecting pin, and the corresponding voltage value of the first resistor R1 may be determined based on the corresponding voltage change of the first resistor R1 and the corresponding change of the voltage value to be tested.
It should be noted that, through the synchronization function of the ATE machine (such as STS8300 machine), when the digital channel board card outputs square waves, the voltage acquisition board card is synchronously started to measure, so that the corresponding pulse current can be accurately tested.
Through the circuit, the pulse current can be tested when the output pin VOUT of the chip to be tested outputs high and low levels, and in the circuit, a special board card is not needed, the square wave signal with the pulse width being the preset pulse width is output through the digital channel board card, the voltage change of the first resistor is synchronously acquired through the voltage acquisition board card, the chip to be tested can be tested for the pulse current in the positive direction and the negative direction, and the extra test cost which is needed to be increased by the special board card is avoided.
In one possible implementation, the digital channel card may be a DCM card.
Specifically, the DCM board is a digital channel module (Digital channel module, DCM) board, the working frequency can reach 83MHz at maximum, namely the DCM board can output a square wave with the pulse width of tens of nanoseconds, in the practical application of the application, the DCM board can output a square wave with the pulse width of microsecond level, so that pulse current with the pulse width of microsecond level is generated at the chip to be tested, and the pulse width of the pulse current at the chip to be tested is ensured to meet the test requirement.
In one possible implementation, the voltage acquisition board may be a QVMe board.
Specifically, the QVMe board is a four-channel full-floating differential voltmeter module (Quad voltmeter module, QVMe) board, supports a high-speed and high-precision voltage acquisition function, supports an input voltage range of +/-4V in a high-speed mode, has a maximum resolution of 0.1us, and can accurately acquire voltage variation at the first resistor R1 through the QVMe board, so that pulse current flowing at the first resistor R1 and a chip to be tested is determined.
In one possible implementation manner, the first resistor R1 may be a high-precision sampling resistor, where the high-precision sampling resistor refers to a resistor with a small tolerance of resistance value and a stable resistance value, and the adoption of the resistor with the stable resistance value as the first resistor R1 is beneficial to ensuring the test precision of the pulse current.
In one possible implementation manner, the voltage drop of the first resistor R1 is less than 200mV, and since in the present application, the pulse current at the chip to be tested is determined by calculating the voltage at the first resistor R1, in order to reduce the interference of the first resistor R1 on the chip to be tested, the voltage drop of the first resistor R1 may be less than 200mV, and in practical application, the voltage drop of the first resistor R1 may be less than 200mV by making the first resistor R1 have a suitable resistance value.
In one possible implementation, the pulse current testing circuit may further include a third resistor R3 and a fourth resistor R4:
one end of the third resistor R3 is grounded, and the other end of the third resistor R3 is connected with the grid electrode of the first MOS tube Q1 and is used for controlling the default working state of the first MOS tube Q1 to be closed;
one end of the fourth resistor R4 is grounded, and the other end of the fourth resistor R4 is connected with the grid electrode of the second MOS tube Q2 and is used for controlling the default working state of the second MOS tube Q2 to be closed and controlling the default working state of the third MOS tube Q3 to be on.
Specifically, in the practical application of the present application, the corresponding third resistor R3 and fourth resistor R4 may be additionally added to the pulse current test circuit, so that when the first control unit and the second control unit do not output signals, the default working states of the first MOS transistor Q1 and the second MOS transistor Q2 are both closed.
In practical application, the resistance values of the third resistor R3 and the fourth resistor R4 are the same as the resistance value of the second resistor R2, and are both 1kΩ.
In one possible implementation, the second punch current testing circuit may further include a fifth resistor R5 and a sixth resistor R6:
the fifth resistor R5 is arranged between the drain electrode of the first MOS tube Q1 and the first resistor and is used for ensuring the safety of the circuit;
the sixth resistor is arranged between the drain electrode of the third MOS tube Q3 and an external power supply and used for guaranteeing the safety of the circuit.
Specifically, in order to avoid that when the first MOS transistor Q1 is turned on, the pulse current flowing at the first resistor R1 and the chip to be tested is too large, a corresponding fifth resistor R5 may be disposed between the drain of the first MOS transistor Q1 and the first resistor R1, and similarly, in order to avoid that when the third MOS transistor Q3 is turned on, the pulse current flowing at the first resistor and the chip to be tested is too large, a corresponding sixth resistor R6 may be disposed between the drain of the third MOS transistor Q3 and the first resistor R1.
In practical applications, the resistance of the fifth resistor R5 and the sixth resistor R6, which play a role in protection, is generally smaller.
In one possible implementation, to reduce the circuit space cost, the design is further refined, and the fifth resistor R5 and the sixth resistor R6 may be chip resistors.
In one possible implementation, the pulse current testing circuit may further include a seventh resistor R7 and an eighth resistor R8:
the seventh resistor R8 is arranged between the source electrode of the second MOS tube Q2 and the ground wire, the eighth resistor is arranged between the drain electrode of the second MOS tube Q2 and the second resistor R2, and the ratio between the total resistance value of the seventh resistor R7 and the eighth resistor R8 and the resistance value of the second resistor R2 is smaller than the preset resistance value ratio.
Specifically, in order to facilitate debugging of the pulse current test circuit, the pulse current test circuit may further include a seventh resistor R7 and an eighth resistor R8, and at this time, in order to ensure that the third MOS transistor Q3 is turned off when the second MOS transistor Q2 is turned on, a ratio between a total resistance value of the seventh resistor R7 and the eighth resistor R8 and a resistance value of the second resistor R2 needs to be smaller than a preset resistance value ratio, the preset resistance value ratio may be 1:10, for example, when the resistance value of the second resistor R2 is 1kΩ, the resistance value of the seventh resistor R7 may be 10Ω and the resistance value of the eighth resistor R8 may be 51Ω, that is, the total resistance value of the seventh resistor R7 and the eighth resistor R8 may be 61 Ω.
From this, this application provides a pulse current test circuit, and this circuit includes first control unit, second control unit, first MOS pipe, second MOS pipe, third MOS pipe, first resistance, second resistance and controller: the first control unit is used for outputting a first control signal; the second control unit is used for outputting a second control signal; the source electrode of the first MOS tube is grounded, the drain electrode of the first MOS tube is respectively connected with one end of the first resistor and the source electrode of the third MOS tube, the other end of the first resistor is connected with an output pin of the chip to be tested, and the grid electrode of the first MOS tube is connected with the first control unit and used for controlling the on-off of the first MOS tube according to the first control signal; the source electrode of the second MOS tube is grounded, the drain electrode of the second MOS tube is respectively connected with one end of the second resistor and the grid electrode of the third MOS tube, the other end of the second resistor is respectively connected with the drain electrode of the third MOS tube and an external power supply, the grid electrode of the second MOS tube is connected with the second control unit and used for controlling the on-off of the second MOS tube and the third MOS tube according to a second control signal, and the on-off state of the second MOS tube is different from the on-off state of the third MOS tube; the controller is used for controlling the second control unit to output a high level to turn on the second MOS tube and turn off the third MOS tube when the chip to be tested outputs the high level, controlling the first control unit to output a square wave signal with the high pulse width being a preset pulse width to turn on the first MOS tube through the digital channel board card, so that pulse current flows into the first resistor from the output pin of the chip to be tested, synchronously acquiring voltage change corresponding to the first resistor through the voltage acquisition board card, and determining a corresponding pulse current value based on the voltage change corresponding to the first resistor; when the chip to be tested outputs a low level, the first control unit is controlled to output the low level to close the first MOS tube, the second control unit is controlled to output a square wave signal with the low pulse width being the preset pulse width through the digital channel board card to close the second MOS tube and conduct the third MOS tube, so that pulse current flows into an output pin of the chip to be tested from the first resistor, voltage changes corresponding to the first resistor are synchronously collected through the voltage collecting board card, and corresponding pulse current values are determined based on the voltage changes corresponding to the first resistor. Through the circuit, an additional special board card is not needed, and the pulse current in the positive direction and the negative direction can be tested through the digital channel board card and the voltage acquisition board card, so that the additional test cost required to be increased for designing the special board card is avoided.
In the description of the present specification, descriptions with reference to the terms "some possible embodiments," "some embodiments," "examples," "specific examples," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiments or examples is included in at least one embodiment or example of the present application, and that the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the various embodiments or examples described in this specification and the features of the various embodiments or examples may be combined and combined by those skilled in the art without contradiction.
The following describes a test method based on the pulse current test circuit provided in the present application with a method embodiment, as shown in fig. 2, fig. 2 is a flow chart of the test method provided in the embodiment of the present application, where the method includes:
s201, when a chip to be tested outputs a high level, a controller controls a second control unit to output the high level to turn on a second MOS tube Q2 and turn off a third MOS tube Q3, controls a first control unit to output a square wave signal with the high pulse width being a preset pulse width through a digital channel board card to turn on a first MOS tube Q1, so that pulse current flows into a first resistor R1 from an output pin of the chip to be tested, synchronously acquires voltage changes corresponding to the first resistor R1 through a voltage acquisition board card, and determines a corresponding pulse current value based on the voltage changes corresponding to the first resistor R1;
and S202, when the chip to be tested outputs a low level, the controller controls the first control unit to output the low level to close the first MOS tube Q1, controls the second control unit to close the second MOS tube Q2 and conduct the third MOS tube Q3 by outputting a square wave signal with the low pulse width being a preset pulse width through the digital channel board card, so that pulse current flows into an output pin of the chip to be tested from the first resistor R1, synchronously acquires voltage change corresponding to the first resistor R1 through the voltage acquisition board card, and determines a corresponding pulse current value based on the voltage change corresponding to the first resistor R1.
While the spirit and principles of the present application have been described above with reference to several embodiments, it should be understood that the application is not limited to the particular embodiments disclosed nor does the division of aspects mean that features in these aspects cannot be combined. The application is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
Claims (10)
1. The pulse current testing circuit is characterized by comprising a first control unit, a second control unit, a first MOS tube, a second MOS tube, a third MOS tube, a first resistor, a second resistor and a controller:
the first control unit is used for outputting a first control signal; the second control unit is used for outputting a second control signal;
the source electrode of the first MOS tube is grounded, the drain electrode of the first MOS tube is respectively connected with one end of the first resistor and the source electrode of the third MOS tube, the other end of the first resistor is connected with an output pin of a chip to be tested, and the grid electrode of the first MOS tube is connected with the first control unit and is used for controlling the on-off of the first MOS tube according to the first control signal;
the source electrode of the second MOS tube is grounded, the drain electrode of the second MOS tube is respectively connected with one end of the second resistor and the grid electrode of the third MOS tube, the other end of the second resistor is respectively connected with the drain electrode of the third MOS tube and an external power supply, the grid electrode of the second MOS tube is connected with the second control unit and is used for controlling the on-off of the second MOS tube and the third MOS tube according to the second control signal, and the on-off state of the second MOS tube is different from the on-off state of the third MOS tube;
the controller is used for controlling the second control unit to output a high level to conduct the second MOS tube and close the third MOS tube when the chip to be tested outputs the high level, controlling the first control unit to output a square wave signal with a high pulse width being a preset pulse width through the digital channel board card to conduct the first MOS tube, so that pulse current flows into the first resistor from an output pin of the chip to be tested, synchronously acquiring voltage change corresponding to the first resistor through the voltage acquisition board card, and determining a corresponding pulse current value based on the voltage change corresponding to the first resistor; when the chip to be tested outputs a low level, the first control unit is controlled to output the low level to close the first MOS tube, the second control unit is controlled to close the second MOS tube and conduct the third MOS tube by outputting a square wave signal with the low pulse width being a preset pulse width through the digital channel board card, so that pulse current flows into an output pin of the chip to be tested from the first resistor, voltage changes corresponding to the first resistor are synchronously collected through the voltage collecting board card, and corresponding pulse current values are determined based on the voltage changes corresponding to the first resistor.
2. The circuit of claim 1, wherein the digital channel card is a DCM card.
3. The circuit of claim 1, wherein the voltage acquisition board is a QVMe board.
4. The circuit of claim 1, further comprising a third resistor and a fourth resistor:
one end of the third resistor is grounded, and the other end of the third resistor is connected with the grid electrode of the first MOS tube and is used for controlling the default working state of the first MOS tube to be closed;
and one end of the fourth resistor is grounded, and the other end of the fourth resistor is connected with the grid electrode of the second MOS tube and is used for controlling the default working state of the second MOS tube to be closed and controlling the default working state of the third MOS tube to be on.
5. The circuit of claim 1, wherein the first resistor is a high precision sampling resistor.
6. The circuit of claim 1, wherein the voltage drop of the first resistor is less than 200mV.
7. The circuit of claim 1, further comprising a fifth resistor and a sixth resistor:
the fifth resistor is arranged between the drain electrode of the first MOS tube and the first resistor and is used for ensuring the safety of the circuit;
the sixth resistor is arranged between the drain electrode of the third MOS tube and the external power supply and used for guaranteeing the safety of the circuit.
8. The circuit of claim 7, wherein the fifth resistor and the sixth resistor are chip resistors.
9. The circuit of claim 1, further comprising a seventh resistor and an eighth resistor:
the seventh resistor is arranged between the source electrode of the second MOS tube and the ground wire, the eighth resistor is arranged between the drain electrode of the second MOS tube and the second resistor, and the ratio between the total resistance value of the seventh resistor and the eighth resistor and the resistance value of the second resistor is smaller than the preset resistance value ratio.
10. A test method based on the pulse current test circuit of any one of claims 1-9, the method comprising:
when the chip to be tested outputs a high level, the controller controls the second control unit to output a high level to conduct the second MOS tube and close the third MOS tube, controls the first control unit to output a square wave signal with a high pulse width being a preset pulse width through the digital channel board card to conduct the first MOS tube, so that pulse current flows into the first resistor from an output pin of the chip to be tested, synchronously acquires voltage changes corresponding to the first resistor through the voltage acquisition board card, and determines a corresponding pulse current value based on the voltage changes corresponding to the first resistor;
when the chip to be tested outputs a low level, the controller controls the first control unit to output a low level to close the first MOS tube, controls the second control unit to close the second MOS tube and conduct the third MOS tube by outputting a square wave signal with the low pulse width being a preset pulse width through the digital channel board card, so that pulse current flows into an output pin of the chip to be tested from the first resistor, synchronously acquires voltage change corresponding to the first resistor through the voltage acquisition board card, and determines a corresponding pulse current value based on the voltage change corresponding to the first resistor.
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