JPH0829490A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enable nondefective chips to be sorted out by interrupting the direct currents of input circuits during a sorting test, and passing the direct currents during normal operation. CONSTITUTION:A normal operation mode is switched to a sorting test mode and vice versa by control signals D, DN which are produced by inverters 31, 33, respectively. During normal operation, high-level (H) and low-level (L) signals are provided respectively to inputs 1, 2, whereas a signal lower than the threshold of the inverter 31 is provided to the input 2 during a sorting test using a static current. The signal D varies from L to H and the signal DN from H to L. The signals D, DN turn off p-type MOS transistors 15, 19, 13, 17, 11 and n-type MOS transistors 27, 5, 9 so that direct currents from a high voltage source VDD are all shut off. When the performance of each MOS transistor is sufficiently high, the currents consumed are small enough so that a sorting test can be conducted by measuring the currents.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device used in an input circuit for performing differential amplification.

[0002]

2. Description of the Related Art Generally, in the field of information processing, the available data transfer rate is increasing year by year with the development of semiconductor processing technology. Currently, frequencies above 100 MHz are very commonly used in high speed computer and data communication applications. For example, in optical communication, 2.4G
Very high speed signals such as Hz are used. In such a frequency band, the amplitude of the signal has to be considerably reduced, and stable transfer is becoming impossible with one signal line. Therefore, at present, it is becoming practical to perform data transfer by using the differential signal using two signal lines.

When these two signal lines are used, data signals having the same amplitude but a phase difference of 180 ° are sent to the respective signal lines. The original digital data is restored by the sign (positive or negative) of the difference between the two signals. FIG. 6 shows a conventional example of a semiconductor integrated circuit for such signal processing.

This semiconductor integrated circuit device is a circuit which inputs a small amplitude signal (for example, a signal having an amplitude of 1 volt) and outputs a signal having an amplitude of CMOS level, and is used as an input circuit of a chip. The input 1 and the input 2 are 180 ° out of phase with each other, and the potential difference between the two inputs is amplified by the CMOS differential amplifier circuit and converted to the CMOS level by the CMOS inverter gate.

[0005]

By the way, when manufacturing and shipping a semiconductor integrated circuit, a screening test is performed for good products and defective products. Generally, a CMOS integrated circuit draws almost no current when it is not switching. Therefore, in a defect-free CMOS integrated circuit, when a power supply is applied to the chip and the switching operation of the chip is stopped, only a very small current consumption flows in the chip. However, when a chip has a defect or a potential defect that leads to a future defect, the current consumption often becomes abnormally large. Therefore, in the sorting test at the time of shipment, it is convenient and often used to check this current consumption first, and exclude chips with current consumption larger than a certain standard as defective products even if they operate normally. .

Here, this consumed current is called a static current.

However, in the circuit of FIG. 6, a direct current as shown in the figure always flows, which hinders the detection of leak current due to a defect, so that there is a problem that the selection test by the static current cannot be performed.

The present invention has been made in consideration of the above circumstances, and an object thereof is to cut off a direct current flowing through a circuit during a screening test with a static current, and to send a direct current through the circuit at other times. Thus, a semiconductor integrated circuit device capable of inputting a small amplitude signal and outputting a CMOS amplitude signal is provided.

[0009]

In order to achieve the above object, the semiconductor integrated circuit device according to the first aspect of the present invention is arranged such that both potentials are provided in response to an input signal having a small amplitude between a first potential and a second potential. An input circuit that outputs a signal having a large amplitude between the input circuit and a control circuit that cuts off a direct current path of the input circuit, the control circuit receiving an input signal of the input circuit, The threshold of the input circuit is set between the potential of the small-amplitude input signal and one of the first and second potentials, and the threshold of the circuit and the first threshold are set as the input signal of the control circuit. When a signal of a potential between the other of the first and second potentials is being input, the control circuit does not interrupt, a direct current flows through the input circuit, and the input circuit operates normally. The circuit threshold and the And when the signal between the potential of one of the second potential is inputted, characterized in that the direct current of the input circuit is cut off.

In the semiconductor integrated circuit device according to the second invention, the input stage of the control circuit is composed of a CMOS gate using PMOS and NMOS, and the PMOS and NMOS are provided.
The input circuit threshold value of the control circuit is set as described above by adjusting the dimension of.

In the semiconductor integrated circuit device according to the third aspect of the invention, an input for outputting a signal having a large amplitude between the first and second potentials in response to an input signal having a small amplitude between the two potentials. A circuit and a control circuit for interrupting a direct current path of the input circuit, the control circuit inputs an input signal of the input circuit, the input terminal of the input circuit and the first and second potentials. A resistor is connected between
The threshold value of the input circuit of the control circuit is set between the potential of the small amplitude input signal and one of the first and second potentials, and when the input of the input circuit is opened, An input potential of the control circuit is one of the first and second potentials, and the input circuit is controlled so as to cut off a direct current.

According to the semiconductor integrated circuit device of the fourth invention, the input stage of the control circuit is a PMOS and an NMOS.
It is composed of a CMOS gate using
It is characterized in that the input circuit threshold value of the control circuit is set as described above by adjusting the dimension of the MOS.

[0013]

According to the semiconductor integrated circuit device of the first aspect of the invention configured as described above, at the time of the selection test by the static current, the potential of the opposite side where the signal having the amplitude smaller than the input circuit threshold value of the control circuit is located. The input is given to interrupt the direct current of the input circuit to make the output of the input circuit constant, and in other cases, the control circuit supplies the direct current necessary for driving to the input circuit to operate the input circuit normally. As a result, good and defective chips can be sorted by a sorting test using a static current.

Further, according to the semiconductor integrated circuit device of the third aspect of the invention configured as described above, when the input is opened during the screening test by the static current, the input potential is changed by the resistor connected between the input and the power supply. Exceeds the input circuit threshold of the control circuit and becomes a potential on the opposite side where the small amplitude signal is located, and the control circuit cuts off the direct current of the input circuit to make the output of the input circuit constant. As a result, it is possible to perform a screening test for good chips and defective chips by a screening test using a static current.

Further, according to the semiconductor integrated circuit device of the second and fourth inventions constructed as described above, the first input stage of the control circuit is composed of a CMOS gate, and its PMOS is formed.
The input circuit threshold value is set by adjusting the dimensions of NMOS and NMOS. Thereby, the input circuit threshold value of the control circuit can be set between the small amplitude input signal and the power supply voltage as described above.

[0016]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a configuration diagram of a first embodiment of a semiconductor integrated circuit device according to the present invention.

As shown in FIG. 1, the semiconductor integrated circuit device of this embodiment is a differential amplifier which receives an input data signal sent from two signal lines. This circuit has one input,
The sign (positive or negative) of the potential difference of the input 2 is detected and converted into a high level (for example, 3 V) and low level (for example, 0 V) output. That is, to the gates of the N-type MOS transistors 1 and 3, a signal to which a positive bias is applied and the phase is inverted is applied from both the input 1 and the input 2. Since both the signals from the input 1 and the input 2 are applied with a voltage higher than the threshold value of these N-type MOS transistors, at least one of the N-type MOS transistors 1 and 3 is turned on.

On the other hand, the sources of the N-type MOS transistors 1 and 3 are connected to the ground level via the N-type MOS transistor 5. Since the gate of the N-type MOS transistor 5 forms a mirror circuit together with the N-type MOS transistor 9, it functions as a constant current source. N type MO
The magnitude of the current flowing through the S transistor 5 depends on the N-type MOS.
Dimension ratio with transistor 9 (ratio of gate width)
And the magnitude of the current flowing through the N-type MOS transistor 9, and the magnitude of the current flowing through the N-type MOS transistor 9 is determined by the bias circuit composed of the P-type MOS transistor 11. Therefore, by setting the magnitude of the current of the constant current source appropriately, the N-type MOS transistor 5
Potential on the drain side of the N-type MOS transistors 1, 3
The potential can be raised to a potential slightly lower (about the threshold value) than the gate having a higher potential. As a result, N type M
It is guaranteed that only one of the OS transistors 1 and 3 will be on and the other will be off.

The drain sides of the N-type MOS transistors 1 and 3 are connected to a high voltage source VDD (for example, 3V) via P-type MOS transistors 13 and 15. These P
The MOS transistors 13 and 15 function as output resistors of this differential amplifier. That is, the gates and drains of the P-type MOS transistors 13 and 15 are connected to each other, and P
With the MOS transistors 17 and 19, mirror circuits are formed respectively. Also, the N-type MOS transistor 2
Numerals 1 and 23 also form a mirror circuit, each of which is a P-type MOS
It is connected between the transistors 17 and 19 and the ground level.

When a signal higher than the input 2 is applied to the input 1, the N-type MOS transistor 3 is turned on, the node N2 becomes low level, and the P-type MOS transistor 19 is turned on.
Turns on. As a result, the N-type MOS transistor 23 is turned on, and the N-type MOS transistor 21 whose gates are connected to it is also turned on. On the other hand, when the N-type MOS transistor 3 turns on, the N-type MOS transistor 1 turns off,
The node N3 goes high. Then, P which forms an output inverter circuit together with the N-type MOS transistor 21.
The type MOS transistor 17 is turned off, and the node N4 surely becomes low level.

On the contrary, when a signal higher than the input 1 is applied to the input 2, the N-type MOS transistor 1 is turned on and the N-type M transistor is turned on.
The OS transistor 3 turns off. Then, the node N2 becomes high level, and the P-type MOS transistor 19 is turned off. As a result, the N-type MOS transistor 23 is also turned off,
N-type MOS transistor 2 with its gate connected to it
1 is also turned off. On the other hand, when the N-type MOS transistor 1 turns on, the node N3 becomes low level, the P-type MOS transistor 17 turns on, and the node N4 is pulled up to high level.

With the above configuration, the voltage of the input 1 becomes the input 2
If the voltage is higher than the voltage of, the node N4 becomes low level, and the inverter 29 including the P-type MOS transistor 25 and the N-type MOS transistor 27 outputs a high-level output signal. On the contrary, when the voltage of the input 1 is lower than the voltage of the input 2, the node N4 becomes high level and the inverter 29 outputs a low level output signal.

In the present invention, a circuit for performing a selection test with a static current is further added to this circuit. That is, this circuit can switch between the normal operation mode and the selection test mode. The mode switching is performed by the control signals D and DN generated by the two inverters 31 and 33 connected to the input 2. The inverter 31 is an N-type MOS transistor 43,
The inverter 33 includes a P-type MOS transistor 45.
Is composed of an N-type MOS transistor 47 and a P-type MOS transistor 49. When operating a normal differential amplifier,
The high level input signal VI of FIG. 2 is input to the input 1 and the input 2, respectively.
H (for example, 2.5 V) and low level input signal VIL
(Eg 1.5V) is applied. When performing the selection test using the static current, a signal lower than the threshold value Vthc of the inverter 31 is applied to the input 2. Threshold V
The value of thc is the N-type MOS transistor 43 and the P-type M
By adjusting the dimension (gate width) of the OS transistor 45, it is preset to an appropriate value (for example, 0.7 V) between the ground level and the input signal. As a result, the control signal D changes from the low level to the high level, and the control signal DN changes from the high level to the low level.

The low level control signal DN is a P-type MOS.
Transistors 15 and 19 and P-type MOS transistor 1
It is given to the gates of P-type MOS transistors 37, 39 connected between the gates of 3, 17 and the high voltage source VDD, and the P-type MOS transistors 37, 39 are turned on, whereby the nodes N2, N3 are at high level. Next, P-type MO
The S transistors 15, 19, 13, 17 are turned off. On the other hand, an N-type MOS transistor 41 is connected to the input of the inverter 29, which is a high level control signal D.
By turning on at, N4 is lowered to the ground level, and N type M
The OS transistor 27 turns off. Further, the P-type MOS transistor 11 is also turned off by the control signal D and the current path from the high voltage source VDD is cut off. Also, the control signal D
Adds to the gate of the N-type MOS transistor 7 and turns it on to set the node N1 to a low level. This allows
N-type MOS transistor 5 and N-type MOS transistor 9
Turn off promptly. Therefore, all the current paths from the high voltage source VDD are cut off, and if the performance of each MOS transistor is sufficient, the current consumption should be sufficiently small, and the selection test can be performed by measuring this. .

Another example of setting the threshold value of the input circuit of the control circuit is shown in FIG. The input circuit threshold value Vthc is set between the high level VIH (for example, 1 V) of the input signal and the VDD potential. In this case, the logic of the control circuit is opposite to that in the above case, so that the P-type MOS circuit is used in the circuit of FIG.
The gate inputs of the transistors 37 and 39 must be changed to the D signal, and the gate inputs of the N-type MOS transistors 7 and 41 and the P-type MOS transistor 11 must be changed to the DN signal.

Next, FIG. 4 shows the configuration of a second embodiment of the semiconductor integrated circuit device according to the present invention. The semiconductor integrated circuit device of the second embodiment is the first embodiment of the semiconductor integrated circuit device according to the present invention shown in FIG. 1 and has a resistor R1 connected between the input 2 and the ground level.

In the semiconductor integrated circuit device of the second embodiment of the present invention thus constructed, when the input 2 is opened, the potential of the input 2 becomes the ground level due to the resistor R1 and the D signal becomes high. The level (VDD) and the DN signal are low level (GND).

Therefore, the circuit operation is the same as that in the screening test of the first embodiment, and the DC current flowing through the circuit of FIG. 6 stops flowing through the circuit of FIG. Further, the output of the input circuit is fixed to high level (VDD). In this way, it is possible to prevent the input circuit from consuming current.
It becomes possible to perform a sorting test with a static current.

By the way, when the input circuit threshold value of the control circuit is set as shown in FIG. 3 in the circuit of FIG. 4, the resistor R1 is connected between the input 2 and VDD as shown in FIG. Further, the signal D and the signal DN are exchanged.

Although the control circuit has one input in the above description, a plurality of input signals may be input. For example, in the circuit of FIG. 1, a 2-input NAND gate may be used instead of the CMOS inverter gate 31 to generate the D signal from the input 1 and the input 2.

In the above description, the D signal and the DN signal cut off the DC current path of one input circuit, but this may cut off the DC currents of a plurality of input circuits. Further, the D signal and the DN signal can be used to cut off the direct current of other circuits inside the chip.

[0033]

As described above, according to the present invention, the DC current flowing in the circuit is cut off during the screening test by the static current, and the DC current of the circuit is supplied in other cases, and the small amplitude signal is input. As a result, a signal having a CMOS level amplitude can be output. The switching of the circuit is automatically judged by the control circuit depending on whether or not the input signal is in the vicinity of the potential defined in the specification in advance. Therefore, the selection test can be performed without requiring a new control signal input pin for switching the circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a first embodiment of a semiconductor integrated circuit device according to the present invention.

2 is an example of a potential of an input signal and a circuit threshold of a control circuit in the semiconductor integrated circuit shown in FIG.

3 is another example of the potential of the input signal and the circuit threshold of the control circuit in the semiconductor integrated circuit shown in FIG.

FIG. 4 is a circuit diagram showing a configuration of a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a modification of the second embodiment of the present invention.

FIG. 6 is a circuit diagram showing an example of a conventional input circuit.

[Explanation of symbols]

 29 Output inverter 31, 33 Control signal generation inverter D, DN Control signal

[Procedure amendment]

[Submission date] February 7, 1995

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

Claims (4)

[Claims] 1. An input circuit for outputting a signal having a large amplitude between the first potential and the second potential in response to an input signal having a small amplitude between the first potential and the second potential, and a direct current path of the input circuit. A control circuit for shutting off, the control circuit inputs an input signal of the input circuit, and a threshold value of the input circuit of the control circuit is the potential of the small amplitude input signal and the first and second When a signal having a potential between the threshold of the circuit and the other of the first and second potentials is input as an input signal of the control circuit, The interruption by the control circuit is not performed, a direct current flows through the input circuit, the input circuit operates normally, and the circuit threshold and one of the first and second potentials are input to the input of the control circuit. When a signal between The semiconductor integrated circuit device and a current is cut off. 2. The input stage of the control circuit comprises a PMOS and an NM.
The PMOS is composed of a CMOS gate using an OS.
2. The semiconductor integrated circuit device according to claim 1, wherein the threshold value of the input circuit of the control circuit is set as described above by adjusting the dimensions of NMOS and NMOS. 3. An input circuit which outputs a signal having a large amplitude between the first potential and the second potential in response to an input signal having a small amplitude between the first potential and the second potential, and a direct current path of the input circuit. A control circuit for shutting off, the control circuit inputs an input signal of the input circuit, and a resistor is connected between an input terminal of the input circuit and one of the first and second potentials. , The threshold value of the input circuit of the control circuit is set between the potential of the small amplitude input signal and one of the first and second potentials, and when the input of the input circuit is opened, The semiconductor integrated circuit device is characterized in that an input potential of the control circuit becomes one of the first and second potentials and is controlled so that a direct current of the input circuit is cut off. 4. The input stage of the control circuit comprises a PMOS and an NM.
The PMOS is composed of a CMOS gate using an OS.
4. The semiconductor integrated circuit device according to claim 3, wherein the threshold value of the input circuit of the control circuit is set as described above by adjusting the dimensions of NMOS and NMOS.