CN206292349U - A kind of test system for wafer - Google Patents
A kind of test system for wafer Download PDFInfo
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- CN206292349U CN206292349U CN201621415299.8U CN201621415299U CN206292349U CN 206292349 U CN206292349 U CN 206292349U CN 201621415299 U CN201621415299 U CN 201621415299U CN 206292349 U CN206292349 U CN 206292349U
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Abstract
The utility model provides a kind of test system for wafer, including tester, first relay module, single-chip microcomputer, second relay module and the 3rd relay module, tester is used to carry out the first test to wafer, first relay module is used to be connected between tester and wafer, first relay module is used to receive the first make-and-break signal of tester output, single-chip microcomputer receives the enabling signal of tester, single-chip microcomputer carries out the second test by AES to wafer, second relay module is used to be connected between single-chip microcomputer and wafer, second relay module is used to receive the second make-and-break signal of tester output, 3rd relay module is connected between tester and single-chip microcomputer, 3rd relay module receives the 3rd make-and-break signal of tester output.Different tests are carried out to chip by tester and single-chip microcomputer respectively, and is switched over using relay module, it can greatly promote testing efficiency.
Description
Technical field
The utility model is related to wafer sort field, more particularly to a kind of test system for wafer.
Background technology
Wafer refers to the silicon wafer used by silicon semiconductor production of integrated circuits, and various circuits can be manufactured on wafer
Component structure, and turn into the IC chip for having specific electrical functionality.After wafer manufacture is completed, wafer sort is that a step is weighed very much
The test wanted, wafer sort is that each IC chip on chip is tested, by with chip on outer contact（pad）Connect
Touch, test its electrical characteristic, see whether meet factory calibration.
Typically tested by special tester during wafer sort, and tester is in design, it is more normal
Test event has been packed into tester, and the logic function of proofing chip is all realized using fixed test pattern.But
With the diversification of chip product, some functional testers again cannot be completed individually, and such as some chips have random code, are obtaining
After having got random code, AES is run, then can just calculate the instruction to chip operation, therefore the finger of different IC chips
Order is different from, and causes the fixed test pattern of existing tester and cannot realize good adaptability.
The content of the invention
The purpose of this utility model is to provide a kind of test system of the wafer high with adaptability and testing efficiency.
In order to realize the purpose of this utility model, the utility model provides a kind of test system for wafer, including surveys
Examination instrument, the first relay module, single-chip microcomputer, the second relay module and the 3rd relay module, tester are used to carry out first to wafer
Test, the first relay module is used to be connected between tester and wafer, and the first relay module is used to receive tester output
First make-and-break signal, single-chip microcomputer receives the enabling signal of tester, and single-chip microcomputer carries out the second test by AES to wafer,
Second relay module is used to be connected between single-chip microcomputer and wafer, and the second relay module is led to for receiving the second of tester output
Break signal, the 3rd relay module is connected between tester and single-chip microcomputer, and the 3rd relay module receives the 3rd of tester output
Make-and-break signal.
From such scheme, because the chip of more and more wafers uses AES, therefore data side is carried out to chip
The test in face then needs the single-chip microcomputer provided using wafer production business, and the single-chip microcomputer has the key of chip, can test its number
Communication according to aspect whether there is failure, while in order to improve testing efficiency, by relay module be separately positioned on single-chip microcomputer with
Between chip wafer, between single-chip microcomputer and tester, between tester and chip, the break-make control using tester to relay module
System, enabling in the case of not switch test equipment, successively carry out tester carries out non-encrypted performance test to wafer,
The data test being encrypted to wafer with single-chip microcomputer, is controlled by the startup of tester before single-chip microcomputer test, single after test
Piece machine will return to test result to tester, and the result of last test feedback can outwards be exported by tester and store or show
Show, it can greatly promote testing efficiency, and using the control break-make of relay module, test can be improved from physical channel
Isolation, so as to reach reduce interference purpose.
Further scheme is that test system also includes interface module, and tester is connected by interface module with single-chip microcomputer
Connect, single-chip microcomputer is connected by interface module with wafer.
Further scheme is that interface module connects including chip interface, set of test modules, interface microcontroller and tester
Mouthful, chip interface is used to be connected with the chip of wafer, and set of test modules is connected between interface microcontroller and chip interface, monolithic
Machine interface is connected with tester interface, and interface microcontroller is used to be connected with single-chip microcomputer, and tester interface is used to be connected with tester.
Therefore, by the setting of interface module, as long as in test that tester, testing needle platform is corresponding with single-chip microcomputer
Wafer sort can be carried out in connection, when different wafer sorts are changed, as long as being accessed using interface microcontroller in interface module
Another single-chip microcomputer can continue to test, and it can greatly promote testing efficiency.
Further scheme is that chip interface has two, and set of test modules has eight, and interface microcontroller has eight
Individual, tester interface has two, and every four set of test modules are connected with a chip interface, each set of test modules and
Individual interface microcontroller, every four interface microcontrollers are connected with a tester interface.
Therefore, eight set of test modules are set in interface module so that the tester of this case can be simultaneously to 8 class cores
Piece carry out simultaneously concurrent testing, and it is separate do not interfere with each other, it can greatly improve testing efficiency.
Further scheme is that set of test modules includes five test modules, and test module is connected in parallel on chip
Between interface and interface microcontroller.
Therefore, five test modules can carry out repeatedly different tests for chip, then ensure that chip
Measuring stability.
Further scheme is that test module and interface microcontroller are arranged along a straight line.
Therefore, the layout being arranged along a straight line optimised devices can be laid out significantly, reduce the electromagnetism between test module
Interference.
Brief description of the drawings
Fig. 1 is the system block diagram of the utility model test system embodiment.
Fig. 2 is the structure principle chart of interface module in the utility model test system embodiment.
Fig. 3 is the flow chart of the utility model method of testing embodiment.
Below in conjunction with drawings and Examples, the utility model is described in further detail.
Specific embodiment
The test system embodiment of wafer：
Reference picture 1, Fig. 1 is the system block diagram of test system, and multiple chips are disposed with wafer, and multiple chips constitute to be measured
The chipset 1 of examination, test system include tester 3, the first relay module 41, single-chip microcomputer 2, the second relay module 42 and the 3rd after
Electric module 43, the first relay module 41 is used to be connected between tester 3 and chipset 1, and tester 3 can be carried out to chipset 1
First test, the first relay module 41 is used to receive the first make-and-break signal of the output of tester 3, then realizes tester 3 pair the
The break-make control of one relay module 41.
Single-chip microcomputer 2 receive tester 3 enabling signal, the key that single-chip microcomputer 2 has program stored therein with chip, its be used for it is right
Chip is answered to be encrypted data interaction, single-chip microcomputer 2 carries out the second test, the second relay module to chipset 1 by AES
42 are used to be connected between single-chip microcomputer 2 and chipset 1, and the second relay module 42 is used to receive the second break-make of the output of tester 3
Signal, realizes the break-make control of 3 pairs of the second relay modules 42 of tester, and the 3rd relay module 43 is connected to tester 3 and monolithic
Between machine 2, the 3rd relay module 43 receives the 3rd make-and-break signal of the output of tester 3.
Reference picture 2, test system also includes interface module, and interface mould is passed through between chipset 1, single-chip microcomputer 2 and tester 3
Block wiring connection, interface module includes two interface microcontrollers 53 of set of test modules 52, eight of chip interface 51, eight and two
Tester interface 54, chip interface 51 is used to be connected with the contact pilotage of pin platform, then realizes being used for the chip with wafer by contact pilotage
Group 1 is connected.
Set of test modules 52 is connected between interface microcontroller and chip interface, and each set of test modules 52 includes five surveys
Die trial block, test module is connected in parallel between chip interface 51 and the interface of single-chip microcomputer 53.Five test modules can use IC
Chip is respectively used to export test signal and test data to chip.
Every four set of test modules 52 are connected with a chip interface 51, each set of test modules 52 and a single-chip microcomputer
Interface 53, every four interface microcontrollers 53 are connected with a tester interface 54.Set of test modules 52 and the edge of interface microcontroller 53
Straight line, chip interface 51 and tester interface 54 are separately positioned on the two ends of interface module.Interface microcontroller is used for single
Piece machine is connected, and tester interface 54 is used to be connected with tester, then realizes that tester is connected by interface module with single-chip microcomputer,
Single-chip microcomputer is connected by interface module with the chipset of wafer.
The method of testing embodiment of the test system of wafer：
Reference picture 3, is that directly the chip of wafer is tested by tester during to wafer sort first, is then surveyed
Examination instrument is tested wafer by control single chip computer.
Specifically, step S1 is first carried out, the first relay module 41 is opened so that tester directly with the chip of wafer
Connection, and simultaneously block the second relay module 42 and the 3rd relay module 43, then performing step S2, i.e., tester is to wafer
Chip carries out the first test, and the first test includes multiple function N tests such as S21, S22, S23 for carrying out in order, in this implementation
In example, the first test includes：
Protection diode is tested, and forward diode and backward dioded to being connected with outer contact in the chip of wafer are carried out
Test, specifically, each outer contact PAD of chip has a forward direction and a reverse diode to GND and VCC, if
Diode damage, or contact it is bad, this functionality will test failure, then the surface chip there is failure；
Whether input pin leakage testses, the leakage current of the outer contact of the chip of test wafer exceedes threshold value, specifically, core
Each outer contact PAD to VCC and GND of piece can have a leakage current, if leakage current is too big, then upper level load cannot
Drive more chips；
Quiescent current is tested, and whether the quiescent current of the chip of test wafer exceedes threshold value, specifically, chip is not working
When, VCC to GND has an electric current to pass through, if this electric current is excessive, the situation that battery is consumed quickly just occurs,
Such as, when remote control is not used, if quiescent current is too big, that remote controller chip by the electricity of excessive loss's battery, after
And cause that battery is accomplished by changing quickly；
Whether Dynamic Current Testing, the dynamic current of the chip of test wafer exceedes threshold value, specifically, chip is in work
When, VCC to GND has an electric current to pass through, if this electric current is excessive, the situation that battery is consumed quickly just occurs, than
As said, same toy for children, same battery, the time of battery altering is different, precisely due to dynamic current causes greatly very much
's.
Above-mentioned is the performance test to chip, tests whether it meets preset standard, if the first test all passes through
Step S3 will be then performed, if the first test is any to test what is do not passed through, test crash signal will be returned to tester.
Step S3 is then performed, the second relay module is connected into S3 with the 3rd relay module so that single-chip microcomputer connects with chip
Connect, single-chip microcomputer is connected with tester, while the first relay module is blocked.Step S4 is then performed, tester is defeated to single-chip microcomputer
Go out enabling signal, and whether normally to verify the communication of single-chip microcomputer, return to test crash signal to tester if breaking down, such as
It is normal then perform step S5, i.e. single-chip microcomputer the second test is carried out to chip wafer, can be by single-chip microcomputer and four set of test modules
Different instruction is exported to chip respectively, the second test includes multiple function N tests such as S51, S52, S53 for carrying out in order,
In the present embodiment, the second test includes：
Whether electricity and power down are normal on the EEPROM of the chip of test wafer, and it can be that first EEPROM is write to test this part
Full 0, treats that chip returns to full 0 and the reading full 0 for passing through single-chip microcomputer, and complete 1 is then write to EEPROM, treats that chip returns to complete 1 and passes through
The reading complete 1 of single-chip microcomputer, if reading other instructions, represents and breaks down, and the full 0 or complete 1 for such as reading then shows upper electricity
It is normal with power down.
Whether adjacent EEPROM is short-circuit in the chip of test wafer, and it can be that first EEPROM is write to test this part
55AA, treats that chip returns to 55AA and the reading 55AA for passing through single-chip microcomputer, then writes AA55 to EEPROM, treats that chip returns to AA55 simultaneously
By the reading AA55 of single-chip microcomputer, if reading other instructions, represent and break down, the 55AA or AA55 for such as reading, then
Show in the absence of short circuit.
The data communication of test wafer, user data is write by EEPROM, treats that chip returns to user data and passes through
The reading user data of single-chip microcomputer, can learn whether the data reliability of chip is normal after being verified.
Above-mentioned is the data test to chip, and the data of test are, by encryption, to test whether it meets pre- bidding
Standard, all shows that the chip functions are normal if the second test if, if the second test is any to test what is do not passed through, to
Tester returns to test crash signal.Step S6 is then performed to close whole relay module.
Therefore, because the chip of more and more wafers uses AES, therefore the survey in terms of data is carried out to chip
The single-chip microcomputer for then needing to be provided using wafer production business is tried, the single-chip microcomputer has the key of chip, can test its data aspect
Communication whether there is failure, while in order to improve testing efficiency, single-chip microcomputer and wafer core are separately positioned on by relay module
Between piece, between single-chip microcomputer and tester, between tester and chip, the break-make of relay module is controlled using tester, made
Obtaining can be in the case of not switch test equipment, and successively carrying out tester carries out non-encrypted performance test to wafer, and single
The data test that piece machine is encrypted to wafer, is controlled by the startup of tester before single-chip microcomputer test, single-chip microcomputer after test
Test result to tester will be returned to, the result of last test feedback can outwards be exported by tester and store or show,
It can greatly promote testing efficiency, and using the control break-make of relay module, test can be improved from physical channel
Isolation, the purpose of interference is reduced so as to reach.
Claims (6)
1. a kind of test system for wafer, it is characterised in that including：
Tester, the tester is used to carry out the first test to the wafer；
First relay module, first relay module is used to be connected between the tester and the wafer, and described first
Relay module is used to receive the first make-and-break signal of the tester output；
Single-chip microcomputer, the single-chip microcomputer receives the enabling signal of the tester, and the single-chip microcomputer is by AES to the crystalline substance
Circle carries out the second test；
Second relay module, second relay module is used to be connected between the single-chip microcomputer and the wafer, and described second
Relay module is used to receive the second make-and-break signal of the tester output；
3rd relay module, the 3rd relay module is connected between the tester and the single-chip microcomputer, the described 3rd after
Electric module receives the 3rd make-and-break signal of the tester output.
2. test system according to claim 1, it is characterised in that：
The test system also includes interface module, and the tester is connected by the interface module with the single-chip microcomputer, institute
Single-chip microcomputer is stated to be connected with the wafer by the interface module.
3. test system according to claim 2, it is characterised in that：
The interface module includes chip interface, set of test modules, interface microcontroller and tester interface, and the chip interface is used
It is connected in the chip with the wafer, the set of test modules is connected between the interface microcontroller and the chip interface,
The interface microcontroller is connected with the tester interface, and the interface microcontroller is used to be connected with the single-chip microcomputer, the survey
Examination instrument interface is used to be connected with the tester.
4. test system according to claim 3, it is characterised in that：
The chip interface has two, and the set of test modules has eight, and the interface microcontroller has eight, the survey
Examination instrument interface has two, and every four set of test modules are connected with a chip interface, each described test mould
Block group and an interface microcontroller, every four interface microcontrollers are connected with a tester interface.
5. test system according to claim 4, it is characterised in that：
The set of test modules includes five test modules, and the test module is connected in parallel on the chip interface and described
Between interface microcontroller.
6. test system according to claim 5, it is characterised in that：
The test module and the interface microcontroller are arranged along a straight line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621415299.8U CN206292349U (en) | 2016-12-21 | 2016-12-21 | A kind of test system for wafer |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621415299.8U CN206292349U (en) | 2016-12-21 | 2016-12-21 | A kind of test system for wafer |
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| CN206292349U true CN206292349U (en) | 2017-06-30 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106771950A (en) * | 2016-12-21 | 2017-05-31 | 珠海市中芯集成电路有限公司 | A kind of test system and its method of testing for wafer |
| CN113031669A (en) * | 2021-02-10 | 2021-06-25 | 国机集团科学技术研究院有限公司 | High-quality crystal cultivation key process environment vibration control technical analysis method |
-
2016
- 2016-12-21 CN CN201621415299.8U patent/CN206292349U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106771950A (en) * | 2016-12-21 | 2017-05-31 | 珠海市中芯集成电路有限公司 | A kind of test system and its method of testing for wafer |
| CN113031669A (en) * | 2021-02-10 | 2021-06-25 | 国机集团科学技术研究院有限公司 | High-quality crystal cultivation key process environment vibration control technical analysis method |
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