JP2009059875A - Semiconductor device manufacturing method and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device which inhibits an increase of the number of power sources for inspection, makes it possible to supply a power source current over an amount of supply of a power source current of a single power source for inspection, and includes an inspection process that can efficiently, certainly inspect the semiconductor device; and provide a semiconductor device. <P>SOLUTION: The semiconductor device 10 includes semiconductor circuit units 31, 32, 33 which operate at the same power source voltage. Moreover, the semiconductor device 10 includes power source lines 5, 6, 7 on which a power source voltage is applied independent of outside each other. Each of the power source lines 5, 6, 7 has a switch 12 which selectively changes between a non-common state that supplies a power source voltage to each semiconductor circuit units 31, 32, 33 independent of each other and a common state that the power source lines 5, 6 supply a power source voltage to the semiconductor circuit unit 31 at the same time and the power source line 7 supplies a power source voltage to the semiconductor circuit units 32, 33. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device, and more particularly, to a semiconductor device manufacturing method including a step of inspecting a semiconductor device having a plurality of terminals to which the same power supply voltage is input from different power supply devices. The present invention relates to a semiconductor device suitable for realizing the method.

  In the manufacturing process of a semiconductor integrated circuit device (hereinafter referred to as a semiconductor device), a plurality of semiconductor chips formed on a wafer by a diffusion process are sealed in a package after the diffusion process is completed. An inspection process for inspecting the functional characteristics in a stopped state and determining whether each semiconductor chip is good or defective is incorporated. SoC (system on chip) typified by system LSIs that are becoming larger and more functional with the increasing number of functions of semiconductor devices in recent years, there are test patterns that are input to semiconductor devices in order to inspect functional characteristics. It is getting longer.

  For this reason, inspection time such as in-process inspection and shipping inspection becomes longer, and the ratio of the inspection cost to the product cost is increased. As one means for solving such a problem, a BIST (Built-In Self) in which a circuit for generating a test pattern used for inspection and a circuit for compressing output determination data are incorporated in the semiconductor device at the design stage of the semiconductor device. Test) has been proposed.

  BIST tries to reduce the inspection cost by distributing the inspection function between the inspection device such as a tester and the semiconductor integrated circuit device (hereinafter referred to as DUT (Device Under Test)) to be inspected. Is. In particular, in a logic BIST intended for a random logic circuit, a circuit can be inspected with a very small test pattern by incorporating a random signal generator and an output pattern compressor in the semiconductor device. Therefore, the test pattern generation cost can be reduced. Further, since inspection can be performed with a very small number of pins, a high-performance system LSI can be inspected with an inexpensive inspection apparatus.

  Further, by multiplying an external input operation clock (for example, 100 MHz) from the inspection device by an internal circuit of the semiconductor device to generate a circuit operation reference clock (for example, 400 MHz), a clock faster than the external input operation clock. It is possible to carry out the inspection of the state in which it is operated stably. For this reason, even when a low-frequency clock signal is input, the inspection can be performed at the same speed (at-speed) as in actual use, and delay faults can be screened. Further, when the external input operation clock is, for example, a circuit operation reference clock, it is possible to perform an inspection in a state of operating at a speed higher than the operation clock frequency in actual use. In the future, the logic BIST inspection function is expected to increase the efficiency of SoC design, manufacturing and inspection, which will become increasingly complex, and greatly reduce the inspection cost. At the same time, it is expected that the time to commercialization of SoC can be greatly shortened.

  By the way, in BIST, in order to inspect a semiconductor device in a short time, inspection is performed in a state where as many circuit blocks constituting a circuit unit are operated at the same time as fast as possible. In this case, the amount of power consumed instantaneously inside the semiconductor device becomes extremely large. Therefore, at the time of inspection, it is necessary to supply a large power supply current from the outside that is greater than the operation current during actual use. For example, it is assumed that the operation current at the time of actual use of the semiconductor device to be inspected is 500 mA or less, and the current supply capability of the power supply for inspection provided in the inspection apparatus is 500 mA. In this case, the semiconductor device can be operated in an actual use state by the inspection power source. However, if the consumption current of the semiconductor device exceeds 500 mA at the time of inspection using the built-in inspection function of BIST (hereinafter referred to as inspection using BIST), the amount of power supply current supplied from the inspection power supply becomes insufficient. . In this case, inspection using BIST cannot be performed. For this reason, it is required for the inspection apparatus to enhance the current supply capability at the time of inspection.

  As a general technique for enhancing the current supply capability of the inspection power supply, there is a technique of using a plurality of inspection power supplies in parallel. That is, with a plurality of inspection power supplies connected in parallel via the common power supply wiring on the inspection substrate on which the DUT is placed, the power supply terminal of the DUT is connected to the common power supply wiring. In this case, since the power supplies for inspection connected in parallel output the same power supply voltage, the current supply capability can be increased as compared with the case where one power supply for inspection is used. Here, the inspection substrate refers to a substrate on which a circuit pattern that realizes electrical connection between the DUT and the inspection apparatus is formed. For example, a board constituting a socket board, a probe card or the like corresponds to the inspection board.

  FIG. 5 is a circuit diagram showing a connection state when a DUT having a plurality of power supply terminals and an inspection power source of the inspection apparatus are used in parallel to inspect the DUT. In FIG. 5, the DUT 100 has a structure in which a semiconductor chip 102 is sealed in a package 1. The semiconductor chip 102 includes a circuit group 3 that realizes the function of the DUT 100. In the example of FIG. 5, the circuit group 3 includes a plurality of circuit units such as a first logic circuit 31, an analog circuit 32, a first memory circuit 33, a second logic circuit 34, and a second memory circuit 35. Has been.

  In this example, the first logic circuit 31, the analog circuit 32, and the first memory circuit 33 operate with the same power supply voltage (for example, 3V), and the second logic circuit 34 and the second memory circuit 35 are operated. Are assumed to operate at the same other power supply voltage (for example, 5 V). Further, the semiconductor chip 102 includes power supply lines 5, 6, 7, 8, and 9 connected to the circuit units 31 to 35, respectively. Each circuit unit 31 to 35 operates by a power supply voltage applied to the power supply lines 5 to 9. The power supply lines 5 to 9 are connected to pads PD1, PD2, PD3, PD4, and PD5, which are terminals formed on the semiconductor chip 102, respectively. Each pad of PD1 to PD5 is connected to a plurality of external terminals L1, L2, L3, L4, and L5 provided in the package 1 via bonding wires W1, W2, W3, W4, and W5.

  When inspecting the DUT 100, the inspection apparatus 4 supplies a power supply voltage and a power supply current to the external terminals L1 to L5 of the DUT 100 via the inspection board 20. Here, it is assumed that a test using BIST is performed on the first logic circuit 31. In the inspection using the BIST, in the first logic circuit 31, a plurality of circuit blocks that are not simultaneously operated at the time of actual use operate simultaneously. Therefore, on the inspection board 20, the power supply wiring corresponding to the external terminal L1 is a common power supply wiring 21 for connecting a plurality of inspection power supplies in parallel. Here, inspection power supplies 41 and 42 included in the inspection apparatus 4 supply a power supply voltage and a power supply current to the external terminal L1 of the DUT 100 through the common power supply wiring 21. With this connection state, it is possible to increase the amount of power supply current supplied to the first logic circuit 31 in which the inspection using the BIST is performed.

  Further, the inspection power supplies 43, 44, 45, 46 provided in the inspection apparatus 4 supply a power supply voltage and a power supply current to the external terminals L 2, L 3, L 4, L 5 of the DUT 100 through the inspection board 20, respectively. In FIG. 5, the semiconductor chip 102 sealed in the package 1 is illustrated as the DUT 100. However, in the wafer state inspection, the probe provided on the inspection substrate 20 on the pads PD1 to PD5 on the semiconductor chip 102. A power supply voltage and a power supply current are supplied by contacting the needle.

  In order to determine whether or not the function of the DUT is normal, in general, a predetermined input signal is applied to the signal input terminal of the DUT, and a signal output from the signal output terminal is measured according to the input signal. Is implemented. In particular, for a DUT that performs digital signal processing, a predetermined low level and high level serial signal (hereinafter referred to as an input pattern) is input, and the measured output signal is an expected low level and high level serial signal. It is inspected whether it is a signal (hereinafter referred to as an output expected value pattern). In the inspection using BIST, an input pattern for generating a random signal is input to a random signal generator on a semiconductor chip.

  In the example of FIG. 5, an input pattern is input from the inspection apparatus 4 to the DUT 100 through an interface and a signal input terminal (not shown) in a state where the power supply voltage and the power supply current are supplied from the inspection power supplies 41 to 46. At this time, the output signal of the DUT 100 is taken into the measurement channel for inspection of the inspection apparatus 4 through a signal output terminal and an interface (not shown). The inspection device 4 compares the output signal with the output expected value pattern, and determines whether or not the DUT 100 correctly performs the specified operation during actual use.

  As a function test for assuring the normal operation of the DUT 100, the first logic circuit 31 and the second logic circuit 34 are operated at a low operating clock frequency (hereinafter referred to as low speed operation). In addition, an inspection using BIST, an inspection such as a scan circuit operation, and the like are performed in an operation in which the operation clock frequency is increased (hereinafter referred to as a high-speed operation). In addition, the first memory circuit 33 and the second memory circuit 35 are subjected to inspections such as a data read / write operation in a low speed operation and a high speed operation. Further, the analog circuit 32 is inspected for non-linearity error, differential linearity error, total harmonic distortion, signal-to-noise ratio, etc. of the A / D converter and D / A converter.

  In these inspections, the state in which each circuit unit 31 to 35 is operated independently of other circuit units and the state in which a plurality of circuit units are combined and operated are synchronized with the clock signal. Will be implemented respectively.

  In FIG. 5, the inspection power supplies 41 to 46 included in the inspection apparatus 4 have a current supply capability capable of supplying an operation current (for example, a maximum of 500 mA) of each circuit unit during actual use. However, in general, a logic circuit occupies a large circuit scale in the area of the entire semiconductor integrated circuit and consumes a large amount of power as compared with an analog circuit or a memory circuit. For this reason, the test power supplies 41 and 42 are connected in parallel to the first logic circuit 31, and the amount of current that can be supplied to the external terminal L1 is increased to 500 mA × 2 = 1 A. Thus, when the inspection using the BIST is performed, the power supply current that needs to be supplied to the first logic circuit 31 exceeds the current supply capability of one inspection power supply (for example, about 600 mA to Even in 1A), the DUT 100 can be operated normally. Here, in the inspection using the BIST for the second logic circuit 34, the power supply current that needs to be supplied to the second logic circuit 34 does not exceed the current supply capability of one inspection power supply. It is said.

  As shown in FIG. 5, by connecting a plurality of inspection power supplies in parallel to a power supply terminal through which a large current flows, a power supply current can be supplied without shortage, and a high-speed operation test using BIST can be performed. . Therefore, the test time can be shortened. In this configuration, the number of external terminals to which the power supply voltage and the power supply current are supplied is five, whereas the circuit group 3 is operated using six test power supplies during the test.

  On the other hand, in the inspection process of a semiconductor device, in order to further shorten the inspection time and reduce the inspection cost, simultaneous measurement for inspecting a plurality of DUTs simultaneously is performed. By simultaneously inspecting a plurality of DUTs in this way, the throughput of the inspection process can be improved and the inspection cost can be reduced. For example, when two DUTs are simultaneously measured in one inspection, the inspection time per DUT is halved.

  FIG. 6 is a circuit diagram showing a connection state between the DUT and the inspection power supply of the inspection apparatus when a plurality of DUTs 100 illustrated in FIG. 5 are inspected simultaneously. FIG. 6 shows an example in which the DUT 100a and the DUT 100b are inspected simultaneously. The structures of the DUT 100a and the DUT 100b are the same as those of the DUT 100 described above, and the parts belonging to the DUTs 100a and 100b are distinguished by adding a and b to the end of the reference numerals.

  In the example of FIG. 6, the power supply wiring corresponding to the external terminal L <b> 1 a of the DUT 100 a is the common power supply wiring 21 on the inspection board 20. The power supply wiring corresponding to the external terminal L1b of the DUT 100b is the common power supply wiring 22. Inspection power supplies 41 and 42 provided in the inspection apparatus 4 supply a power supply voltage and a power supply current to the external terminal L1a of the DUT 100a through the common power supply wiring 21. Also, the inspection power supplies 47 and 48 supply a power supply voltage and a power supply current to the external terminal L1b of the DUT 100b through the common power supply wiring 22. Further, the inspection power supplies 43, 44, 45, 46, 49, 50, 51, 52 provided in the inspection apparatus 4 are connected to the external terminals L2a, L3a, L4a, L5a, and the external terminals L2b, L3b of the DUT 100b through the inspection board 20. , L4b and L5b are supplied with a power supply voltage and a power supply current, respectively.

  With the above connection state, the power supply current supply amount to the first logic circuit 31a of the DUT 100a is increased to 500 mA × 2 = 1A, and the power supply current supply amount to the first logic circuit 31b of the DUT 100b is also 500 mA × 2 = 1A. Is increased. Thus, when the inspection using the BIST is performed, the power supply current that needs to be supplied to the first logic circuits 31a and 31b exceeds the power supply capability of one inspection power supply (for example, The DUTs 100a and 100b can be operated normally even at about 600 mA to 1 A).

  As shown in FIG. 6, the power supply current can be supplied without shortage by connecting a plurality of inspection power supplies in parallel to the power supply terminal through which a large current flows. In this case, a high-speed operation test using BIST can be simultaneously performed on both the DUT 100a and the DUT 100b. Therefore, the test time can be shortened. In this configuration, the number of external terminals to which the power supply voltage and the power supply current are supplied is ten, whereas the circuit groups 3a and 3b are operated using twelve test power supplies during the test. .

  According to the inspection method using a plurality of inspection power supplies that output the same voltage in parallel as described above, it is not necessary to individually improve the current supply capability of the inspection power supply of the inspection apparatus. In other words, the current supply capacity of the inspection device can be purchased without purchasing a new inspection device equipped with a large number of inspection power supplies with a high current supply capability or purchasing and replacing only a large number of inspection power sources with a high current supply capability. Can be improved.

In addition, there are the following patent documents as prior art related to the present invention.
JP 2001-296336 A

  However, in recent years, the number of connection terminals between a semiconductor device and an external circuit has increased, and in such a semiconductor device, various circuits such as a memory circuit, a logic circuit, and an analog circuit are mixedly mounted in order to realize various functions. ing. The power supply voltage for driving these circuits is not single, and the power supply voltage is often different depending on the circuit. For this reason, in the inspection of semiconductor devices, the number of inspection power supplies used at the same time is increasing. In such a situation, as described above, when an inspection is performed with one power supply line on a semiconductor chip supplied with a power supply voltage and a power supply current from a plurality of inspection power supplies, the following problems occur. Arise.

  That is, normally, the number of power supplies for inspection that can be installed in the casing of the inspection apparatus is limited. Further, as described above, it is not easy to add an inspection power supply or purchase a new large-scale inspection apparatus due to cost limitations. For this reason, in the inspection of a semiconductor device that requires a large number of power supplies for inspection as described above, it is difficult to secure a power supply for inspection only to supplement the amount of power supply current that can be supplied. Further, when performing simultaneous measurement of a plurality of semiconductor devices that require a larger number of power supplies for inspection, it becomes more difficult to secure a power supply for inspection only to supplement the amount of power supply current that can be supplied. .

  If an inspection power supply that can compensate for the amount of power supply current that can be supplied cannot be secured, a high-speed operation test using the BIST cannot be performed within the existing number of inspection power supplies. In particular, when the power supply current is insufficient at the time of inspection using the BIST, only an operation test close to a normal operation operation can be performed. In this case, it is impossible to reduce the inspection time by the inspection using the BIST. In addition, it becomes difficult to perform a large number of simultaneous measurements, and problems such as the inability to greatly shorten the inspection time occur. There is no effective inspection method for solving such problems.

  In the future, it is expected that an inspection apparatus for inspecting a product of a semiconductor device will need to be equipped with a larger number of inspection power sources and a larger number of inspection measurement channels (measuring instruments for measuring the output from the semiconductor device). . In the future, with the progress of DUT system LSI development, the scale of inspection equipment equipped with functions for inspecting digital circuits and analog circuits such as memory circuits and logic circuits will increase, and the inspection cost is expected to increase further. . On the other hand, due to the customization of the semiconductor device, the function according to the customization of the semiconductor device is required before the collection of the initial investment amount of the inspection facility is completed. In other words, further investment is required to expand the measurement function of the inspection apparatus itself, and it becomes difficult to recover the investment for the inspection apparatus in a short period of time. For this reason, the necessity for suppressing the increase in the number of power supplies for inspection with which the inspection apparatus is equipped increases more than before.

  The present invention has been made in view of the above-described conventional problems, and suppresses an increase in the number of power supplies for inspection and enables supply of a power supply current exceeding the power supply amount of a single power supply for inspection. It is an object of the present invention to provide a method for manufacturing a semiconductor device including an inspection process capable of efficiently and reliably inspecting the semiconductor device, and a semiconductor device suitable for carrying out the manufacturing method.

  The present invention employs the following means in order to achieve the above object. That is, the semiconductor device according to the present invention includes the first, second, and third semiconductor circuit units that operate at the same power supply voltage, and the first, second, and second power supply voltages that are independently applied from the outside. 3 power lines. Furthermore, each of the first, second and third power supply lines applies a power supply voltage to each of the first, second and third semiconductor circuit units independently of each other, and the first power supply And a common state in which the power supply voltage is simultaneously applied to the first semiconductor circuit unit by the line and the second power supply line, and the power supply voltage is selectively applied to the second and third semiconductor circuit units by the third power supply line. And a switch unit for switching to.

  According to this configuration, a single power supply device is connected to a specific semiconductor circuit unit in the semiconductor device that supplies a power supply current by switching the switch unit between a non-common state and a common state, and A state in which a plurality of power supply devices are connected to a specific semiconductor circuit unit can be switched. That is, the current supply capability to a specific semiconductor circuit unit can be increased as necessary without increasing the number of power supply devices of the inspection device. In this configuration, when the switch unit is in a common state, a common power supply voltage is supplied to the second and third semiconductor circuits through the third power supply line. Accordingly, power supply to the second semiconductor circuit is not interrupted. As a result, it is possible to perform a function test using the built-in test function of BIST that requires instantaneous supply of a large power supply current to the first semiconductor circuit without changing the connection state.

  In the above structure, the first, second and third semiconductor circuits, the first, second and third power supply lines and the switch portion can be formed on the same semiconductor substrate. In addition, the switch unit can be configured by three switch elements that selectively switch between a conduction state and a cutoff state. In this case, the first switch element is interposed in the first connection wiring that selectively electrically connects the first power supply line and the second power supply line. The second switch element is interposed in a second connection wiring that selectively electrically connects the second power supply line and the third power supply line. Further, the third switch element includes a second power supply line between a connection point between the second power supply line and the first connection wiring and a connection point between the second power supply line and the second connection wiring. Intervened in.

  In the above structure, the switch portion can also be configured by an element that can selectively maintain a non-common state or a common state without inputting a control signal. As such an element, for example, a flash memory element can be used.

  The semiconductor device is used in the non-common state in actual use, for example, and the same power supply potential is applied to the first, second, and third power supply lines by independent power supply devices. .

  On the other hand, in another aspect, the present invention provides a method for manufacturing a semiconductor device including a plurality of semiconductor circuit units to which a power supply voltage of the same potential is independently applied from power supply devices independent from each other in actual use. it can. That is, the method for manufacturing a semiconductor device according to the present invention includes the following first and second inspection steps. In the first inspection step, the first power supply device and the second power supply device simultaneously apply a power supply voltage to the first semiconductor circuit unit, and the second semiconductor circuit unit and the third semiconductor circuit unit With the third power supply device applying the power supply voltage, at least the electrical characteristics of the first semiconductor circuit unit are measured. In the second inspection step, the first power supply device applies a power supply voltage to the first semiconductor circuit unit, and the second power supply device applies a power supply voltage to the second semiconductor circuit unit. The electrical characteristics of the first, second, and third semiconductor circuit units are measured in a state where the power supply voltage is applied to the third semiconductor circuit unit by the third power supply device.

  For example, in the first inspection step, measurement of an inspection item in which the power supply current supply amount during operation of the first semiconductor circuit is insufficient due to the upper limit current supply amount of the first power supply device is performed. In the second inspection step, measurement of inspection items is performed in which the power supply current supply amount during the operation of the first semiconductor circuit due to the upper limit current supply amount of the first power supply device is not insufficient. In this case, the inspection performed in the first inspection step is a step of measuring electrical characteristics in a state where the first semiconductor circuit unit is operated by a clock signal having a frequency higher than the operation clock frequency during actual use. And measuring the electrical characteristics in a state where the second and third semiconductor circuit units are operated by a clock signal having a frequency lower than that of the first semiconductor circuit unit.

  According to the present invention, the switch unit is switched between the non-common state and the common state, so that the single power supply device is connected to the specific semiconductor circuit unit in the semiconductor device, and the specific semiconductor circuit unit A state in which a plurality of power supply devices are connected can be selected. In other words, the power supply current supply capability to a specific semiconductor circuit unit can be increased as necessary without increasing the number of power supply devices of the inspection device. As a result, even when the power supply current required by a specific semiconductor circuit unit greatly exceeds the operation current during actual use for the circuit operation at the time of inspection using the BIST, the power supply current can be supplied without shortage. it can. As a result, the function inspection using the BIST for the semiconductor device can be performed without increasing the number of power supply devices of the inspection device and without changing the connection state between the inspection device and the semiconductor device. Further, even in a situation where the switch unit is in a common state, since the power supply voltage is applied to other circuit units other than the specific circuit unit, it is possible to inspect other circuit units. Therefore, a series of inspections for the semiconductor device can be performed in a short time and at a low cost.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First embodiment)
In the present embodiment, when a semiconductor device including five semiconductor circuit units is inspected, only five inspection power sources built in the inspection device (tester) are used and supplied to one semiconductor circuit unit of the semiconductor device. The present invention is embodied as an example of increasing the power supply current amount.

  FIG. 1 is a schematic configuration diagram showing a semiconductor device according to the first embodiment of the present invention. In FIG. 1, parts having the same operations and effects as those in the configuration diagram of the conventional semiconductor device shown in FIG.

  As shown in FIG. 1, the semiconductor device 10 of this embodiment has a structure in which a semiconductor chip 2 is sealed in a package 1. The semiconductor chip 2 includes a circuit group 3 that realizes the function of the semiconductor device 10. In the present embodiment, as in the case of FIG. 5, the circuit group 3 includes the first logic circuit 31, the analog circuit 32, the first memory circuit 33, the second logic circuit 34, and the second memory circuit 35. It consists of units. In addition, the semiconductor chip 2 includes power lines 5, 6, 7, 8, and 9 that supply a power voltage and a power current to the circuit units 31 to 35. Here, the first logic circuit 31, the analog circuit 32, and the first memory circuit 33 operate with the same power supply voltage (for example, 3V), and the second logic circuit 34 and the second memory circuit 35 It is assumed that it operates with the same power supply voltage (for example, 5V). The power supply lines 5 to 9 are electrically connected to pads PD1, PD2, PD3, PD4, and PD5, which are terminals formed on the semiconductor chip 2, respectively. Each of the pads PD1 to PD5 is connected to a plurality of external terminals L1, L2, L3, L4, and L5 included in the package 1 via bonding wires W1, W2, W3, W4, and W5. The semiconductor device 10 is used in a state where the power supply voltage applied to each of the external terminals L1 to L5 is applied to each of the circuit units 31 to 35 during actual use.

  In the semiconductor device 10 of the present embodiment, the electrical connection state of the power supply line 5, the power supply line 6, and the power supply line 7, and the first logic circuit 31, the analog circuit 32, and the first memory circuit 33 is in a non-common state. And a switch unit 12 that selectively switches to a common state. Here, the non-common state means that the power line 5 is independently connected to the first logic circuit 31, the power line 6 is independently connected to the analog circuit 32, and the power line 7 is independent to the first memory circuit 33. It is in a state connected to. That is, the power supply line connected to the external terminal L1 (pad PD1), the power supply line connected to the external terminal L2 (pad PD2), and the power supply line connected to the external terminal L3 (pad PD3) are independent from each other. Are electrically connected to the first logic circuit 31, the analog circuit 32, and the first memory circuit 33, respectively. The common state is a state in which the power supply line 5 and the power supply line 6 are connected to the first logic circuit, and the power supply line 7 is connected to the analog circuit 32 and the first memory circuit 33. That is, the power supply line connected to the external terminal L1 (pad PD1) and the power supply line connected to the external terminal L2 (pad PD2) are electrically connected to the first logic circuit 31, and the external terminal L3 (pad PD3). The power supply line connected to is electrically connected to the analog circuit 32 and the first memory circuit 33.

  The switch unit 12 includes three switch elements SW1, SW2, and SW3. The switch element SW1 is interposed in a connection wiring 61 that electrically connects the power supply line 5 and the power supply line 6. The switch element SW1 selectively switches between a closed state (conductive state) and an open state (cut-off state), whereby the power supply line 5 and the power supply line 6 are electrically connected, the power supply line 5 and the power supply The state in which the line 6 is electrically separated is switched. The switch element SW2 is interposed in a connection wiring 62 that electrically connects the power supply line 6 and the power supply line 7. The switch element SW2 is selectively switched between a closed state and an open state, so that the power line 6 and the power line 7 are electrically connected to each other and the power line 6 and the power line 7 are electrically separated. Switch between the states to be performed. The switch element SW3 is interposed in the power supply line 6 between the connection point 63 between the power supply line 6 and the connection wiring 61 and the connection point 64 between the power supply line 6 and the connection wiring 62. The switch element SW3 selectively switches between a closed state and an open state, whereby the analog circuit 32 and the power supply line 6 (pad PD2) are electrically connected, and the analog circuit 32 and the power supply line 6 (pad). PD2) is switched to the electrically separated state.

  The switch elements SW1, SW2, and SW3 are configured by semiconductor elements that selectively switch between a closed state and an open state. For example, transfer gates can be used as the switch elements SW1, SW2, and SW3. Here, the transfer gate refers to a transistor switch that switches a conduction state or a cutoff state between a source and a drain by applying an open / close control signal to the gate of the MOS transistor.

  The opening / closing control of the switch element SW1 is performed when the inspection control circuit 11 formed on the semiconductor chip 2 inputs the opening / closing control signal S1 to the switch element SW1. The switching control of the switch element SW2 is performed when the inspection control circuit 11 inputs the opening / closing control signal S2 to the switch element SW2. The switching control of the switch element SW3 is performed when the inspection control circuit 11 inputs the switching control signal S3 to the switch element SW3.

  FIG. 2 is a schematic diagram showing the relationship between the open / close states of the switch elements SW1, SW2, and SW3 and the non-common state and the common state. 2A shows a non-common state, and FIG. 2B shows a common state.

  As shown in FIG. 2A, in the non-common state, the switch element SW3 is closed, and the switch element SW1 and the switch element SW2 are opened. In this case, as described above, the external terminal L1 (pad PD1) is electrically connected to the logic circuit 31 through the power supply line 5. The external terminal L2 (pad PD2) is electrically connected to the analog circuit 32 through the power supply line 6. The external terminal L3 (pad PD3) is electrically connected to the first memory circuit 33 through the power supply line 7.

  Further, in the common state as shown in FIG. 2B, the switch element SW3 is opened, and the switch element SW1 and the switch element SW2 are closed. In this case, as described above, the external terminal L1 (pad PD1) is electrically connected to the first logic circuit 31 through the power supply line 5, and the external terminal L2 (pad PD2) is connected to the pad PD2 and the connection point 63. Are electrically connected to the first logic circuit 31 through the power supply line 6, the connection wiring 61 and the power supply line 5. The external terminal L3 (pad PD3) is electrically connected to the first memory circuit 33 through the power supply line 7 and is also electrically connected to the analog circuit 32 through the connection wiring 62 and the power supply line 6. The external terminal L2 (pad PD2) is electrically separated from the analog circuit 32.

  As described above, in the semiconductor device 10 of FIG. 1, the power supply devices independent of each other are connected to the external terminals L1 to L5, respectively, and the power supply voltage and the power supply current are supplied to the circuit units 31 to 35 in actual use. Is done. That is, the switch unit 12 is in a non-common state during actual use. In this case, the first logic circuit 31 operates with a power supply voltage and a power supply current supplied independently to the external terminal L1 (pad PD1). The analog circuit 32 operates by a power supply voltage and a power supply current supplied independently to the external terminal L2 (pad PD2). The first memory circuit 33 operates with a power supply voltage and a power supply current supplied independently to the external terminal L3 (pad PD3). Therefore, the switch element SW3 is preferably a normally-on type switch element, and the switch elements SW1 and SW2 are preferably normally-off type switch elements.

  FIG. 3 is a circuit diagram showing a connection state between the semiconductor device 10 (hereinafter referred to as DUT 10) and the inspection device 4 when the above-described semiconductor device 10 is inspected. In FIG. 3, the inspection power supply devices 41, 42, 43, 44, 45 (hereinafter referred to as inspection power supply) included in the inspection device 4 are operation currents (for example, maximum) when the circuit units 31 to 35 are actually used. 500 mA) can be supplied. Here, the inspection power supplies 41 to 45 included in the inspection apparatus 4 supply the power supply voltage and the power supply current to the external terminals L1, L2, L3, L4, and L5 of the DUT 10 through the inspection board 20, respectively. The inspection power supplies 41 to 45 are configured by a voltage source and an ammeter that measures a current flowing through the voltage source. In FIG. 3, illustration of terminals and wirings not involved in the power supply line is omitted, but the DUT 10 is a signal for inputting a signal to be processed by the DUT 10 in addition to the external terminals L1 to L5 to which the power supply voltage is applied. An input terminal, a signal output terminal for outputting a signal processed by the DUT 10, a clock terminal for inputting a clock signal for synchronizing the operations of the circuit units 31 to 35, and the like are provided.

  Further, the inspection device 4 has a signal generator for inputting a predetermined inspection input signal to the signal input terminal, a clock generator for applying a clock signal to the clock terminal, and a test input signal applied to the DUT. An inspection measurement channel for measuring a signal output from the signal output terminal is provided. In the following description, it is assumed that the inspection apparatus 4 inputs a control signal that instructs the inspection control circuit 11 to switch the switch elements SW1, SW2, and SW3 via an interface (not shown).

  3, when the DUT 10 is inspected, each of the inspection power supplies 41, 42, 43 of the inspection apparatus 4 is supplied to the external terminals L1, L2, L3 via the inspection substrate 20 with respect to the DUT 10 with a predetermined power supply voltage. (For example, 3V) is applied. Each of the inspection power supply 44 and the inspection power supply 45 applies a predetermined power supply voltage (for example, 5 V) to the external terminals L4 and L5. In this state, the first logic circuit 31, the analog circuit 32, the first memory circuit 33, and the second logic circuit 34 that constitute the circuit group 3 of the DUT 10 from the inspection apparatus 4 via an interface and a signal input terminal (not shown). A predetermined input pattern is input to each of the second memory circuits 35 as an inspection input signal.

  In addition, signals output from the first logic circuit 31, the analog circuit 32, the first memory circuit 33, the second logic circuit 34, and the second memory circuit 35 in accordance with the test input signal are illustrated in the figure. Not taken in by the inspection device 4 via the signal output terminal and the interface. The inspection device 4 compares each output signal with the output expected value pattern according to the clock signal input to the DUT 10. The function inspection items in the inspection process for assuring the normal operation of the DUT 10 are the same as those described in the background art, so description thereof is omitted here. The inspection process will be specifically described below.

  In the inspection process, first, an inspection is performed on the DUT 10 in FIG. 3 with the switch unit 12 in the common state shown in FIG. Here, the inspection for the inspection item in which the power supply current supply amount during operation of the circuit unit is insufficient due to the upper limit current supply amount of the power supply for inspection, that is, the current consumption amount of the first logic circuit 31 is the power supply for inspection. Inspection exceeding the upper limit of the current supply capacity of 41 is performed. Here, a test is performed in an operation state in which a large power supply current is required for the first logic circuit 31 and a large current consumption is required. The inspection in an operating state with a large current consumption is, for example, an inspection using BIST in an operation in which the operation clock frequency is higher than that in actual use (hereinafter referred to as high-speed operation), an inspection of scan circuit operation, and the like. . At this time, the inspection device 4 inputs a control signal to the inspection control circuit 11 to bring the switch unit 12 into the common state, opens the switch element SW3, and closes the switch element SW1 and the switch element SW2. To do. In this state, the inspection apparatus 4 applies a predetermined power supply voltage to the DUT 10 by the inspection power supplies 41 to 45. Thus, the power supply voltage and the power supply current are supplied to the first logic circuit 31 from both the inspection power supply 41 and the inspection power supply 42 through the external terminals L1 and L2 (pads PD1 and PD2). At this time, a common power supply voltage is applied to the analog circuit 32 and the first memory circuit 33 from the inspection power supply 43 through the external terminal L3 (pad PD3).

  While the high-speed operation test with large current consumption is performed on the first logic circuit 31, the analog circuit 32 and the first memory circuit 33 to which the power supply voltage common to the analog circuit 32 is applied are Inspections with low current consumption are performed. For example, the analog circuit 32 is subjected to inspections such as non-linearity error inspection and differential linearity error inspection of A / D converters and D / A converters with thinned measurement points. In addition, the first memory circuit 33 is subjected to a data read / write operation test in an operation (hereinafter referred to as a low speed operation) in which the operation clock frequency is approximately equal to the operation clock frequency during actual use. Therefore, the power supply current that needs to be supplied to the analog circuit 32 and the first memory circuit 33 does not exceed the upper limit of the current supply amount of the inspection power supply 43.

  By mounting the switch unit 12 on the semiconductor device 10 and using this method, the first logic circuit 31 can be used even when only one inspection power source of the inspection device 4 is connected to the external terminal L1. In addition, a power supply current can be supplied from the inspection power supply 41 and the inspection power supply 42. As a result, it is possible to prevent a supply shortage from occurring in the power supply current required by the first logic circuit 31 during the inspection using the BIST. As a result, even if the number of inspection power supplies built in the inspection apparatus 4 is limited, the supply capability of the power supply current to the first logic circuit 31 can be enhanced and the inspection using the BIST can be performed. In addition, such high-speed operation inspection is intended to detect a defective product having a fatal defect or a potential defect in manufacturing in the diffusion process of the semiconductor device at an early stage and exclude it as a defect from the measurement target. .

  Further, in the test, when the signal processed by the first logic circuit 31 is D / A converted in the analog circuit 32, the analog circuit 32 and the first memory circuit 33 are connected through the switch element SW2. Therefore, there is a concern about the propagation of power supply noise between the analog circuit 32 and the first memory circuit 33. However, since the power supply fluctuation is small in the inspection with the measurement points thinned out and the inspection of the low speed operation, both the analog circuit 32 and the first memory circuit 33 suppress the generation of power supply noise during the circuit operation. For this reason, the power supply noise generated during the circuit operation of the analog circuit 32 propagates to the first memory circuit 33 via the commonly connected power supply line, thereby preventing the circuit operation of the first memory circuit 33. There is no. Further, power noise generated during the circuit operation of the first memory circuit 33 is not propagated to the analog circuit 32 via the power line connected in common, and the circuit operation of the analog circuit 32 is not hindered. Therefore, the analog circuit 32 and the first memory circuit 33 operate without causing a malfunction due to mutual interference such that a normal output signal cannot be obtained. For this reason, the test | inspection in the stable operation state can be performed.

  When the inspection in the common state is completed, the DUT 10 is inspected with the switch unit 12 in the non-common state shown in FIG. In the non-common state, inspection of the inspection item in which the power supply current supply amount during operation of the semiconductor circuit unit does not become insufficient due to the upper limit current supply amount of the power supply for inspection, that is, consumption of the first logic circuit 31. An inspection is performed in which the amount of current does not exceed the upper limit of the current supply capability of the inspection power supply 41.

  The inspection performed with the switch unit 12 in a non-common state is an inspection of the first logic circuit 31 such as a scan circuit operation at a low speed operation. Since this inspection item is inspected in a state where a low clock frequency equivalent to the operation clock frequency in actual use, which is a lower frequency than the inspection using the BIST, is input, the power supply required by the first logic circuit 31 The amount of current does not exceed the current supply capability of the inspection power supply 41. Therefore, the first logic circuit 31 operates normally without malfunction by using only the power supply current supplied from one inspection power supply 41.

  In the inspection of the non-common state, the first memory circuit 33 and the second memory circuit 35 are subjected to inspection such as data read / write operation at high speed. The analog circuit 32 is inspected for A / D converter and D / A converter nonlinearity error, differential linearity error, total harmonic distortion, signal-to-noise ratio, and the like. In these inspections, the state in which each circuit unit 31 to 35 is operated independently of other circuit units and the state in which a plurality of circuit units are combined and operated are synchronized with the clock signal. Will be implemented respectively.

  In the case of an inspection in which the switch unit 12 is in a non-common state, a power supply voltage is applied to the analog circuit 32 from the inspection power supply 42 alone, and a power supply voltage is applied to the first memory circuit 33 from the inspection power supply 43 alone. Is done. For this reason, the power supply noise generated by the power supply fluctuation during the circuit operation of the analog circuit 32 does not propagate to the first memory circuit 33 and does not hinder the circuit operation of the first memory circuit 33. Similarly, power supply noise generated by power supply fluctuations during circuit operation of the first memory circuit 33 is not propagated to the analog circuit 32 and does not hinder the circuit operation of the analog circuit 32. Therefore, for analog circuit 32, A / D converter and D / A converter non-linearity error test, differential linearity error test, and circuit operation test of total harmonic distortion rate and signal-to-noise ratio are stable. The first memory circuit 33 can be stably subjected to the data read / write operation inspection in the low-speed operation and the high-speed operation. In addition, such normal operation inspection is performed under the condition close to the operation at the time of actual use, normal ones that meet the specifications of operation speed and operation characteristics are selected as good products, and inferior ones are judged as defective from the measurement target. It is intended to be excluded.

  As described above, according to the present embodiment, by switching the switch unit 12 between the non-common state and the common state, the single logic power supply 41 is connected to the first logic circuit 31, and A state in which a plurality of power supplies for inspection 41 and 42 are connected to the first logic circuit 31 can be selected. That is, the current supply capability to a specific semiconductor circuit unit can be increased as necessary without increasing the number of power supplies for inspection of the inspection apparatus 4. Therefore, even when a single power supply for inspection, such as a function inspection using a BIST for a semiconductor device, is in a state where the amount of power supply current is insufficient, a plurality of power supplies for inspection are connected to cause a power supply current shortage. An accurate inspection without malfunction can be performed. At this time, since the power supply voltage is also applied to the other circuit units other than the specific circuit unit, the other circuit units can be inspected.

  Further, in the present embodiment, as described above, the functional inspection, which is a high-speed operation test using BIST, and the inspection in the power supply state close to actual use can be performed on the same inspection board, so that the test time can be shortened. be able to. As a result, a series of inspections on the semiconductor device can be performed in a short time and at a low cost.

  In addition, the function test | inspection which combined the above-mentioned several circuit unit includes the test | inspection implemented by making the switch part 12 into a non-common state. For such a test, the first logic circuit 31 and the second logic circuit 34 communicate with each other, a test of the circuit operation of the logic circuit close to actual use, and the first memory circuit 33 and the second memory circuit 35 are performed. Of the circuit operation of the memory circuit close to actual use, and the communication of the first logic circuit 31, the second logic circuit 34, and the analog circuit 32 of the logic circuit and analog circuit close to actual use. Inspection of circuit operation, and further one-chip close to actual use in which the first logic circuit 31, the analog circuit 32, the first memory circuit 33, the second logic circuit 34, and the second memory circuit 35 are communicated. The circuit operation inspection is included.

(Second Embodiment)
Subsequently, a second embodiment of the present invention will be described. In the present embodiment, an example in which a plurality of DUTs are simultaneously measured by the above-described inspection method will be described. FIG. 4 is a circuit diagram showing a connection state of power supplies between the DUT and the inspection apparatus when a plurality of DUTs 10 illustrated in FIG. 3 are inspected simultaneously. FIG. 4 shows an example in which the DUT 10a and the DUT 10b are inspected simultaneously. The structures of the DUT 10a and the DUT 10b are the same as those of the DUT 10 described above, and the parts belonging to the DUTs 10a and 10b are distinguished from each other by adding a and b to the end of the code.

  In the example of FIG. 4, the inspection power sources 41, 42, 43, 44, 45, 46, 47, 48, 49, 50 provided in the inspection apparatus 4 are connected to the external terminals L 1 a, L 2 a, L 3 a, L 4 a, DUT 10 a through the inspection board 20. A power supply voltage and a power supply current are supplied to the external terminals L1b, L2b, L3b, L4b, and L5b of L5a and DUT 10b, respectively. In FIG. 4, description of terminals and wirings not involved in the power supply line is omitted. Moreover, the switch parts 12a and 12b will be in a non-common state at the time of actual use. In the following description, the inspection apparatus 4 inputs a control signal for instructing switching of the switch elements SW1a, SW2a, and SW3a to the inspection control circuit 11a of the DUT 10a via an interface (not shown), and to the inspection control circuit 11b of the DUT 10b. In the following description, it is assumed that a control signal for instructing switching of the switch elements SW1b, SW2b, and SW3b is input.

  When performing the simultaneous inspection of the DUT 10a and the DUT 10b, a predetermined power supply voltage (for example, 3V) is applied to the external terminal L1a from the inspection power supply 41 of the inspection apparatus 4 to the external terminal L1a with respect to the DUT 10a as in the case of FIG. A predetermined power supply voltage (for example, 3 V) is applied from the inspection power supply 42 to the external terminal L2a via the inspection board 20, and a predetermined power supply voltage is applied from the inspection power supply 43 to the external terminal L3a via the inspection board 20. (For example, 3V) is applied. Further, a predetermined power supply voltage (for example, 5 V) is applied from the inspection power supply 44 and the inspection power supply 45 to the external terminals L4a and L5a, respectively.

  Similarly, a predetermined power supply voltage (for example, 3V) is applied from the inspection power supply 46 of the inspection apparatus 4 to the external terminal L1b via the inspection substrate 20 to the DUT 10b, and the predetermined power supply from the inspection power supply 47 to the external terminal L2b. A power supply voltage (for example, 3V) is applied, and a predetermined power supply voltage (for example, 3V) is applied from the inspection power supply 48 to the external terminal L3b. Further, a predetermined power supply voltage (for example, 5 V) is applied to the external terminals L4b and L5b from the inspection power supply 49 and the inspection power supply 50, respectively.

  In this state, the first logic circuit 31a, the analog circuit 32a, the first memory circuit 33a, the second logic circuit 34a, and the second logic circuit of the DUT 10a are connected from the inspection device 4 through an interface and a signal input terminal (not shown). A predetermined input pattern is input as an inspection input signal to each of the memory circuits 35a. Similarly, a predetermined input pattern is input as a test input signal to each of the first logic circuit 31b, the analog circuit 32b, the first memory circuit 33b, the second logic circuit 34b, and the second memory circuit 35b of the DUT 10b. Is done.

  In addition, signals output from the first logic circuit 31a, the analog circuit 32a, the first memory circuit 33a, the second logic circuit 34a, and the second memory circuit 35a in accordance with the test input signal are signals not shown. It is taken into the inspection apparatus 4 through the output terminal and the interface. Similarly, signals output from the first logic circuit 31b, the analog circuit 32b, the first memory circuit 33b, the second logic circuit 34b, and the second memory circuit 35b in accordance with the test input signal are not shown. The data is taken into the inspection device 4 through the signal output terminal and the interface. The inspection device 4 compares each output signal with the expected output value pattern according to the clock signal input to the DUTs 10a and 10b.

  In the inspection process of the present embodiment, first, an inspection is performed on the DUTs 10a and 10b with the switch unit 12a and the switch unit 12b in the common state shown in FIG. In the inspection of the state, inspections using BIST in a high-speed operation that requires a large supply current supply to the first logic circuit 31a and the first logic circuit 31b, inspections such as scan circuit operation, and the like are performed. The At this time, the inspection device 4 inputs a control signal to the inspection control circuits 11a and 11b in order to make the switch units 12a and 12b common. With this control signal, the switch elements SW3a, SW3b are opened, and the switch elements SW1a, SW2a, SW1b, SW2b are closed.

  In this state, the inspection apparatus 4 applies a predetermined power supply voltage to the DUT 10a by the inspection power supplies 41 to 45, and applies a predetermined power supply voltage to the DUT 10b by the inspection power supplies 46 to 50. Thereby, the power supply voltage and the power supply current are supplied to the first logic circuit 31a of the DUT 10a from both the inspection power supply 41 and the inspection power supply 42 through the external terminals L1a and L2a. At this time, a common power supply voltage is applied to the analog circuit 32a and the first memory circuit 33a from the inspection power supply 43 through the external terminal L3a. Similarly, the first logic circuit 31b of the DUT 10b is supplied with a power supply voltage and a power supply current from both the inspection power supply 46 and the inspection power supply 47 through the external terminals L1b and L2b. A common power supply voltage is applied from the inspection power supply 48 to the analog circuit 32b and the first memory circuit 33b through the external terminal L3b.

  In the above state, the inspection apparatus 4 performs, for example, inspection using the BIST at high speed operation and inspection with large current consumption such as scan circuit operation on the first logic circuits 31a and 31b. Even when a plurality of DUTs are measured simultaneously, the high-speed operation inspection detects a defective product having a fatal defect or a potential defect in manufacturing a semiconductor device at an early stage, and excludes it from the measurement object as a defect. The purpose is that.

  While a high-speed operation test with a large current consumption is being performed on the first logic circuits 31a and 31b, the analog circuits 32a and 32b are thinned out from the measurement points as in the first embodiment. Inspections with low current consumption such as non-linearity error inspection and differential linearity error inspection of A / D converters and D / A converters are performed. The first memory circuits 33a and 33b to which a common power supply voltage is applied to the analog circuits 32a and 32b are subjected to a data reading / writing operation inspection at a low speed operation. As described in the first embodiment, the power supply current that needs to be supplied to the analog circuit 32 a and the first memory circuit 33 a does not exceed the upper limit of the current supply amount of the test power supply 43. Further, the power supply current that needs to be supplied to the analog circuit 32 b and the first memory circuit 33 b does not exceed the upper limit of the current supply amount of the inspection power supply 48.

  As described above, even when the switch unit 12a and the switch unit 12b are in a common state, even when only one inspection power source of the inspection apparatus 4 is connected to each of the external terminals L1a and L1b, The amount of current supply can be increased. That is, a power supply current can be supplied from the inspection power supplies 41 and 42 to the first logic circuit 31a, and a power supply current can be supplied from the inspection power supplies 46 and 47 to the first logic circuit 31b. As a result, it is possible to prevent a supply shortage from occurring in the power supply current required by the first logic circuits 31a and 31b during the inspection using the BIST. Therefore, even if the number of power supplies for inspection built in the inspection apparatus 4 is limited, it is possible to increase the power supply capability of the first logic circuits 31a and 31b and perform inspection using the BIST. As a result, in this embodiment, the high-speed operation test can be stably performed even when the number of inspection power supplies built in the inspection apparatus 4 is limited, and the test time can be shortened by simultaneously measuring a plurality of DUTs. Can be achieved.

  In the inspection, when the D / A conversion is performed on the signals processed by the first logic circuits 31a and 31b in the analog circuits 32a and 32b, the analog circuits 32a and 32b and the first memory are respectively used in the DUTs 10a and 10b. There is a concern about the propagation of power supply noise between the circuits 33a and 33b. However, as described above, the power supply noise generated during the circuit operation of the analog circuits 32a and 32b does not disturb the circuit operation of the first memory circuits 33a and 33b. Further, the power supply noise generated during the circuit operation of the first memory circuits 33a and 33b does not disturb the circuit operation of the analog circuits 32a and 32b. Therefore, the analog circuits 32a and 32b and the first memory circuits 33a and 33b operate without causing malfunction due to mutual interference. For this reason, the test | inspection in the stable operation state can be performed.

  When the inspection in the common state is completed, an inspection is performed on the DUTs 10a and 10b with the switch units 12a and 12b in the non-common state shown in FIG. Such inspection is performed in the case where a plurality of DUTs are measured at the same time, and is operated in a state close to the operation at the time of actual use. Is excluded from the measurement target as defective. In the non-common state, an inspection is performed on an inspection item in which the current consumption amount of the first logic circuits 31a and 31b does not exceed the upper limit of the current supply capability of the inspection power sources 41 and 46.

  The inspection performed with the switch unit 12 in a non-common state is an inspection of a scan circuit operation or the like in a low-speed operation for the first logic circuits 31a and 31b, as in the first embodiment. Therefore, the amount of power supply current required by the first logic circuit 31 a does not exceed the current supply capability of the inspection power supply 41. Further, the power supply current amount required by the first logic circuit 31b does not exceed the current supply capability of the inspection power supply 46. For this reason, the first logic circuits 31a and 31b operate normally without malfunction by only the power supply current supplied from the respective inspection power supplies 41 and 46.

  In the inspection of the non-common state, the first memory circuits 33a and 33b and the second memory circuits 35a and 35b are inspected such as a data read / write operation in a high-speed operation. Further, the analog circuits 32a and 32b are inspected for non-linearity error, differential linearity error, total harmonic distortion, signal-to-noise ratio, etc. of the A / D converter and D / A converter. In these inspections, the inspection of the state in which each circuit unit 31a to 35a, 31b to 35b is operated independently of the other circuit units and the inspection of the state in which a plurality of circuit units are combined are operated. It is implemented in the state synchronized with each.

  In an inspection in which the switch unit 12 is in a non-common state, a power supply voltage is applied independently from the inspection power sources 42 and 47 to the analog circuits 32a and 32b, and the inspection power sources 43 and 33b are applied to the first memory circuits 33a and 33b. A power supply voltage is applied from 48 alone. For this reason, the power supply noise generated by the power supply fluctuation during the circuit operation of the analog circuit 32a32b does not disturb the circuit operation of the first memory circuits 33a and 33b. Similarly, the power supply noise generated by the power supply fluctuation during the circuit operation of the first memory circuits 33a and 33b does not disturb the circuit operation of the analog circuits 32a and 32b. Therefore, for the analog circuits 32a and 32b, A / D converter and D / A converter non-linearity error inspection, differential linearity error inspection, and circuit operation inspection of total harmonic distortion rate and signal-to-noise ratio are performed. It can be implemented stably. In addition, the first memory circuits 33a and 33b can be stably subjected to the data reading / writing operation inspection in the low-speed operation and the high-speed operation.

  As described above, according to the present embodiment, as in the first embodiment, the current supply capability to a specific semiconductor circuit unit can be increased as needed without increasing the number of inspection power supplies of the inspection apparatus. Can be increased. Therefore, even when a single power supply for inspection, such as a function inspection using a BIST for a semiconductor device, is in a state where the amount of power supply current is insufficient, a plurality of power supplies for inspection are connected to cause a power supply current shortage. An accurate inspection without malfunction can be performed. At this time, since the power supply voltage is also applied to the other circuit units other than the specific circuit unit, the other circuit units can be inspected.

  Further, in the present embodiment, as described above, the functional inspection, which is a high-speed operation test using BIST, and the inspection in the power supply state close to actual use can be performed on the same inspection board, so that the test time can be shortened. be able to. As a result, a series of inspections on the semiconductor device can be performed in a short time and at a low cost. Furthermore, in this embodiment, when a plurality of semiconductor devices are inspected at the same time, it is possible to secure a sufficient number of inspection power sources that can be allocated to the inspection of other semiconductor devices. The number of DUTs that can be measured can be increased compared to the conventional case, and the inspection cost can be reduced.

  In the first and second embodiments, the configuration in which the switch unit is provided in the semiconductor device has been described. However, the switch unit is, for example, in a resin mold between a bonding pad of a semiconductor chip and an external terminal. Alternatively, it may be provided between the power line and the external terminal. The switch part can also be formed on the inspection substrate.

  As described above, according to the present invention, a single power supply device is connected to a specific semiconductor circuit unit in a semiconductor device that supplies power supply current by switching the switch unit between a non-common state and a common state. And a state in which a plurality of power supply devices are connected to the specific semiconductor circuit unit can be selected. In other words, the power supply current supply capability to a specific semiconductor circuit unit can be increased as necessary without increasing the number of power supply devices of the inspection device. As a result, even when the power supply current required by a specific semiconductor circuit unit greatly exceeds the operation current during actual use for the circuit operation at the time of inspection using the BIST, the power supply current can be supplied without shortage. it can. As a result, the function inspection using the BIST for the semiconductor device can be performed without increasing the number of power supply devices of the inspection device and without changing the connection state between the inspection device and the semiconductor device. Further, even in a situation where the switch unit is in a common state, since the power supply voltage is applied to other circuit units other than the specific circuit unit, it is possible to inspect other circuit units. Therefore, a series of inspections for the semiconductor device can be performed in a short time and at a low cost.

  The present invention is not limited to the embodiment described above, and various modifications and applications are possible within the scope of the effects of the present invention. In each of the above embodiments, the configuration in which the inspection control circuit 11 outputs the open / close control signal to each switch element SW1, SW2, SW3 constituting the switch unit 12 based on the instruction of the inspection device 4 is described. It is not limited to. For example, if the switch element SW1 is configured by a P-channel transistor and the switch element SW3 is configured by an N-channel transistor, the switch unit can be switched by inputting the same open / close control signal to the switch elements SW1 and SW3. it can. The same applies to the combination of the switch element SW2 and the switch element SW3.

  In addition, the switch element may be configured by a switch element that includes a floating gate such as a flash memory element and can selectively maintain a non-common state or a common state without input of a control signal. According to this configuration, the inspection control circuit can select the non-common state and the common state only by inputting the open / close control signal to the switch element only when the switch unit is switched.

  Furthermore, in each of the above-described embodiments, the power supply voltage having the same potential can be selectively switched between the non-common state and the common state for the three power supply lines to which the power supply voltage is independently applied. . However, the present invention is not limited to this configuration. For example, if there are three or more power supply lines to which the power supply voltage of the same potential is independently applied, a combination of any three or more power supply lines is included. Thus, it is possible to employ a configuration that can switch between a common state and a non-common state of the power supply lines.

  In addition, in the above embodiment, a semiconductor device having a structure in which a semiconductor chip is sealed in a package having a lead as an external terminal is exemplified. However, the present invention is applicable to a semiconductor device having another structure such as a wafer state. Naturally applicable.

  The present invention can supply a power supply current exceeding the power supply amount of a single inspection power supply without changing the connection state between the inspection apparatus and the DUT, and can efficiently and reliably inspect a semiconductor device. It is useful as a method for manufacturing a semiconductor device and a semiconductor device.

1 is a schematic configuration diagram showing a semiconductor device according to a first embodiment of the present invention. The schematic diagram explaining operation | movement of the switch part of this invention The circuit diagram which shows the connection state of the semiconductor device and test | inspection apparatus in the 1st Embodiment of this invention The circuit diagram which shows the connection state of the semiconductor device and test | inspection apparatus in the 2nd Embodiment of this invention A circuit diagram showing a connection state between a conventional semiconductor device and an inspection device A circuit diagram showing a connection state between a conventional semiconductor device and an inspection device

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Package 2, 102, 112 Semiconductor chip 3 Circuit group 4 Inspection apparatus 5-9 Power supply line 10, 100, 110 DUT (semiconductor device)
DESCRIPTION OF SYMBOLS 11 Inspection control circuit 12 Switch part 20 Inspection board 31 1st logic circuit (1st semiconductor circuit unit)
32 Analog circuit (second semiconductor circuit unit)
33 First memory circuit (third semiconductor circuit unit)
34 Second logic circuit 35 Second memory circuit L1 to L5 Lead (external terminal)
SW1, SW2, SW3 Switch element PD1-PD5 Pad (internal terminal)
W1-W5 bonding wire

Claims (10)

First, second and third semiconductor circuit units operating at the same power supply voltage;
First, second and third power supply lines to which power supply voltages are applied independently from each other;
A non-common state in which each of the first, second, and third power supply lines applies a power supply voltage to each of the first, second, and third semiconductor circuit units independently of each other; A common power supply line and the second power supply line simultaneously apply a power supply voltage to the first semiconductor circuit unit, and the third power supply line applies a power supply voltage to the second and third semiconductor circuit units. A switch part for selectively switching between states,
A semiconductor device comprising:   2. The semiconductor device according to claim 1, wherein the first, second and third semiconductor circuit units, the first, second and third power supply lines, and the switch section are formed on the same semiconductor substrate. . The switch part is
A first switch element that is selectively connected between a conductive state and a cut-off state, interposed in a first connection wiring that electrically connects the first power line and the second power line;
A second switch element selectively switching between a conductive state and a cut-off state interposed in a second connection wiring that electrically connects the second power line and the third power line;
The second power supply line is interposed between the connection point between the second power supply line and the first connection wiring and the connection point between the second power supply line and the second connection wiring. A third switch element for selectively switching between the conductive state and the cutoff state;
The semiconductor device according to claim 2, further comprising:   The semiconductor device according to claim 1, wherein the switch unit is configured by an element capable of selectively maintaining the non-common state or the common state without input of a control signal.   The power supply voltage having the same potential is applied to the first, second, and third power supply lines by an independent power supply device while being used in the non-common state during actual use. Semiconductor device. A method of manufacturing a semiconductor device comprising a plurality of semiconductor circuit units to which a power supply voltage of the same potential is independently applied from power supply devices independent from each other during actual use,
The first power supply device and the second power supply device simultaneously apply a power supply voltage to the first semiconductor circuit unit, and the third power supply device supplies power to the second semiconductor circuit unit and the third semiconductor circuit unit. A first inspection step for measuring at least electrical characteristics of the first semiconductor circuit unit in a state where a voltage is applied;
The first power supply device applies a power supply voltage to the first semiconductor circuit unit, the second power supply device applies a power supply voltage to the second semiconductor circuit unit, and the third semiconductor circuit unit A second inspection step of measuring electrical characteristics of the first, second and third semiconductor circuit units in a state where a power supply voltage is applied by the third power supply device;
A method of manufacturing a semiconductor device including: In the first inspection step, due to the upper limit current supply amount of the first power supply device, measurement of an inspection item in which the power supply current supply amount during operation of the first semiconductor circuit unit is insufficient is performed,
In the second inspection step, measurement of an inspection item is performed such that the power supply current supply amount during operation of the first semiconductor circuit unit does not become insufficient due to the upper limit current supply amount of the first power supply device. The method for manufacturing a semiconductor device according to claim 6, which is carried out. The inspection performed in the first inspection step is
A step of measuring electrical characteristics in a state where the first semiconductor circuit unit is operated by a clock signal having a frequency higher than an operation clock frequency during actual use;
Measuring electrical characteristics in a state where the second and third semiconductor circuit units are operated by a clock signal having a frequency lower than that of the first semiconductor circuit unit;
The manufacturing method of the semiconductor device of Claim 6 or 7 containing these.   The semiconductor device according to claim 6, wherein the first semiconductor circuit is a logic circuit, the second semiconductor circuit is an analog circuit, and the third semiconductor circuit is a memory circuit. Manufacturing method.   The method of manufacturing a semiconductor device according to claim 6, wherein the first and second inspection steps are simultaneously performed on each of the plurality of semiconductor devices.

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