JP2000284024A - Semiconductor device and integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To add a boundary scan function to an integrated circuit, to suppress a boundary scan circuit becoming useless after its shipment to a minimum, to reduce the cost of the boundary scan circuit itself and to perform an inspection quickly. SOLUTION: A test control block circuit is removed from an integrated circuit having an analog boundary scan function, Instead, terminals for test are installed. A control signal for test is input directly. As the terminals for test, a TCK terminal 8, a TDI terminal 13, a TDO terminal 16, a Shift-DR terminal 9, a Capture-DR terminal 10, an Update-DR terminal 11, an Enable terminal 12, a Mode 1 terminal 47a, a Mode 2 terminal 47b, an analog test bus terminal 35a, and an analog test bus terminal 35b are provided. In addition, the respective terminals for test are installed at the interposer of a semiconductor device, respective control signals are input from an inspection apparatus, and a boundary scan test is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having an integrated circuit having a boundary scan cell.

[0002]

2. Description of the Related Art Conventionally, semiconductor devices such as LSIs (ICs)
The circuit test (operation test) of the device) and the circuit test of the substrate on which these semiconductor devices are mounted need to be performed with each element mounted. On the other hand, with the recent increase in the density and mounting density of substrates and the emergence of devices having connection parts such as BGA (ball grid array) on the lower surface,
Visual testing of the mounted state has become difficult. On the other hand, as a test that does not rely on vision, there is an in-circuit test in which test pads are arranged on a component mounting board. It is becoming difficult to dispose a test pad (test terminal) for contacting a probe pin of an inspection device on a wiring pattern.

In order to cope with such circumstances, a semiconductor device in which a test pad is formed on the semiconductor device itself (for example, on an interposer) has been proposed (for example, see Japanese Patent Application Laid-Open No. 10-199941). That is, in this semiconductor device, a package enclosing an integrated circuit is provided on an interposer (package carrier), leads are radially provided from the package onto the interposer, and test terminals are provided on each lead. However, in such a semiconductor device, since many lead wires and test terminals are provided on the interposer, the semiconductor device itself becomes large.

On the other hand, a digital circuit test that does not require a large number of test pads on a component mounting board is an IEEE test.
There is a digital boundary scan test according to the standard 1149.1. In this, a means for generating a signal corresponding to an external test signal by a test pad is provided inside an integrated circuit as a digital boundary scan cell.In addition to a digital boundary scan cell for performing a test operation, an instruction register for receiving an instruction, a digital Built-in TAP (Test Access Port) circuit for controlling boundary scan cells, and TDI (Test Data In), TDO (Test Data Out), TMS
(Test mode select), TCK (test clock)
By sending a few types of signals, such as those described above, many tests are performed on the connection portions of the semiconductor device.

FIG. 4 is a block diagram showing an example of a package having a digital boundary scan test function.
FIG. 5 is a block diagram showing a configuration example of a digital boundary scan test circuit mounted on the package shown in FIG. In FIG. 4, a core logic 1 is a circuit having a main function of the integrated circuit. In a package having a circuit without a digital boundary scan function, the core logic 1 and signal pins 17a and 17 shown in FIG.
b is directly connected, and the package 18 has the core logic 1 and the signal pins 17a and 17b, and does not have the digital boundary scan cells 2a and 2b and the instruction register 26. The digital boundary scan cells 2a and 2b correspond to test pads on a mounting board in an in-circuit test.

In FIG. 4, for a package 18,
The input cell 2a is arranged between the input pin 17a and the core logic 1. The input pin 17a is connected to the input terminal 6
Is connected in a signal manner. The output cell 2b is arranged between the core logic 1 and the output pin 17b.
The output pin 17b is connected to the output terminal 7 in a signal manner. FIG. 5 shows that the input cell 2a and the output cell 2b each have 1
One time at a time. The TDI and TDO of the adjacent digital boundary scan cells are connected, and the digital boundary scan cells from the TDI terminal 13 to the TDO terminal 16 are connected in a daisy chain.

[0007] A series of digital boundary scan cells connected from the TDI terminal 13 to the TDO terminal 16 are collectively called a data register. The data input through the TDI terminal 13 passes through a data register, an instruction register 26, or a bypass register 25, and is output to the TDO terminal 16 through a test signal multiplexer. Instruction register 26
Is a register for storing an external instruction, an EXTEST instruction for executing an open / short test, a BYPASS instruction for not performing inspection on this semiconductor device,
An INTEST instruction for checking the core logic 1 is stored. The stored instruction is reflected on the circuit through the instruction decoder 29.

A test signal pin 17c is added for a digital boundary scan function.
TCK terminal 8, TDI terminal 13, TDO terminal 1
6. The TMS terminal 30 is connected in a signal manner. In addition,
TRST is a reset signal of the digital boundary scan circuit, but is not essential and is not shown in FIG. 5 because it is optional. TDI is a terminal for inputting an instruction set for a test pad or a circuit to the circuit. TDO is a terminal for outputting a test result and the like. T
CK is a clock signal, and TMS is a signal for changing the state of the digital boundary scan circuit.

The digital boundary scan circuit has a TA
The state changes according to the value of the TMS signal at the rise of the clock signal TCK input to the P controller 27, and has 16 types of states. FIG. 6 is an explanatory diagram showing the state transition. A signal corresponding to each state of the digital boundary scan circuit is supplied to the state decoder 28.
Is sent to the data register or the instruction register 26 to perform a digital boundary scan test. The operation of the digital boundary scan cell will be described using the output cell 2b as an example. The basic operation of the input cell 2a is the same.

The operation of the digital boundary scan cell differs depending on the stays determined by the above-described 16 states and the signals from the decoder 28 and the instruction decoder 29. Test Logi in FIG.
c In the reset state, the digital boundary scan cell does not operate as a test circuit, and the core logic 1
Is output to the output terminal 7 through the multiplexer 5. Also, in the Run Test / Idle state, the digital boundary scan cell is in a standby state.

In the Capture-DR state, the enable signal from the instruction decoder 29 and the Capture-DR from the state decoder 28 are output.
A signal is sent. A signal from the core logic 1 is stored in the boundary scan shift register 3. Also, S
In the shift-DR state, an instruction decoder 29 sends an enable signal and a state decoder 28 sends a Shift-DR signal. The data stored in the boundary scan shift register 3 is TDO
And the signal from the TDI is newly stored in the boundary scan shift register 3. Also, Updat
In the e-DR state, the instruction decoder 2
9 and the enable signal from the state decoder 28
A pdate-DR signal is sent. Data stored in the boundary scan shift register 3 is sent to the parallel latch 4. The data stored in the parallel latch 4 is sent to the output terminal 7 through the multiplexer 5.

The Capture-IR shown in FIG.
In the state, Shift-IR state, and Update-IR state, an instruction is sent to the data register in the above-described Capture-DR state, Shift-DR state, and Update-DR state, and the data register operates. A similar operation is performed on the instruction register. The board test can be performed by a combination of the operations of the digital boundary scan cell as described above. The detailed operation at the time of the board test is described in detail in IEEE Standard 1149.1.

An analog circuit test method that does not require many test pads on a mounting board is an analog boundary scan test according to IEEE standard 1149.4. FIG. 7 is a block diagram illustrating an example of a package having an analog boundary scan test function. I
In the EEE standard 1149.4, the digital boundary scan cell is called a DBM (digital boundary module), and the analog boundary scan cell is called an ABM.
(Analog boundary module). In FIG. 7, the ABM 32 is shown only on the output cell side,
A similar arrangement can be provided on the input cell side.

FIG. 10 is a block diagram collectively showing the functional elements necessary for the analog boundary scan test. The ABM 32 is an output cell connected to an output pin in FIG. TBIC34 to ABM32
The analog control buses 35 a and 35 b are connected to each other, and various control signals (such as Shift-DR) are sent from the test control block 33 to the capture and update register 44. The capture and update register 44 is operated by the control signal sent from the test control block 33 to the capture and update register 44, and the data serially input from the TDI is shifted or output. The data output from the capture and update register 44 and the control signal (Mode 1 or the like) from the test control block 33 are input to the ABM control decode logic 45.
The operation of the BM 32 is determined.

FIGS. 8 and 9 are block diagrams showing the structure of the ABM 32. FIG. First, in FIG. 8, the switch (S
D) 36 electrically disconnects the analog core. The 1-bit digitizer 37 converts an analog signal into a digital signal using a threshold voltage (VTH) 38, and outputs the digital signal to a digital signal output terminal (DPin) 39, which becomes an input in FIG. This digital signal is input to a data register and used for an IEEE 1149.1 type digital boundary scan test. The threshold voltage (VTH)
38 does not require a physical voltage terminal. Further, the high level voltage (VH) 40a is connected to the switch (SH) 4
1a, a low level voltage (VL) 40b is connected to a switch (S
L) 41b is connected to a reference voltage (VG) 40c by a switch (S).
G) Connected to the analog pin by 41c.

The high-level voltage (VH) 40a and the low-level voltage (VL) 40b are used to generate an analog signal from a digital signal for an IEEE 1149.1 type digital boundary scan test. Switch (S
The H) 41a and the switch (SL) 41b need not be physically present as long as they can appropriately supply the high-level voltage (VH) 40a and the low-level voltage (VL) 40b. The reference voltage (VG) 40c is a reference voltage for analog measurement. The reference voltage (VG) 40c is a constant voltage source that does not change in voltage within a specified range and can change current, and is not stable in time. must not. The fact that this integrated circuit is connected to the system ground indicates that the reference voltage (V
G) Desirable for 40c. If this condition is not satisfied, the high-level voltage (VH) 40a and the low-level voltage (VL) 40b may replace the reference voltage (VG) 40c.

The analog test signal switch SB (SB
1) 42a connects an analog test bus (AB1) 35a to an analog pin, and an analog test signal switch S
B (SB2) 42b is an analog test bus (AB2)
35b is connected to an analog pin. The test control block 33 is a circuit having a function of integrating an instruction register, a TAP controller, and an instruction decoder as referred to in the digital boundary scan test described above, and corresponds to the lower half of FIG. The function of the test control block 33 is, in addition to the function of integrating the instruction register, the TAP circuit, and the instruction decoder, referred to in the above-described digital boundary scan test, as well as the instruction state signals Mode1 and Mode.
It has a function of sending de2 to the TBIC 34 and ABM described later.

Next, in FIG. 9, the capture and update register 44 stores the IEEE standard 1149.1.
Are combined with the functions of the boundary scan shift register 3 and the parallel latch 4 of the digital boundary scan cells 2a and 2b, and the digital boundary scan cells 2a and 2b are connected to the core logic 1 and the input terminal 6 or the output terminal 7. Can be considered not. The input to the capture and update register 44 is a digital signal output terminal (DPi
n) Signals other than 39 are optional and are indicated by broken lines. Normally, a control signal sent from the TDI side to the TDO side via each data register (digital boundary scan cell) is an input to the capture and update register 44.

D for one ABM 32 by input to four capture and update registers 44
C, B1, B2, and test control block 33
The signals of Mode 1 and Mode 2 are M1 signal and M
Two signals are input to the ABM control decode logic, and these control signals D, C, B1, B2, M1,.
By the combination of M2, the above-mentioned switch (SD) 3
6, switch (SH) 41a, switch (SL) 41
b, switch (SG) 41c, switch (SB1) 42
a, Open / close of each switch of the switch (SB2) 42b is determined.

[0020] Further, a TBIC (Test Bus In) is unique to the analog boundary scan test.
(Interface Circuit) 34. The TBIC 34 is electrically connected to the ABM 32 via analog test buses (AB1) 35a and (AB2) 35b, respectively. The function of the TBIC 34 is to connect and disconnect the analog test terminals (AT1) and (AT2) to and from the analog test buses (AB1) 35a and (AB2) 35b. Signal from block 33 and TDI
Is switched by the test data from.

By sending a small number of signals such as TDI, TDO, TMS, TCK, and two analog test terminals AT1 and AT2 from the test signal pin 17c to the integrated circuit, many connection portions of the semiconductor device are provided. Test. An analog board test can be performed by a combination of the operations of the ABM, the TBIC, and the test control block as described above. The detailed operation in the board test is described in IEEE Standard 1149.4.

[0022]

By the way, the semiconductor device having an external test terminal disclosed in Japanese Patent Laid-Open Publication No. Hei 10-199941 has the following problems. First, since external test terminals are provided in the same number as the number of connection pins, and the external test terminals are required to have a certain interval, the lead wires are radiated from the integrated circuit toward the periphery of the semiconductor device. And the semiconductor device itself becomes large. This meets the demand for higher density of the board itself, which does not have test pads on the mounting board, but contradicts the demand for miniaturization of the parts themselves. Also, the larger the components, the more difficult the mounting becomes, and the lower the mounting reliability becomes.

Second, when the test pads are provided as test terminals on the semiconductor device side, the intervals between the test terminals are smaller than when similar test pads are arranged on the substrate. Precision is required. This leads to an increase in the cost of the inspection device. In order to solve this, a method of incorporating the digital boundary scan circuit or the analog boundary scan circuit as described above in an integrated circuit is considered. That is, in this method, T
A circuit test can be performed with 6 to 7 test terminals such as DI, TDO, TMS, and TCK.

However, since the above-described boundary scan circuit is used only for a test at the time of manufacture and is not used after shipment, it is necessary to put such a boundary scan circuit on the integrated circuit in the market. The cost increase is a problem. In addition, in the inspection using the above-described boundary scan circuit, a signal for inspection is generated by decoding an external input signal, and the inspection is performed while performing the state transition shown in FIG. There is a problem that a complicated inspection cannot be performed.

Accordingly, an object of the present invention is to add a boundary scan function to an integrated circuit while minimizing a boundary scan circuit that is wasted after shipment, thereby reducing the cost of the boundary scan circuit itself and achieving a rapid operation. An object of the present invention is to provide a semiconductor device and an integrated circuit that enable inspection. Further, an object of the present invention is to reduce the number of test terminals, reduce the size of the semiconductor device itself, and reduce the cost, even though the semiconductor device itself has test terminals and has a structure that simplifies inspection. Another object of the present invention is to provide a semiconductor device and an integrated circuit in which an increase in cost of the integrated circuit is minimized.

[0026]

According to the present invention, in order to achieve the above object, in a semiconductor device having an integrated circuit having a boundary scan cell, the integrated circuit includes a test control block for controlling the boundary scan cell. The boundary scan cell is directly controlled by a signal input from outside without a circuit. Further, the present invention provides an integrated circuit mounted on a semiconductor device and having a boundary scan cell, which does not have a test control block circuit for controlling the boundary scan cell, and the boundary scan cell is controlled by an externally input signal. It is characterized by being directly controlled.

In the semiconductor device and the integrated circuit of the present invention, the integrated circuit does not have a test control block circuit for controlling boundary scan cells, but a circuit corresponding to a test control block circuit provided in an external inspection device. , The boundary scan cell is directly controlled by a signal input from the outside. For example, in a digital boundary scan cell for a digital circuit, TDI and TD required for a digital boundary scan test are used.
O, TCK, Capture-DR, Shift-D
A test is performed by externally inputting signals such as R, Update-DR, and Enable. In the analog boundary scan cell for an analog circuit, TDI, TDO, TCK,
Capture-DR, Shift-DR, Updat
A test is performed by inputting signals such as e-DR, Enable, Mode 1 and Mode 2 from the outside.

Means for externally inputting such a signal include a signal input by bringing a terminal of an inspection device into contact with a test pad formed on an interposer of the semiconductor device, and a wiring on which the semiconductor device is mounted. There is a method of inputting by contacting a terminal of an inspection device with a test pad provided on a substrate, and a method of inputting via a connection portion (such as a connector) provided on a wiring substrate. Therefore, in the semiconductor device and the integrated circuit of the present invention, while adding the boundary scan function to the integrated circuit, the boundary scan circuit wasted after shipment is minimized by eliminating the test control block circuit, The cost of the device itself can be reduced.

Further, since control is directly performed by an external signal without performing processing such as decoding by the test control block circuit in the integrated circuit, quick inspection can be performed. Furthermore, since the test is performed by the boundary scan function, the number of external signals may be small, and a test pad (test terminal) for inputting the signals is required.
Is provided on an interposer of a semiconductor device or a mounting wiring board, the arrangement space is not so large. Therefore, the size and cost of the semiconductor device can be reduced.

[0030]

Embodiments of a semiconductor device and an integrated circuit according to the present invention will be described below in detail with reference to the drawings. FIG. 1 is a circuit diagram showing functional elements required for an analog boundary scan test of an integrated circuit according to a first embodiment of the present invention. Note that the same components as those in FIG. 10 are described with the same reference numerals. As shown, in the integrated circuit of this example, the test control block 33 is removed from the configuration of the conventional example shown in FIG. 10, and in the conventional example shown in FIG. Capture-DR, Shi
ft-DR, Update-DR, Mode1, Mod
Each signal of e2 is input to input terminals 9, 10, 11, 12, 47.
a and 47b. Also,
In this example, as in the conventional example shown in FIG.
Input / output terminals 13, 16, and 8 for I, TDO, and TCK are provided.

In FIG. 1, ABM 32 is an output pin 1
This is the output cell connected to 7d. And TBI
Analog test bus 35a from C34 to ABM32, 3
5b are connected, and input terminals 8 to 13, 47
Various control signals (such as Shift-DR) are sent to the capture and update register 44 from a and 47b. The capture and update register 44 is controlled by a control signal sent from the input terminals 8 to 13, 47 a and 47 b to the capture and update register 44.
Operates, and the data serially input from the TDI is shifted or output. Data output from the capture and update register 44 and input terminals 8 to
Control signals from 13, 47a, 47b (Mode 1 etc.)
Is input to the ABM control decode logic 45, and the operation of the ABM 32 is determined by the input signal.

Next, the configuration of the ABM 32 will be described with reference to FIGS. First, in FIG. 8, a switch (SD) 36 electrically disconnects an analog core. The 1-bit digitizer 37 converts the analog signal into a digital signal by a threshold voltage (VTH) 38,
The signal is output to the digital signal output terminal (DPin) 39 and becomes the input in FIG. This digital signal is input to a data register, and is used for an IEEE 1149.1 type digital boundary scan test. Note that the threshold voltage (VT
H) 38 does not require the physical presence of a voltage terminal.
Further, a high level voltage (VH) 40a is connected to the switch (S
H) 41a, the low level voltage (VL) 40b is connected to the switch (SL) 41b, and the reference voltage (VG) 40c is connected to the analog pin by the switch (SG) 41c.

The high-level voltage (VH) 40a and the low-level voltage (VL) 40b are used to create an analog signal from a digital signal for an IEEE 1149.1 type digital boundary scan test. Switch (S
The H) 41a and the switch (SL) 41b need not be physically present as long as they can appropriately supply the high-level voltage (VH) 40a and the low-level voltage (VL) 40b. The reference voltage (VG) 40c is a reference voltage for analog measurement. The reference voltage (VG) 40c is a constant voltage source that does not change in voltage within a specified range and can change current, and is not stable in time. must not. The fact that this integrated circuit is connected to the system ground indicates that the reference voltage (V
G) Desirable for 40c. If this condition is not satisfied, the high-level voltage (VH) 40a and the low-level voltage (VL) 40b may replace the reference voltage (VG) 40c.

The analog test signal switch SB (SB
1) 42a connects an analog test bus (AB1) 35a to an analog pin, and an analog test signal switch S
B (SB2) 42b is an analog test bus (AB2)
35b is connected to an analog pin. Next, in FIG. 9, the capture and update register 4
Reference numeral 4 denotes a combination of the functions of the boundary scan shift register 3 and the parallel latch 4 of the digital boundary scan cells 2a and 2b in the IEEE standard 1149.1.
It can be considered that 2b is not connected to the core logic 1 and the input terminal 6 or the output terminal 7.

The input to the capture and update register 44 is a digital signal output terminal (DPin)
Since the signals other than the signal 39 are optional, they are indicated by broken lines. Normally, a control signal sent from the TDI side to the TDO side via each data register (digital boundary scan cell) is an input to the capture and update register 44. D, C, B1, B2, and input terminals 47a by input to four capture and update registers 44 for one ABM 32;
The Mode 1 and Mode 2 signals from 47b are input to the ABM control decode logic 45 as M1 and M2 signals, and these control signals D, C, B1, and B
The switch (SD) 36, the switch (SH) 41a, and the switch (S
L) 41b, switch (SG) 41c, switch (SB)
1) Open / close of each switch of the switch 42a and the switch (SB2) 42b is determined.

In this embodiment, the TBIC shown in FIG.
The function of the analog test terminal 34 (AT1) in the TBIC 34 is the same as that shown in FIG.
And (AT2) and the analog test bus (AB1) 35
The connection to and disconnection from (a) and (AB2) 35b is switched by input signals from the input terminals 8 to 13, 47a, and 47b.

As described above, in the integrated circuit of this embodiment, FIG.
10 has a configuration without the test control block 33 as compared with the conventional circuit shown in FIG.
The terminal (signal input terminal for state transition) corresponding to the TMS terminal 30 of the TAP controller 27 shown in FIG. Instead, Shift-DR terminal 9, Capture-DR terminal 10, Update-D
R terminal 11, Enable terminal 12, Mode 1 terminal 4
By newly adding the Mode 7a and the Mode 2 terminal 47b, the boundary scan cell is directly controlled by these signals, and the analog boundary scan test function can be realized.

As described above, the test control block 3
With the configuration excluding 3, the configuration of the integrated circuit can be simplified and reduced in size. Further, the analog boundary scan test can be performed without performing the control signal decoding and the state transition operation as in the related art, and the inspection can be speeded up. Further, since it can be realized by adding a small number of input terminals, a large number of test pads are not required, and it is possible to respond to a demand such as mounting density. Further, since it is not necessary to add the test control block 33 to each integrated circuit, cost reduction can be realized.

FIG. 2 is a perspective view showing an example of a semiconductor device on which an integrated circuit having the test input / output terminals 8 to 13, 16, 47a, and 47b is mounted. An example is shown. In the semiconductor device of this example, the integrated circuit 19 is provided on the first main surface of the interposer 21 which is an insulating substrate in a state where the integrated circuit 19 is sealed with a sealing body 20. The material of the sealing body 20 is the integrated circuit 19
For example, an anisotropic conductive resin may be used. A wiring pattern such as copper is formed on a first main surface of the interposer 21, and a test terminal 23 is provided at an end of a specific lead wire 22. The test terminals 23 are the TCK terminal 8 and the TDI terminal 1 shown in FIG.
3, TDO terminal 16, Shift-DR terminal 9, Cap
cure-DR terminal 10, Update-DR terminal 1
1, Enable terminal 12, Mode 1 terminal 47a, M
mode2 terminal 47b, analog test terminals 46a, 4
6b are electrically connected to a total of 11 terminals.

A large number of connection terminals 24 such as solder balls are formed on the second main surface of the interposer 21 and serve as connection portions to a mounting board (not shown). In the semiconductor device having such a configuration, a probe terminal of an inspection device (not shown) is brought into contact with each test terminal 23, and TCK,
TDI, TDO, Shift-DR, Capture-
DR, Update-DR, Enable, Mode
1, a Mode 2 and an analog test signal are supplied to perform a boundary scan test. The inspection apparatus includes the test control block 33 described in the conventional example.
However, in this example, an instruction to be issued to the boundary scan cell such as the above-described Shift-DR can be issued directly without state transition.

According to the configuration described above, the boundary scan test of the integrated circuit can be realized by a small number (11 in this example) of test terminals provided on the interposer 21, thereby suppressing an increase in the size of the semiconductor device. In addition, it is possible to perform a test of the integrated circuit while contributing to miniaturization of a semiconductor device, high-density mounting on a mounting substrate, and the like. Further, in the conventional boundary scan test, an instruction issued to a boundary scan cell such as Shift-DR is issued in response to a state transition by a TMS signal or the like as described above. Although a useless state (for example, Exit1-DR shown in FIG. 6) must be passed and extra time is required, in this example, since each control signal can be issued directly regardless of the state transition, the test time Can be reduced.

FIG. 3 is a circuit diagram showing functional elements required for an analog boundary scan test of an integrated circuit according to the second embodiment of the present invention. Note that the same components as those in FIG. 10 are described with the same reference numerals. As shown in the figure, the integrated circuit of this example is obtained by removing the test control block 33 and the TBIC 34 from the configuration of the conventional example shown in FIG. 10, and in the conventional example shown in FIG. The Capture
-DR, Shift-DR, Update-DR, Mo
The signals of de1 and Mode2 are input to input terminals 9, 10, 1
The analog test buses 35a and 35b, which have been inputted from 1, 12, 47a and 47b and selectively inputted AB1 and AB2 by the TBIC 34 in the conventional example, are provided as direct input terminals. Also in this example, similarly to the conventional example shown in FIG.
CK input / output terminals 13, 16 and 8 are provided.

In FIG. 3, ABM 32 is an output pin 1
This is the output cell connected to 7d. Then, various control signals (Shi) are input from the input terminals 8 to 13, 47a and 47b.
ft-DR, etc.) are sent to the capture and update register 44, and analog signals for testing are sent to the capture and update register 44 from the input terminals 35a and 35b. These input terminals 8 to 13,
The capture and update register 44 is operated by the control signals sent from the 47a and 47b to the capture and update register 44, and the data serially input from the TDI is shifted or output. The data output from the capture and update register 44 and the control signals (such as Mode 1) from the input terminals 8 to 13, 47a and 47b are input to the ABM control decode logic 45, and the operation of the ABM 32 is determined by the input signals. Is done.

On the other hand, a semiconductor device having an integrated circuit having such a structure is mounted on the first main surface of the interposer 21 in the same manner as that shown in FIG.
TDI terminal 13, TDO terminal 16, Shift-DR terminal 9, Capture-DR terminal 10, Update-
A test terminal 23 electrically connected to the DR terminal 11, the Enable terminal 12, the Mode 1 terminal 47a, the Mode 2 terminal 47b, and the analog test bus terminals 35a and 35b is provided, and each test terminal 23 is illustrated. The probe terminal of the inspection device that does not
TDI, TDO, Shift-DR, Capture-
DR, Update-DR, Enable, Mode
1, a Mode 2 and an analog test signal are supplied to perform a boundary scan test. The inspection apparatus includes the test control block 33 described in the conventional example.
And a function corresponding to the TBIC 34 are provided.
In this example, an instruction to be issued to the boundary scan cell such as the above-mentioned Shift-DR can be issued directly without depending on the state transition.

As described above, in the integrated circuit of this embodiment,
Compared with the conventional circuit shown in FIG. 10, the configuration is such that the test control block 33 and the TBIC 34 are not provided.
No terminal corresponding to the TMS terminal 30 (signal input terminal for state transition). Instead,
Shift-DR terminal 9, Capture-DR terminal 1
0, Update-DR terminal 11, Enable terminal 1
2. A new Mode 1 terminal 47a and a Mode 2 terminal 47b are newly added, and analog test bus terminals 35a and 35b are provided instead of the AT terminals 46a and 46b. Boundary scan test function can be realized.

As described above, the test control block 3
3 and the configuration excluding the TBIC 34, the configuration of the integrated circuit can be simplified and reduced in size. Further, the analog boundary scan test can be performed without performing the control signal decoding and the state transition operation as in the related art, and the inspection can be speeded up. Further, since it can be realized by adding a small number of input terminals, a large number of test pads are not required, and it is possible to respond to a demand such as mounting density. Furthermore, a test control block 33 is provided for each integrated circuit.
In addition, since there is no need to add the TBIC 34, the cost can be reduced.

Since the boundary scan test of the integrated circuit can be realized by a small number (11 in this example) of test terminals provided on the interposer 21, the test of the integrated circuit can be performed while suppressing the increase in the size of the semiconductor device. This can contribute to downsizing of the semiconductor device, high-density mounting on a mounting substrate, and the like. Further, in the conventional boundary scan test, an instruction issued to a boundary scan cell such as Shift-DR is issued in response to a state transition by a TMS signal or the like as described above. Useless state (for example, Exit shown in FIG. 6)
1-DR), which takes extra time. However, in this example, since each control signal can be issued directly irrespective of the state transition, the test time can be reduced.

In the above example, an example in which the analog boundary scan test function is implemented has been described. Similarly, the digital boundary scan test function can also be implemented in the above-described instruction register 26, TAP.
Except for the controller 27 and the instruction decoder 29, the Shift-DR terminal 9, the Capture-DR
Terminal 10, Update-DR terminal 11, Enable
This can be realized by adding the terminal 12. The present invention is shown in FIG.
The present invention can be similarly applied to an integrated circuit in which the analog boundary scan test function and the digital boundary scan test function are mixed as shown in FIG. In the above example, each control signal is input through the test terminal 23 provided on the interposer 21 of the semiconductor device. However, the present invention is not limited to this. For example, the control signal may be input to a wiring board on which the semiconductor device is mounted. The input may be made by bringing the terminal of the inspection device into contact with the provided test pad. In addition, connection parts (such as connectors) provided on the wiring board
May be input via the.

[0049]

As described above, according to the present invention, in a semiconductor device mounted with an integrated circuit having a boundary scan cell, the integrated circuit does not have a test control block circuit for controlling the boundary scan cell. The boundary scan cell is directly controlled by a signal input from the outside. Therefore, in the semiconductor device of the present invention, while adding the boundary scan function to the integrated circuit, the wasteful boundary scan circuit after shipment is minimized by removing the test control block circuit, and the cost of the boundary scan circuit itself is reduced. Down can be planned.

In addition, since the control is directly performed by an external signal without performing processing such as decoding by the test control block circuit in the integrated circuit, quick inspection can be performed. Furthermore, since the test is performed by the boundary scan function, the number of external signals may be small, and a test pad (test terminal) for inputting the signals is required.
Is provided on an interposer of a semiconductor device or a mounting wiring board, the arrangement space is not so large. Therefore, the size and cost of the semiconductor device can be reduced.

In the present invention, the semiconductor device is mounted on a semiconductor device.
In an integrated circuit having a boundary scan cell, a test control block circuit for controlling the boundary scan cell is not provided, and the boundary scan cell is directly controlled by an externally input signal. Therefore, in the integrated circuit of the present invention, while adding the boundary scan function to the integrated circuit, the wasteful boundary scan circuit after shipment is minimized by removing the test control block circuit, and the cost of the boundary scan circuit itself is reduced. Down can be planned.

Further, since the control is directly performed by an external signal without performing processing such as decoding by the test control block circuit in the integrated circuit, quick inspection can be performed. Furthermore, since the test is performed by the boundary scan function, the number of external signals may be small, and a test pad (test terminal) for inputting the signals is required.
Is provided on an interposer of a semiconductor device or a mounting wiring board, the arrangement space is not so large. Therefore, the size and cost of the semiconductor device can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of an analog boundary scan circuit section of an integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a perspective view showing a configuration example of a semiconductor device on which the integrated circuit shown in FIG. 1 is mounted.

FIG. 3 is a block diagram illustrating a schematic configuration of an analog boundary scan circuit section of an integrated circuit according to a second embodiment of the present invention.

FIG. 4 is a block diagram illustrating a configuration of a semiconductor device equipped with a conventional digital boundary scan circuit.

FIG. 5 is a block diagram showing a detailed configuration of the digital boundary scan circuit shown in FIG. 4;

FIG. 6 is a block diagram showing a state transition of the digital boundary scan circuit shown in FIG. 4;

FIG. 7 is a block diagram showing a configuration of a conventional semiconductor device equipped with a digital boundary scan circuit and an analog boundary scan circuit.

8 is a block diagram showing a detailed configuration of the analog boundary scan circuit shown in FIG.

9 is a block diagram showing a detailed configuration of the analog boundary scan circuit shown in FIG.

FIG. 10 is a block diagram illustrating a schematic configuration of an analog boundary scan circuit section illustrated in FIG. 7;

[Explanation of symbols]

1 ... core logic, 8 ... TCK terminal, 9 ... Shi
ft-DR terminal, 10 ... Capture-DR terminal,
11: Update-DR terminal, 12: Enable
e terminal, 13: TDI terminal, 16: TDO terminal, 1
9 ... integrated circuit, 20 ... sealed body, 21 ... interposer, 22 ... lead wire, 23 ... test terminal, 32 ...
... ABM, 35a, 35b ... Analog test bus terminals, 46a, 46b ... Analog test terminals, 47a ...
... Mode 1 terminal, 47b... Mode 2 terminal.

Claims (22)

[Claims] 1. A semiconductor device equipped with an integrated circuit having a boundary scan cell, wherein the integrated circuit does not have a test control block circuit for controlling the boundary scan cell, and the integrated circuit does not have a test control block circuit. A semiconductor device wherein boundary scan cells are directly controlled. 2. The method according to claim 1, wherein the boundary scan cell is a digital boundary scan cell for a digital circuit.
O, TCK, Capture-DR, Shift-D
2. The semiconductor device according to claim 1, wherein the semiconductor device includes signals of R, Update-DR, and Enable. 3. The boundary scan cell according to claim 1, wherein said boundary scan cell is an analog boundary scan cell for an analog circuit.
O, TCK, Capture-DR, Shift-D
R, Update-DR, Enable, Mode1,
2. The semiconductor device according to claim 1, comprising each signal of Mode2. 4. The integrated circuit according to claim 3, further comprising a test bus interface circuit dedicated to analog test for selectively supplying an analog test signal from an external input to an analog bus of the analog boundary scan cell. Semiconductor device. 5. The integrated circuit does not have a test bus interface circuit dedicated to analog test for selectively supplying an analog test signal by an external input to an analog bus of the analog boundary scan cell. 4. The semiconductor device according to claim 3, wherein the signal is selectively inputted from the analog signal line and directly inputted to the analog boundary scan cell. 6. The boundary scan cell according to claim 1, wherein said boundary scan cell is a digital boundary scan cell for a digital circuit and an analog boundary scan cell for an analog circuit.
O, TCK, Capture-DR, Shift-D
R, Update-DR, Enable, Mode1,
2. The semiconductor device according to claim 1, comprising each signal of Mode2. 7. The analog circuit according to claim 6, wherein the integrated circuit has a test bus interface circuit dedicated to analog test for selectively supplying an analog test signal by an external input to an analog bus of the analog boundary scan cell. Semiconductor device. 8. The integrated circuit does not have a test bus interface circuit dedicated to analog test for selectively supplying an analog test signal by an external input to the analog bus of the analog boundary scan cell, and the analog test signal is supplied to an external device. 7. The semiconductor device according to claim 6, wherein the signal is selectively input to the analog boundary scan cell and directly input to the analog boundary scan cell. 9. An interposer on which the integrated circuit is mounted, and a test pad formed on the interposer, wherein the signal input from the outside is supplied to a test pad formed on the interposer by a test pad of an inspection apparatus. The semiconductor device according to claim 1, wherein an input is made to the boundary scan cell from the inspection device by contacting a terminal. 10. A wiring board on which the semiconductor device is mounted has a test pad connected to the integrated circuit via a wiring pattern, and the signal inputted from the outside is a test pad formed on the wiring board. 2. The semiconductor device according to claim 1, wherein an input is made from said inspection device to said boundary scan cell by bringing a terminal of the inspection device into contact with a pad. 11. A wiring board on which the semiconductor device is mounted has a connection portion connected to the integrated circuit via a wiring pattern and connected to an inspection device, and the signal input from the outside is: 2. The semiconductor device according to claim 1, wherein the signal is input from the inspection device to the boundary scan cell through a connection portion provided on the wiring board. 3. 12. An integrated circuit mounted on a semiconductor device and having a boundary scan cell, wherein the integrated circuit does not include a test control block circuit for controlling the boundary scan cell, and the boundary scan cell is not controlled by an externally input signal. An integrated circuit characterized by being directly controlled. 13. The boundary scan cell for a digital circuit, wherein the boundary scan cell is a digital boundary scan cell for a digital circuit.
The signals input from the outside are at least TDI, TDI
DO, TCK, Capture-DR, Shift-D
13. The integrated circuit according to claim 12, comprising R, Update-DR, and Enable signals. 14. The semiconductor device according to claim 1, wherein the boundary scan cell is an analog boundary scan cell for an analog circuit.
The signals input from the outside are at least TDI, TDI
DO, TCK, Capture-DR, Shift-D
R, Update-DR, Enable, Mode1,
13. A mode 2 signal is included.
An integrated circuit as described. 15. The integrated circuit according to claim 14, further comprising a test bus interface circuit dedicated to analog test for selectively supplying an analog test signal from an external input to the analog bus of the analog boundary scan cell. 16. A test bus interface circuit dedicated to analog test for selectively supplying an analog test signal from an external input to the analog bus of the analog boundary scan cell, and the analog test signal is selectively input from the outside. 15. The integrated circuit according to claim 14, wherein the signal is directly input to the analog boundary scan cell. 17. The method according to claim 17, wherein the boundary scan cell is a digital boundary scan cell for a digital circuit and an analog boundary scan cell for an analog circuit.
The signals input from the outside are at least TDI, TDI
DO, TCK, Capture-DR, Shift-D
R, Update-DR, Enable, Mode1,
13. A mode 2 signal is included.
An integrated circuit as described. 18. The integrated circuit according to claim 17, further comprising a test bus interface circuit dedicated to an analog test for selectively supplying an analog test signal by an external input to the analog bus of the analog boundary scan cell. 19. A test bus interface circuit dedicated to analog test for selectively supplying an analog test signal from an external input to the analog bus of the analog boundary scan cell, and the analog test signal is selectively input from the outside. 18. The integrated circuit according to claim 17, wherein the signal is directly input to the analog boundary scan cell. 20. The semiconductor device has an interposer on which the present integrated circuit is mounted, and a test pad formed on the interposer, wherein the signal input from the outside is a test pad formed on the interposer. 13. The integrated circuit according to claim 12, wherein the boundary scan cell is input from the inspection device by bringing a terminal of the inspection device into contact with a pad. 21. A wiring board on which the semiconductor device is mounted has a test pad connected to the present integrated circuit via a wiring pattern, and the signal input from the outside receives a test signal formed on the wiring board. 13. An input to the boundary scan cell from the inspection device by bringing a terminal of the inspection device into contact with a pad.
An integrated circuit as described. 22. A wiring board on which the semiconductor device is mounted is connected to the present integrated circuit via a wiring pattern and has a connection portion connected to an inspection device, and the signal input from the outside is: 13. The integrated circuit according to claim 12, wherein the signal is input from the inspection apparatus to the boundary scan cell through a connection portion provided on the wiring board.