JP2000243914A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a small semiconductor device at low cost for reducing the number of outer test terminals, and limiting an increase in cost to a minimum. SOLUTION: An integrated circuit having a core logic 1 and an input cell 2a and an output cell 2e made of a plurality of boundary scan cells are mounted on a package carrier and fixed on a first main face using a sealing material. A plurality of test terminals connected to a control signal terminal through a wiring is formed on the first main face, and a plurality of input/output terminals are formed on a second main face using metallic balls. These input/ output terminals are connected to an data input/output terminal of the integrated circuit through an inner face of a through hole and the wiring on the first main face, so the number of the test terminals on the first main face can be reduced, and a space between the test terminals can be enlarged and the semiconductor device can be connected easily to a testing apparatus. In addition, the integrated circuit has a simple constitution to reduce the cost to a minimum.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device capable of simplifying inspection of a mounting board.

[0002]

2. Description of the Related Art A circuit test (operation test) of a semiconductor device such as an LSI (large-scale integrated circuit) and a circuit test of a substrate on which these semiconductor devices are mounted need to be performed in a mounted state. Visual testing has become difficult due to recent increases in the density and mounting density of substrates and the appearance of devices having a connection portion such as a BGA (Ball grid array) on the lower surface of the package substrate. Although there is an in-circuit test as a test that does not rely on visual perception, it is difficult to arrange a test pattern on a substrate in response to recent demands for high-density mounting and high-density substrates. Therefore, a method has been proposed in which an external test terminal is formed on a semiconductor device and an operation test of the semiconductor device is performed via the test terminal (Japanese Patent Application Laid-Open No. 10-199941).

As a digital circuit test method that does not require many test pads on a substrate, there is a digital boundary scan test according to IEEE standard 1149.1. In this method, a portion corresponding to a test pad is built in a semiconductor integrated circuit as a digital boundary scan cell, and in addition to the digital boundary scan cell, an instruction register for receiving an instruction and a TAP for controlling the digital boundary scan cell.
(Test access port) circuit. by this,
TDI (Test data in), TDO (Test dat
a out), TMS (Test mode select) TCK (Test c
By sending a small number of signals, such as locks, many tests can be performed on the connection portions of the semiconductor device.

FIG. 4 shows an example of a package having a digital boundary scan test function. FIG. 5 is a circuit diagram of a semiconductor integrated circuit having a digital boundary scan test function mounted on the package of FIG. In the package 18 of the semiconductor device shown in FIG. 4, the core logic 1 is a main circuit having a main function of the integrated circuit. In a package of a semiconductor device having no ordinary digital boundary scan test function, the core logic 1 shown in FIG. 4 is directly connected to the signal pins 17a and 17b, and receives necessary signals from outside through these pins. In contrast, FIG.
In the package 18 shown in FIG. 1, the digital boundary scan cells 2a and 2b, the instruction register 26, and the TAP controller 27 are arranged in addition to the core logic 1 and the signal pins 17a and 17b.

In FIG. 4, digital boundary scan cells 2a to 2h correspond to test pads on a mounting board in an in-circuit test. Boundary scan cells 2a to 2d in package 18
Are input cells disposed between the input pins 17a to 17d and the core logic 1. The boundary scan cells 2e to 2h are connected to the core logic 1 and the output pins 17e to 17e.
7h.

FIG. 5 is a circuit diagram showing a configuration of an integrated circuit having a boundary scan test function in the package 18 shown in FIG. Note that, in FIG.
Of the input / output cells 2a to 2h
And only the output cell 2e. The other input / output cells have substantially the same configuration as the input cell 2a and the output cell 2e, respectively, and are omitted in FIG.

In FIG. 5, the input terminal 6 is connected to the input pin 17a of the package 18 shown in FIG. 4, and the output terminal 7 is connected to the output pin 17e of the package 18. The input cells 2a to 2d and the output cells 2e to 2h in the package 18 are provided with a test data input terminal TDI and a test data output terminal TDO, respectively. As shown in FIG. 4, terminals TDI and TDO of adjacent input / output cells
Are connected to each other. As described above with reference to FIG. 5, only two boundary scan cells of the input cell 2a and the output cell 2e are shown. However, in an actual package, the test data input terminal (TDI) 13 and the test data output terminal (TDO) 16 In between, a plurality of input / output cells are connected in a daisy chain. A series of boundary scan cells connected from the TDI terminal 13 to the TDO terminal 16 is generally called a data register. TDI terminal 13
The test data inputted through the data register, the instruction register 26 shown in FIG. 5 or the bypass register 25 shown in FIG. 4 is output to the TDO terminal 16 through the multiplexer 31.

In FIG. 5, an instruction register 26 is a register for storing an external instruction, such as an EXTEST instruction for executing an open / short test and a BYPAS for not performing an inspection on this semiconductor device.
An S instruction, an INTEST instruction for checking the core logic 1, and the like are stored. The stored instruction is reflected on the circuit through the instruction decoder 29.

The input / output pin 1 of the package 18 shown in FIG.
Test signal pins 7j to 17n are added to realize the digital boundary scan function. For example, the input pin 17j is at the TDI terminal 13 in FIG. 5, the input pin 17k is at the TMS terminal 30, and the input pin 171 is at TCK.
The terminal 8 and the output pin 17m correspond to the TDO terminal 16, respectively. The input pin 17n is an input terminal for a reset signal TRST not shown in FIG. The reset signal TRST is not essential for the circuit operation and is not shown in FIG. 5 because it is optional.

In FIG. 5, a data input terminal TDI (1
3) is a terminal for inputting a test pattern or an instruction set for the circuit to the circuit. Data output terminal TDO (1
6) is a terminal for outputting a test result and the like. Terminal 8
Is a clock signal and is input to the terminal 30.
Is a signal for changing the state of the boundary scan circuit. The state changes according to the value of the TMS signal at the rise of the clock signal signal TCK input to the TAP controller 27.

FIG. 6 shows an example of a package of a semiconductor device on which the integrated circuit shown in FIG. 5 is mounted. As shown, the core integrated circuit 1 and the semiconductor integrated circuit 19 in which a plurality of boundary scan cells are formed are mounted on a main surface 100 of an interposer 21 (package carrier) which is an insulating substrate. The integrated circuit 19 is composed of, for example, a semiconductor element formed on a semiconductor substrate, and the semiconductor substrate is sealed in the main surface 100 of the package carrier 21 by a sealing material 20. Although the sealing material 20 varies depending on the mounting mode of the integrated circuit 19, for example,
It may be an anisotropic conductive resin. Interposer 21
Of the plurality of lead wires 2 made of copper or the like
2, one end of each lead wiring 22 is connected to each terminal of the integrated circuit 19, and the other end is connected to a test terminal 23 formed on the periphery of the main surface 100.

The test terminals 23 are connected to an input terminal 8 for inputting a clock signal TCK shown in FIG.
The terminal 13, the TDO terminal 16, and the input terminal 30 for inputting the state transition signal TMS are connected respectively. For this reason, the main surface 100 of the interposer 21
At least four test terminals are formed. A plurality of signal input / output terminals 24 made of, for example, solder balls are formed on the main surface 200 of the interposer 21. Each of the solder balls 24 is arranged on the main surface 200, for example, in a matrix. A plurality of through holes are formed in the interposer 21 corresponding to the solder balls. Metal wires made of copper or the like are formed on the inner walls of these through holes, and the wires on the inner walls of each through hole are connected to the metal wires formed on the main surface 100. The solder balls formed on the main surface 200 are connected to the integrated circuit 19 mounted on the main surface 100 through the wiring formed on the inner wall of the corresponding through hole and the wiring formed on the main surface 100. Have been.

FIG. 7 is a state transition diagram of the digital boundary scan circuit shown in FIG. This digital boundary scan circuit has 16 types of states. A signal corresponding to each state of the digital boundary scan circuit is transmitted from the state decoder 28 to the data register or the instruction register 26, so that a digital boundary scan test can be performed.

Hereinafter, the operation of the digital boundary scan circuit will be described with reference to the state transition diagram of FIG. 7 using the output cell 2e in FIG. 6 as an example. The basic operation of the input cell 2a is almost the same as that of the output cell 2e.
First, in the state S1 (Test Logic Reset) in FIG. 7, the digital boundary scan cell does not operate as a test circuit, and the signal from the core logic 1 is output to the output terminal 7 through the multiplexer 5e. In the state S2 (Run Test / Idel), the digital boundary scan cell is in a standby state.

In the state S4 (Capture-DR) in FIG. 7, an enable signal (Enable) from the instruction decoder 29 and a (Capture-DR) signal from the state decoder 28 are sent. In this case, the signal from the core logic 1 is stored in the boundary scan shift register 3e.

In the state S5 (Shift-DR) in FIG. 7, an enable signal (Enable) from the instruction decoder 29 and a (Shift-DR) signal from the state decoder 28 are sent. In this case, the data stored in the boundary scan shift register 3e is output to the TDO terminal of the output cell 2e, and the data newly input from the TDI terminal of the output cell 2e is stored in the boundary scan shift register 3e. .

In the state S9 (Update-DR) in FIG. 7, an enable signal (Enable) from the instruction decoder 29 and an (Update-DR) signal from the state decoder 28 are sent. In this case, the data stored in the boundary scan shift register 3e is transmitted to the parallel latch 4e,
Is output to the output terminal 7 through the multiplexer 5e.

State S11 (Capture-IR) in FIG.
State S12 (Shift-IR) and state S16 (Update-IR)
), The state S4 (Capture-D
R), state S5 (Shift-DR) and state S9 (Update-DR)
), An instruction is sent to the data register,
The same is done for instruction register 26 while the data register operates.

A board test can be performed by a combination of the operations of the digital boundary scan cell described above. The detailed operation during the board test is described in IEEE.
According to standard 1149.1.

[0020]

The semiconductor device having the above-described conventional boundary scan circuit has the following problems. First, since there are external test terminals corresponding to the number of connection pins, the number of external test terminals increases. Since each external test terminal requires a certain interval, the external test terminals have lead wirings radially from the integrated circuit toward the periphery of the semiconductor device, and the semiconductor device itself becomes large. This meets the demand for higher density of the board, which does not have test pads on the board, but is contrary to the demand for higher density, which requires downsizing of components. Also,
The larger the components, the greater the difficulty of mounting and the lower the reliability of mounting.

Second, since the test pads are integrated into the semiconductor device as external test terminals, the interval between the external test terminals is smaller than when the test pads are arranged on a substrate. Therefore, the inspection apparatus requires high precision. This has the disadvantage of increasing the cost of the inspection device.

In order to solve this problem, a method of incorporating a digital boundary scan circuit is considered. In this method, a circuit test can be performed with four or five external test terminals such as TDI, TDO, TMS, and TCK. However, there is a problem that the cost is increased by putting a digital boundary scan circuit, which is used only at the time of manufacturing such as a board test and is not used in the market, into the integrated circuit and put it on the market.

The present invention has been made in view of the above circumstances, and an object of the present invention is to add a digital boundary scan function to an integrated circuit while minimizing a digital boundary scan circuit that is wastefully distributed to the market. To reduce the cost of the digital boundary scan circuit itself. In addition, although the semiconductor device itself has an external test terminal, the number of external test terminals can be reduced even though the semiconductor device has a simplified inspection structure, and the size and cost of the semiconductor device are reduced, and the cost of the integrated circuit is increased. It is to provide a semiconductor device which minimizes.

[0024]

In order to achieve the above object, a semiconductor device according to the present invention is a semiconductor device having a main circuit for realizing a predetermined function and a plurality of boundary scan cells, and includes at least one data line. An input terminal, at least one data output terminal, and a plurality of control signal terminals for inputting a control signal for controlling the plurality of boundary scan cells, wherein the plurality of boundary scan cells are controlled according to the control signal. A data holding circuit for holding input data, and a selection circuit for selecting and outputting either the input data or the data held by the data holding circuit in accordance with the control signal, and Cancellation is divided into two types: an input cell and an output cell. The input cell stores data input from the data input terminal. Then, either the input data or the held data is selected and input to the main circuit, the output cell holds the output data of the main circuit, and outputs the main circuit output data or the held data. One of them is selected and output to the data output terminal.

In the present invention, preferably, a package carrier for mounting the semiconductor substrate on which the main circuit and the plurality of boundary scan cells are formed, and a first carrier for mounting the semiconductor substrate in the package carrier. A plurality of test terminals formed on the main surface and a plurality of test terminals formed on the first main surface of the package carrier and connected between the test terminals and the plurality of control signal terminals on the semiconductor substrate. Wiring, a plurality of input / output terminals formed on a second main surface of the package carrier opposite to the first main surface, a plurality of through holes formed in the package carrier; Formed on the first main surface and the inner wall of the through hole;
A wiring connected between the plurality of input / output terminals formed on the second main surface and the data input terminal and the data output terminal on the semiconductor substrate;

In the present invention, preferably, the semiconductor substrate on which the main circuit and the boundary scan cell mounted on the first main surface of the package carrier are formed is sealed with a sealing material. It is fixed to the first main surface.

Further, according to the present invention, the input / output terminals formed on the second main surface of the package carrier are:
Formed by metal balls, these metal balls
The package carriers are arranged in a matrix on the second main surface.

[0028]

FIG. 1 is a circuit diagram showing one embodiment of a semiconductor device according to the present invention. As shown in FIG. 1, a semiconductor device according to the present embodiment includes a core logic 1 and an input cell 2 provided as a digital boundary scan cell.
a, and an output cell 2e. The input cell 2a and the output cell 2e have basically the same configuration.
In an actual circuit, a plurality of input cells and a plurality of output cells are arranged, respectively. However, in FIG.
And only the output cell 2e.

As shown, each of these digital boundary scan cells includes a boundary scan (hereinafter abbreviated as BS) shift register, a parallel latch, and a multiplexer. For example, the input cell 2a is a BS shift register 3
a, a parallel latch 4a and a multiplexer 5a. The operation timing of the BS shift register 3a and the parallel latch 4a is controlled by the clock signal TCK input from the input terminal 8.

The BS shift register 3a has an input terminal 6
And receives the data input from and stores it. The parallel latch 4a receives and holds the data stored in the BS shift register 3a, and outputs the held data to the multiplexer 5a. The multiplexer 5a
Either the data input from the input terminal 6 or the latch data of the parallel latch 4a is selected, and the selected data is output to the core logic 1. As shown in FIG.
The multiplexer 5a receives the input test signal INTEST input from the input terminal 14, and selects and outputs input data according to the test signal.

In substantially the same manner as the input cell 2a, the output cell 2e includes a BS shift register 3e and a parallel latch 4e.
e and a multiplexer 5e. B
-S shift register 3e and parallel latch 4e
The operation timing is controlled by the clock signal TCK input from the input terminal 8.

The BS shift register 3e receives data from the core logic 1 and stores it. The parallel latch 4e holds the data output from the BS shift register 3e and multiplexes the held data with the multiplexer 5.
e. The multiplexer 5e is a core logic 1
, Or the latch data of the parallel latch 4e, and outputs the selected data to the core logic 1. As shown in FIG. 1, the multiplexer 5e
Is the output test signal EXT input from the input terminal 15
In response to the EST, data is selected and output according to the test signal.

In FIG. 1, the (Shift-DR) signal and the (Capture-DR) signal input from the input terminals 9 and 10 are:
Each is input to the BS shift register 3a of the input cell 2a and the BS shift register 3e of the output cell 2e. The BS shift register 3 is controlled by these control signals.
The operations of a and 3e are controlled. The (Update-DR) signal input from the input terminal 11 is input to the parallel latch 4a of the input cell 2a and the parallel latch 4e of the output cell 2e. According to this control signal, the parallel 4
The operations of a and 4e are controlled. An enable signal (Enable) input from the input terminal 12 is input to the input / output cells 2a and 2e, respectively. The operating state of the BS shift registers 3a and 3e and the parallel latches 4a and 4e in the input / output cells 2a and 2e is controlled by the enable signal.

As described above, the semiconductor device of the present embodiment is different from the conventional semiconductor device having a digital boundary scan function shown in FIG. 6 in that the TAP controller 27, the state decoder 28, the instruction
The decoder 29, the instruction register 26 and the test signal multiplexer 31 are not provided. Therefore, the input terminal 30 of the state transition control signal TMS
Has also been omitted. Instead, the input terminals 9, 10,
11, 12, 14, and 15 are newly provided. Control signals (Shift-DR), (Capture-
DR), (Update-DR), an enable signal (Enable), and test signals INTEST and EXTEST are respectively input. A boundary scan test is performed in accordance with these signals.

In the above-described semiconductor device of the present embodiment, the circuit configuration is simplified, so that the circuit area can be reduced while maintaining substantially the same boundary scan function as in the conventional semiconductor device shown in FIG. Therefore, cost reduction of the semiconductor device can be realized.

FIG. 2 shows an example of a package of a semiconductor device on which the circuit shown in FIG. 1 is mounted. As shown, the package 18a includes a core logic 1 and a plurality of boundary scan cells 2a, 2b, 2c, 2d, 2
e, 2f, 2g, and 2h are provided. Among these boundary scan cells, boundary scan cell 2a
２2d are input cells, which are boundary scan cells 2e
２2h are output cells. The input cells 2a to 2d are respectively connected between the input pins 17a to 17d of the package 18a and the core logic 1, and the output cells 2e to 2h are
Each is connected between the core logic 1 and the output pins 17e to 17h. Therefore, input data from the input pins 17a to 17d of the package 18a are input to the core logic 1 via the input cells 2a to 2d, respectively. Output data of the core logic 1 is output to output pins 17e to 17h of the package 18a via output cells 2e to 2h, respectively.

As shown in FIG. 2, in the boundary scan cells 2a to 2h, test data input terminals and output terminals of adjacent cells are connected to each other. That is, these boundary scan cells constitute a scan cell chain. The test data input pin 17j (TDI) of the package 18a is connected to the test data input terminal of the cell 2d at the head of the scan chain,
The test data output terminal 18n of the package 18a
(TDO) is connected to the test data output terminal of the last cell 2h of the scan chain.

At the time of the scan operation, the test data input from the test data input pin 17j of the package 18a is sequentially transmitted by the cells forming the scan chain. For example, test data input from the test data input pin 17j is transmitted in the order of cells 2d, 2c, 2b, and 2a. By this scanning operation, the package 1
When a test pattern composed of serial data is input to the test data input pin 17j of 8a, each bit of the test pattern is held by each of the input cells 2a to 2d. Then, after all the bits of the test pattern have been input to each input cell, these input cells can be input to the core logic 1 in parallel. On the output side, the parallel data output from the core logic 1 as opposed to the input side is output cells 2e to 2h.
Is converted into serial data and output to the test data output pin 17n. For example, each bit of the data output by the core logic 1 is held by each of the output cells 2e to 2h. Then, the data held by the output cells 2e to 2h are sequentially transmitted to the test data output pins 17n of the package 18 and output as serial data.

In addition to the scanning operation described above, the input cell 2
The data cells a to 2d and the output cells 2e to 2h can also input and output data as normal input buffers and output buffers. For example, on the input side, the input cells 2a to 2a
2d functions as an input buffer, and inputs the input data from the input pins 17a to 17d of the package 18 to the core logic 1 respectively. On the output side, output cell 2
e to 2h output the output data from the core logic 1 to the output pins 17e to 17h of the package 18, respectively.

The operations of the input cell and the output cell described above correspond to the test signal TEST and the enable signal (Enabl) input from the control signal pins 171, 17m, 17p, 17q, 17r of the package 18.
e) and control signals (Shift-DR), (Capture-DR), (U
pdate-DR). These signals are input to the boundary scan cells 2a to 2h in the package 18, respectively, and the operation of each of the boundary scan cells is controlled by these external signals. That is, for example, in the conventional semiconductor device shown in FIG. 5, the TAP controller 27 and the state decoder 28 receiving the state transition control signal TMS enable the enable signal (Enab).
le) and control signals (Shift-DR), (Capture-DR),
(Update-DR), and controlled the operation of boundary scan cells. On the other hand, in the present embodiment, control signals for controlling the operation of the boundary scan cell, for example, control signals (Shift-DR), (Capture-DR),
(Update-DR) is supplied directly from outside, so TA
The operation delay caused by the processing time of the P controller and the state decoder is eliminated, and high-speed control can be realized.
Shortening of test time can be achieved.

FIG. 3 shows an example of a package of a CSP (Chip Size Package) semiconductor device with an external test terminal on which the circuit shown in FIG. 1 is mounted. FIG. 2A is a three-dimensional view of the package of the semiconductor device, and FIG. 2B is a cross-sectional view of the package along the line AA ′ in FIG. 2, the integrated circuit 19 is composed of a plurality of semiconductor elements formed on a semiconductor substrate. The semiconductor substrate is mounted on a main surface 100 of an interposer 21 (package carrier), which is an insulating substrate, and is sealed in the main surface 100 by a sealing material 20. The sealing material 20 varies depending on the mounting mode of the integrated circuit 19, but may be, for example, an anisotropic conductive resin. On the main surface 100 of the interposer 21, a plurality of lead wires 22 are formed of copper or the like, one end of each of the lead wires 22 is connected to each terminal of the integrated circuit 19, and the other end is connected to the main surface 100. Is connected to a test terminal 23 formed in the peripheral portion of.

The test terminal 23 is an input terminal 8, a TDI terminal 13, and a TDO terminal 1 for the clock signal TCK shown in FIG.
6, enable signal (Enable) terminal 12, test signal terminals INTEST, EXTEXT terminals 14, 15, and control signals (Shift-DR), (Capture-DR), (Update-DR)
) Terminals 9, 10, and 11 are connected to each other, and at least eight, for example, are formed. Interposer 2
A plurality of signal input / output terminals 24 formed of, for example, solder balls are formed on one main surface 200.
The solder balls 24 are arranged on the main surface 200, for example, in a matrix.

A plurality of through holes are formed in the interposer 21 corresponding to the respective solder balls. Metal wires made of copper or the like are formed on the inner walls of these through holes, and the wires on the inner walls of each through hole are connected to the metal wires formed on the main surface 100. For this reason, the solder balls formed on the main surface 200 pass through the wiring formed on the inner wall of the corresponding through hole and the wiring formed on the main surface 100, respectively, and the integrated circuit mounted on the main surface 100. 19 is connected. When the package is mounted on a printed circuit board or the like, the input / output terminals 24 formed of these solder balls serve as connecting portions to a mounting board not shown in FIG. That is, the input / output terminals made of the respective solder balls come into contact with the metal pattern formed on the mounting board to transmit signals.

In the package of the semiconductor device shown in FIG. 3, the number of test terminals is slightly increased as compared with the conventional semiconductor device, for example, the package of the semiconductor device shown in FIG. Since a sufficient space for arranging the increased number of terminals can be secured, the test terminals and the wiring corresponding thereto can be easily realized without increasing the size of the package. Therefore, the size of the package of the semiconductor device can be reduced, and the structure of the integrated circuit mounted on the package is simplified, so that the cost of the semiconductor device can be reduced and high-density mounting can be realized. Further, since the number of test terminals formed on the surface of the package is small and the interval between the test terminals can be made relatively large, an increase in the cost of the inspection apparatus itself can be avoided.

As described above, according to this embodiment, the integrated circuit including the core logic 1 and the input cells 2a to 2d and the output cells 2e to 2h each including a plurality of boundary scan cells is mounted on a package carrier. The circuit is fixed to the first main surface of the package carrier by a sealing material. A plurality of test terminals are formed on a first main surface, each test terminal is connected to a control signal terminal of an integrated circuit via a wiring, and a plurality of input / output terminals are formed on a second main surface by metal balls. , These input / output terminals are respectively connected to the inner wall of a plurality of through holes formed in the package carrier and the first
Connected to the data input and data output terminals of the integrated circuit via the wiring formed on the main surface of the first main surface, the number of test terminals on the first main surface is small, the interval between the test terminals can be increased, and the inspection device and Connection can be easily realized. Further, the increase in cost can be suppressed to a necessary minimum by simplifying the configuration of the integrated circuit.

[0046]

As described above, according to the semiconductor device of the present invention, the circuit configuration can be simplified while retaining the digital boundary scan function, and the package can be packaged in comparison with a semiconductor device having a normal boundary scan function. Can be reduced in size and cost. Further, in the semiconductor device of the present invention, since control signals for controlling the boundary scan test function are supplied from the outside through test terminals formed on the package, these control signals are internally supplied to the integrated circuit. Compared with a conventional semiconductor device generated by a control circuit, a decoder, or the like, the operation delay time can be reduced, and the test can be performed faster and the test time can be reduced. Furthermore, in the semiconductor device of the present invention, the number of test terminals formed on the package can be reduced, and the interval between test terminals can be sufficiently ensured.
In addition to cost reduction, there is an advantage that the size of the entire mounted circuit can be reduced and the cost can be reduced due to the small size of the package of the semiconductor device.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a semiconductor device according to the present invention.

FIG. 2 is a conceptual diagram showing an internal configuration of a package of the semiconductor device shown in FIG.

3A and 3B are a three-dimensional view and a cross-sectional view illustrating an example of a package on which the integrated circuit illustrated in FIG. 1 is mounted.

FIG. 4 is a conceptual diagram of a package showing a configuration of a conventional semiconductor device.

FIG. 5 is a circuit diagram showing a configuration of an integrated circuit mounted on a conventional semiconductor device.

FIG. 6 is a three-dimensional view and a cross-sectional view showing a package of a conventional semiconductor device.

FIG. 7 is a state transition diagram showing an operation of a conventional semiconductor device.

[Explanation of symbols]

1 ... core logic, 2a, 2b, 2c, 2d, 2e, 2
f, 2g, 2h ... Boundary scan cell, 3a, 3e
... Boundary scan shift registers, 4a, 4e ...
Parallel latch, 5a, 5e multiplexer, 6 data input terminal, 7 data output terminal, 8 terminal for inputting clock signal TCK, 9, 10, 11 control signal terminal, 12 enable signal terminal, 13 ... input terminals for inputting test data, 14, 15 ... test signal terminals, 16 ... output terminals for outputting test data,
17h, input / output pins, 17j, test data input pins, 17k, clock signal TCK pins, 17l, test signal pins, 17m, enable signal pins, 17n, test data output pins, 17p, 17
q, 17r: control signal pins, 18: package, 19:
Semiconductor integrated circuit, 20: sealing material, 21: interposer,
Reference numeral 22: metal wiring, 23: test terminal, 24: solder ball, 26: instruction register, 27: instruction decoder, 28: state decoder, 29: TAP controller, 30: state transition signal input terminal, V _CC : power supply Voltage, GND: ground potential.

Claims (6)

[Claims] 1. A semiconductor device having a main circuit realizing a predetermined function and a plurality of boundary scan cells, comprising: at least one data input terminal; at least one data output terminal; A plurality of control signal terminals for inputting a control signal for controlling the control signal, wherein the plurality of boundary scan cells hold the input data according to the control signal, and the input signal according to the control signal. A selection circuit for selecting and outputting either data or data held by the data holding circuit, and wherein the plurality of boundary scan cells are divided into two types of cells for input and cells for output; The cell for holding the data input from the data input terminal, selecting either the input data or the held data Enter the serial main circuit, the output cell, and holds the output data of the main circuit,
A semiconductor device for selecting either the output data of the main circuit or the held data and outputting the selected data to the data output terminal. 2. A package carrier for mounting a semiconductor substrate on which the main circuit and the plurality of boundary scan cells are formed, and a plurality of packages formed on a first main surface of the package carrier on which the semiconductor substrate is mounted. A test terminal formed on the first main surface of the package carrier;
A wiring connected between the test terminal and the plurality of control signal terminals on the semiconductor substrate; and a wiring formed on a second main surface of the package carrier opposite to the first main surface. A plurality of input / output terminals; a plurality of through holes formed in the package carrier; a first main surface of the package carrier and an inner wall of the through hole; and a plurality of through holes formed in the second main surface. 2. The semiconductor device according to claim 1, further comprising a wiring connected between the plurality of input / output terminals and the data input terminal and the data output terminal on the semiconductor substrate. 3. The semiconductor substrate on which the main circuit and the boundary scan cell mounted on the first main surface of the package carrier are fixed to the first main surface with a sealing material. 3. The semiconductor device according to claim 2, wherein: 4. The semiconductor device according to claim 2, wherein said input / output terminals formed on said second main surface of said package carrier are formed of metal balls. 5. The package according to claim 4, wherein the metal balls are arranged in a matrix on the second main surface of the package carrier.
13. The semiconductor device according to claim 1. 6. The semiconductor device according to claim 2, wherein said package carrier is constituted by a printed circuit board.