CN107870773A - A kind of method of online updating FPGA programs - Google Patents
A kind of method of online updating FPGA programs Download PDFInfo
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- CN107870773A CN107870773A CN201711189963.0A CN201711189963A CN107870773A CN 107870773 A CN107870773 A CN 107870773A CN 201711189963 A CN201711189963 A CN 201711189963A CN 107870773 A CN107870773 A CN 107870773A
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- fpga
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- external memory
- memory storage
- online updating
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
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- Computer Security & Cryptography (AREA)
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Abstract
A kind of method for the upgrading of FPGA system remote online program of the present application.The present invention is connected external memory storage by jtag interface in FPGA I/O pin simultaneously；Memory control module, program receiving module are set inside FPGA.By program receiving module by the program transportation to be updated to FPGA, external memory storage is first wiped by memory control module, then write new program；After new procedures download is completed, FPGA is restarted again completes program renewal.Upgrading is updated to external memory storage using FPGA internal logics in the case where not increasing hardware cost substantially.
Description
Technical field
The present invention relates to server test field, and in particular to a kind of method of online updating FPGA programs.
Background technology
FPGA (Field-Programmable Gate Array field programmable gate arrays) bit stream loading technique is
An essential part in FPGA design and debugging.In the prior art the loading of FPGA bit streams be all using outside downloading wire or
Device is downloaded, and currently passes through JTAG (Joint to the downloading mode majority of FPGA bit stream files for the online cable of PC
Test Act ion Group joint test behavior tissues, a kind of boundary scan technique) interface download, with jtag interface to FPGA
External memory storage carries out programming, and PC must be used by JTAG cables, and it is without FPGA remote downloads itself and control work(
Can, this mode brings inconvenience to product up-gradation.And remote download will be carried out in actual applications to FPGA by often occurring
Scene.
For FPGA system run into can not off line ROMPaq the problem of, the present application it is a kind of for FPGA system it is long-range
In the method for sequence of threads upgrading.The present invention by external memory storage by jtag interface connect FPGA, do not increase substantially hardware into
Upgrading is updated to external memory storage using FPGA internal logics in the case of this.
The content of the invention
At present in FPGA commercialization, FPGA working method is substantially long-range off-line working, main mesh of the invention
Be that how solution does not increase hardware cost and realize remote online and update position in the case of this long-range off-line working
The problem of stream code.
In the case of normal, FPGA is to connect FPGA external memory storages by jtag interface.PC utilizes jtag interface line
Cable carries out erasable operation to external memory storage, and outside newest program in machine code is put into external memory storage.When upper electricity again
When, FPGA loads newest program in machine code from external memory storage automatically, so as to realize the purpose of FPGA programs renewal.But
Such case needs to connect circuit board is connected to JTAG cables always, can not accomplish off line or long-range renewal FPGA programs.This Shen
The method for the online updating FPGA programs that please be invent, then JTAG cables can be no longer needed completely, but utilize FPGA right in itself
External memory storage is updated.
Specifically, a kind of method of online updating FPGA programs is claimed in the application, it is characterised in that this method is specific
Including：
While jtag interface is connected to external memory storage, jtag interface is connected in FPGA I/O pin；
Memory control module is set inside FPGA, for controlling the erasable of external memory storage；
One program receiving module is set inside FPGA, for obtaining the program to be updated outside FPGA；
When need to be updated program to FPGA external memory storages when, it will be updated by program receiving module
Program transportation is first wiped external memory storage in FPGA by memory control module, is write again after erasure completion new
Program；After new procedures download is completed, FPGA is restarted again just completes program renewal.
The method of online updating FPGA programs as described above, is further characterized in that, without using FPGA to external storage
When device enters line program renewal, FPGA pins are arranged to high-impedance state.
The method of online updating FPGA programs as described above, is further characterized in that, one is also set up inside FPGA and is delayed
Storing module, for preventing the mismatch of program receiving module and memory control module in speed.
The method of online updating FPGA programs as described above, is further characterized in that, the cache module is one small delays
FIFO in punch die block piece.
The method of online updating FPGA programs as described above, is further characterized in that, program receiving module can be various
Different interface modes.
Brief description of the drawings
Fig. 1, online updating FPGA programs of the present invention operating diagram
Fig. 2, prior art operating diagram
Embodiment
As shown in Figure 1, the present invention needs jtag interface while is connected in FPGA I/O pin, FPGA external memory storages
Just linked together with FPGA, the sequential that jtag interface can be simulated by these I/O pins is wiped external memory storage
Write, newest program in machine code is put into external memory storage, realize the purpose to be downloaded by JTAG cables.The tool of the function
Body is implemented without additional device, it is only necessary to makes when circuit design and a little changes.
In addition to needing to add the pin for downloading external memory storage, FPGA will also have from external reception new procedures
Module.This module can be common i2c interfaces, spi interfaces etc. or network interface.It is many in the prior art
FPGA system inherently carries this interface, so can substantially not have to add external interface again.
When need to be updated program to FPGA external memory storages when, it be able to will be updated by external interface
Program transportation is in FPGA.A memory control module is added inside FPGA, it is advanced to external memory storage by the module
Row erasing.New program is write after erasure completion again.After new procedures download is completed, FPGA is restarted again just completes program more
Newly.
A specific embodiment of the method for 1 pair of online updating FPGA program of the present invention is carried out below in conjunction with the accompanying drawings
Explanation.
The method of online updating FPGA programs of the present invention connects jtag interface and FPGA pin.Normally
Design in order to carry out JTAG cable downloads, be that jtag interface is connected on external memory storage.The present invention is same on this basis
When be also connected on FPGA pins.Because FPGA pins could be arranged to high-impedance state.Without using, do not need FPGA it is external
When portion's memory enters line program renewal, FPGA pins are arranged to high-impedance state, are that jtag interface and outside will not be deposited
Reservoir is influential.
External memory storage control module is set inside FPGA, and it is the erasable of control external memory storage that it, which is acted on,.Work as needs
When being updated to the program in external memory storage, module is started working.It is advanced according to the timing requirements of external memory storage
Row erasing, then by new burning program into external memory storage.
Also set up a program receiving module.The major function of this module is the program for obtaining being updated outside FPGA,
Can be a variety of interfaces, such as i2c, spi, Ethernet interface.In general FPGA system is to have this connect in itself
Mouthful, so substantially the program of this interface need not be developed again.
One cache module is set inside FPGA, because external program receiving module and memory control module are in speed
Some upper mismatches, so having added FIFO on a small buffer module piece inside FPGA.
It should be evident that illustrated above is only the specific embodiment of the present invention, for the common skill in this area
For art personnel, on the premise of not paying creative work, other technical schemes can also be obtained according to above-described embodiment,
And the equivalent variations made in the scope of protection of the invention all should be fallen within the scope of protection of the present invention, and belong to the present invention
The scope of protection.
In summary, the method for the online updating FPGA programs of the present application, JTAG cables can be no longer needed, but
External memory storage is updated in itself using FPGA.Can solve remote online more in the case where not increasing hardware cost
The problem of new bit stream code.
Claims (5)
- A kind of 1. method of online updating FPGA programs, it is characterised in that this method specifically includes：While jtag interface is connected to external memory storage, jtag interface is connected in FPGA I/O pin；Memory control module is set inside FPGA, for controlling the erasable of external memory storage；One program receiving module is set inside FPGA, for obtaining the program to be updated outside FPGA；When needing to be updated program to FPGA external memory storages, the program that will be updated by program receiving module It is transferred in FPGA, external memory storage is first wiped by memory control module, writes new journey after erasure completion again Sequence；After new procedures download is completed, FPGA is restarted again just completes program renewal.
- 2. the method for online updating FPGA programs as claimed in claim 1, is further characterized in that, without using FPGA to outside When memory enters line program renewal, FPGA pins are arranged to high-impedance state.
- 3. the method for online updating FPGA programs as claimed in claim 1, is further characterized in that, one is also set up inside FPGA Individual cache module, for preventing the mismatch of program receiving module and memory control module in speed.
- 4. the method for online updating FPGA programs as claimed in claim 1, is further characterized in that, the cache module is one small Buffer module piece on FIFO.
- 5. the method for online updating FPGA programs as claimed in claim 1, is further characterized in that, program receiving module can be A variety of interface modes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711189963.0A CN107870773A (en) | 2017-11-24 | 2017-11-24 | A kind of method of online updating FPGA programs |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711189963.0A CN107870773A (en) | 2017-11-24 | 2017-11-24 | A kind of method of online updating FPGA programs |
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| CN201711189963.0A Pending CN107870773A (en) | 2017-11-24 | 2017-11-24 | A kind of method of online updating FPGA programs |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102279756A (en) * | 2010-06-11 | 2011-12-14 | 英业达股份有限公司 | CPLD (Complex Programmable Logic Device) firmware updating method |
| CN102436385A (en) * | 2011-11-15 | 2012-05-02 | 电子科技大学 | Online updating device for configuration files of programmable logic device |
| CN104407882A (en) * | 2014-10-28 | 2015-03-11 | 大唐移动通信设备有限公司 | Board card device |
| CN105955783A (en) * | 2016-05-09 | 2016-09-21 | 浙江大学 | Method for downloading remote FPGA logic codes on basis of FPGA control |
-
2017
- 2017-11-24 CN CN201711189963.0A patent/CN107870773A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102279756A (en) * | 2010-06-11 | 2011-12-14 | 英业达股份有限公司 | CPLD (Complex Programmable Logic Device) firmware updating method |
| CN102436385A (en) * | 2011-11-15 | 2012-05-02 | 电子科技大学 | Online updating device for configuration files of programmable logic device |
| CN104407882A (en) * | 2014-10-28 | 2015-03-11 | 大唐移动通信设备有限公司 | Board card device |
| CN105955783A (en) * | 2016-05-09 | 2016-09-21 | 浙江大学 | Method for downloading remote FPGA logic codes on basis of FPGA control |
Non-Patent Citations (1)
| Title |
|---|
| 张永乐，王永勇，郑炜: ""一种基于FPGA 的在线程序升级方案"", 《电子技术应用》 * |
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Application publication date: 20180403 |
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