CN109189624A - A kind of magnanimity information processing device single particle experiment implementation method and single particle test plate - Google Patents
A kind of magnanimity information processing device single particle experiment implementation method and single particle test plate Download PDFInfo
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- CN109189624A CN109189624A CN201811058513.2A CN201811058513A CN109189624A CN 109189624 A CN109189624 A CN 109189624A CN 201811058513 A CN201811058513 A CN 201811058513A CN 109189624 A CN109189624 A CN 109189624A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
- G06F11/2242—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors in multi-processor systems, e.g. one processor becoming the test master
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/273—Tester hardware, i.e. output processing circuits
- G06F11/2733—Test interface between tester and unit under test
Abstract
The invention discloses a kind of magnanimity information processing device single particle experiment implementation method and single particle test plates, and the method includes the verifying of 4 road 4X RapidIO single particle experiments, the compatible DDR2/DDR3 single particle experiment verifying of ddr interface, debugging, reset and process monitoring design and the single particle experiment verifyings of low-speed communication interface；The single particle test plate includes 1601ARH, 4 Samtec connectors connecting with the 4 road RapidIO interfaces of 1601ARH, 2 CDCM6208 connecting with the REFCLK interface of 1601ARH, 3 DDR3+SDRAM connecting with the ddr interface being integrated on PPC core on 1601ARH, the FPGA connecting with the debugging interface of 1601ARH and 422 serial ports transceivers connecting with the 4 road low-speed communication interfaces of 1601ARH.The present invention meets the single particle experiment verifying of the 4 road 4X RapidIO design functions and different working modes of 1601ARH, complete the single particle experiment verifying of 2 DDR2/DDR3 interface compatibilities, the single particle experiment verifying for realizing monitoring, reset and the test of low-speed communication module self-cycle etc., completes the verifying, identification and examination to the 1601ARH anti-radiation performance designed.
Description
Technical field
The invention belongs to Application of integrated circuit verifying and environmental test fields, are related to a kind of magnanimity information processing device simple grain
Son test implementation method and single particle test plate.
Background technique
1601ARH is the multi-core processor of a Flouride-resistani acid phesphatase, belongs to the positive sample of the high ground term mesh of core " magnanimity information processing device "
Chip integrates the DSP core of PPC core and 16 autonomous instruction set, is interconnected by network-on-chip, and collect on network-on-chip
At multiple functional modules such as QDR, DDR, EMIF/PIU and RapidIO and high-speed communication interface.Flouride-resistani acid phesphatase design objective is simple grain
Son overturning (SEU error rate) (geostationary orbit)≤10-5Mistake/device day, single event latch-up threshold value >=75MeVcm2/
mg.But the existing application verification plate for first sample proofing chip 1601P cannot be unfolded 1601ARH because of design object difference
Single particle experiment verifying, the functional block diagram of 1601P application verification plate are as shown in Figure 1.Firstly, 1601P application verification plate will
The high speed Bank of 4 road the 4X RapidIO and FPGA of 1601P is interconnected to carry out functional verification, be easy in single particle experiment because
The exception of FPGA function and cause test judge by accident；Secondly, 1601ARH devises the memory control of two compatible DDR2/DDR3
Device interface has separately designed DDR2+SDRAM and DDR3+SDRAM on the application verification plate of 1601P to verify it and design function
Can, integrated level is too high in single particle experiment, and memory is easy to be influenced by single particle experiment environment, and too many high density is deposited
Reservoir will affect the judgement of test result；Finally, design of the 1601P application verification plate in debugging interface and low-speed communication interface
It is unsatisfactory for the requirement such as monitoring, reset and self-looped testing in single particle experiment, is unsatisfactory for 1601ARH single particle experiment verifying work
The demand of work.
Summary of the invention
It is an object of the invention to overcome the above-mentioned prior art, a kind of magnanimity information processing device single-particle is provided
Test implementation method and single particle test plate.
In order to achieve the above objectives, the present invention is achieved by the following scheme:
A kind of magnanimity information processing device single particle experiment implementation method, comprising the following steps:
The 4 road RapidIO of 1601ARH are connected to the edge of pcb board by 4 connectors, carry out 4 road RapidIO's
The step of verification experimental verification of communication function, interconnection test and self-looped testing；
It will be integrated in the ddr interface on PPC core in 1601ARH and carry out DDR2 and DDR3 by integrated 3 DDR3+SDRAM
The compatible verification experimental verification of function, the test point that the ddr interface being integrated on network-on-chip reserves key signal carry out itself function
The step of monitoring；
It is connected to FPGA while the debugging interface of 1601ARH is normally drawn, is connect in FPGA by converting integrated DSU
Mouthful, carry out the step of debugging 1601ARH over long distances；
Reset signal and interrupt signal accessed into FPGA, the monitoring of process is resetted and tested by debugging interface
Step；
The 4 road low-speed communication interfaces of 1601ARH are connected to transceiver, the edge of pcb board is connected to by connector,
And ring is reserved before being connected to transceiver and surveys interface, carry out the communication function verification experimental verification of low-speed communication module and is surveyed from ring
The step of examination；
Above-mentioned steps since any or appoint it is several start simultaneously at progresss, up to above-mentioned steps complete when terminate.
A further improvement of the present invention lies in that:
Carry out the communication function of RapidIO, the verification experimental verification of interconnection test and self-looped testing method particularly includes:
The minimum system that 1601ARH is designed in 1601ARH single particle test plate generates 16 pairs using 2 CDCM6208
Differential clocks individually provide difference ginseng by the operating mode of 4 road 1X RapidIO for every road 4X RapidIO of 1601ARH
Clock is examined, makes 1601ARH work under 1X or 4X mode；It sends and receives signal and carries out high-frequency resistance matching and filtering processing
Afterwards, it is connected to the edge of pcb board by 4 Samtec connectors, carries out the communication function of RapidIO, interconnection test and from ring
The verification experimental verification of test.
Two panels forms 32 data bit widths in 3 DDR3+SDRAM, and third piece only carries out EDAC verification function with least-significant byte
The verifying of energy.
Carry out debugging 1601ARH's over long distances method particularly includes:
FPGA is connected to while the debugging interface of 1601ARH is normally drawn, integration logic is converted in FPGA, will
The JTAG debugging interface of 1601ARH is converted to DSU interface, connects after being converted into 422 agreements by 422 transceivers after being picked out
To PC machine, debugging 1601ARH over long distances is carried out.
Resetted and tested the monitoring of process method particularly includes:
The reset signal of 1601ARH provides after being generated by external reset switch after TPS70302 to FPGA, Huo Zheyou
DSU sends reset command to FPGA, generates reset signal by FPGA and is answered under the logic control of FPGA to 1601ARH
The monitoring of position and test process.
Carry out communication function verification experimental verification and the self-looped testing of low-speed communication module method particularly includes:
It after the 4 road low-speed communication interfaces of 1601ARH are picked out, reserves ring and surveys interface, electricity is being carried out by level translator
After flat turn is changed, it is connected to after 422 transceivers carry out transmitting-receiving protocol conversion, the edge of pcb board is connected to by DB35 connector, into
The communication function verification experimental verification of row low-speed communication module and self-looped testing.
A kind of magnanimity information processing device single particle test plate, which is characterized in that 4 tunnels including 1601ARH and 1601ARH
RapidIO interface connection 4 Samtec connectors, connect with the RECLK interface of 1601ARH 2 CDCM6208, and
3 DDR3+SDRAM of the ddr interface connection being integrated on 1601ARH on PPC core, it connect with the debugging interface of 1601ARH
FPGA and 422 serial ports transceivers being connect with the 4 road low-speed communication interfaces of 1601ARH；Wherein:
4 Samtec connectors are used to for the 4 road RapidIO of 1601ARH being connected to the edge of single particle test plate；
2 CDCM6208 press 4 road 1X for generating 16 pairs of differential clocks, and for every road 4X RapidIO of 1601ARH
The operating mode of RapidIO individually provides differential reference clock；
3 DDR3+SDRAM are laid out wiring by the topological structure of DDR2, the examination compatible for DDR2 and DDR3 function
Verifying；
FPGA is used to be converted to the debugging interface of 1601ARH DSU interface, and provides reset signal in for 1601ARH
Break signal；
The 4 road low-speed communication interfaces of 1601ARH reserve ring before being connected to serial ports transceiver and survey interface, are used for low speed
The self-looped testing of communication module and the verification experimental verification of communication function.
Further include to FPGA provide reset signal reset switch and TPS70302 power management chip, reset signal by
Reset switch is provided through TPS70302 to FPGA after generating.
Compared with prior art, the invention has the following advantages:
The present invention connect the side of 4 road 4X RapidIO to breadboard edge by using 1601ARH with Samtec connector
The RapidIO of formula, alternative processor and FPGA are interconnected, and are verified and are designed compared to conventional func, which can not only try
The communication function for verifying 1X/4X RapidIO, can also verify the veneer interconnected communication and self-looped testing function of RapidIO,
Greatly improve the spreadability of verification experimental verification；By the way that the ddr interface on PPC core external 3 will be integrated in 1601ARH
DDR3+SDRAM carries out the compatible verification experimental verification of DDR2 and DDR3 function, the reserved key of the ddr interface being integrated on network-on-chip
The test point of signal can sufficiently verify the DDR2/3 compatibility of 1601ARH design；Using by the debugging of 1601ARH, reset and
Interrupt signal is connected to FPGA, passes through in FPGA and converts integrated DSU interface, and then debugging over long distances, reset and mistake may be implemented
The function of range monitoring；By reserving before signal enters transceiver from ring access port in 4 road UART, low-speed communication is completed
The self-looped testing of module and authentication design.Ensure the comprehensive verification and anti-spoke to magnanimity information processing device design function
According to effective assessment of performance, lay a good foundation for the anti-radiation performance examination and identification of magnanimity information processing device.
Detailed description of the invention
Fig. 1 is existing 1601P application verification plate functional block diagram；
Fig. 2 is 1601ARH single particle test plate functional block diagram of the invention；
Fig. 3 is the RapidIO verification experimental verification functional block diagram of 1601ARH of the invention；
Fig. 4 is the DDR verification experimental verification functional block diagram of 1601ARH of the invention；
Fig. 5 is debugging interface verification experimental verification functional block diagram of the invention；
Fig. 6 is the verification experimental verification functional block diagram of reset of the invention, monitoring signal；
Fig. 7 verifies functional block diagram from ring, communication experiment for UART of the invention.
Specific embodiment
In order to enable those skilled in the art to better understand the solution of the present invention, below in conjunction in the embodiment of the present invention
Attached drawing, technical scheme in the embodiment of the invention is clearly and completely described.Obviously, described embodiment is only
It is the embodiment of a part of the invention, instead of all the embodiments.Based on the embodiments of the present invention, the common skill in this field
Art personnel every other embodiment obtained without making creative work, all should belong to protection of the present invention
Range.
It should be noted that description and claims of this specification and term " first " in above-mentioned attached drawing, "
Two " etc. be to be used to distinguish similar objects, without being used to describe a particular order or precedence order.It should be understood that making in this way
Data are interchangeable under appropriate circumstances, so that the embodiment of the present invention described herein can be in addition to scheming herein
Sequence other than those of showing or describe is implemented.In addition, term " includes " and " having " and their any deformation, it is intended that
Be to cover it is non-exclusive include, for example, containing the process, method, system, product or equipment of a series of steps or units
Those of be not necessarily limited to be clearly listed step or unit, but may include be not clearly listed or for these processes,
The intrinsic other step or units of method, product or equipment.
The invention will be described in further detail with reference to the accompanying drawing:
Magnanimity information processing device single particle experiment implementation method of the present invention compares existing 1601P for how to provide one kind
Application verification, be both able to satisfy the single particle experiment of 4 road the 4X RapidIO design functions and different working modes of 1601ARH
Verifying, and the single particle experiment verifying of 2 DDR2/DDR3 interface compatibilities can be completed, moreover it is possible to realize that monitoring, reset and low speed are logical
The single particle experiment verifying for believing module self-cycle test etc., complete to the verifying of 1601ARH anti-radiation performance design, identify and
The problem of examination.The 4 road RapidIO of 1601ARH are all connected to the side of pcb board using 4 Samtec connectors by the present invention
The single particle experiment verifying of the 4 road 4X RapidIO design functions of 1601ARH is completed on edge.Specific method is, mono- in 1601ARH
The minimum system of 1601ARH is designed on particle breadboard, the 16 pairs of differential clocks generated using 2 CDCM6208 are
Every road 4X RapidIO of 1601ARH provides differential reference clock by the operating mode of 4 road 1X RapidIO respectively, makes
1601ARH can work respectively under 1X or 4X operating mode；Samtec is regarded as a communication terminal, according to close to reception
The principle at end is filtered the layout of capacitor, and carries out Samtec pipe according to the design on 0 tunnel and the interconnection of 1 tunnel, 2 tunnels and the interconnection of 3 tunnels
The definition of foot, it is ensured that interconnected communication test can be carried out by high-speed dedicated cable；The RapidIO of 1601ARH design is in outside
It can be with self-looped testing in the case where there is no terminal load.By designing the 4 road 4X, it can be achieved that 1601ARH design above
The 1X/4X of RapidIO is compatible, mixed, ring is surveyed and the single particle experiment of self-test is verified and examination.It is integrated on 1601ARH
Two ddr interfaces, wherein first ddr interface is integrated on network-on-chip, second ddr interface is integrated on PPC core,
It is connected to network-on-chip by PPC, and the design objective of two ddr interfaces is identical, compatible DDR2+SDRAM and DDR3+
SDRAM.In the design of 1601ARH single particle experiment, first ddr interface does not connect memory particle, extension key letter
Number to monitor its function；The external 3 DDR3+SDRAM memories of second ddr interface, wherein preceding two panels forms 32 data bit
Width, third piece only use least-significant byte, carry out the verifying of EDAC verifying function, and are laid out wiring by the topological structure of DDR2.
In this way, just completing two DDR2/3 interface compatibilities of 1601ARH by a secondary design in the same single particle test plate
The verification experimental verification of design.By the debugging interface JTAG of 1601ARH other than normally drawing, it is also connected to FPGA, is passed through in FPGA
Conversion integrates DSU interface, and 1601ARH can be debugged over long distances by facilitating under emergency case；Access FPGA will be resetted and be interrupted, will be led to
Cross the monitoring that debugging interface is resetted and tested process；4 road UART reserve wire jumper interface, side before being connected to transceiver
Just self-looped testing.In this way, realize reset, monitoring, debugging long range is controllable and the self-looped testing of low-speed communication module with
And the single particle experiment of communication function verifies design.
Magnanimity information processing device single particle test plate theory structure and application conditions of the present invention:
(1) single particle test plate theory structure
The single particle test plate of magnanimity information processing device 1601ARH is connect by 1601ARH, 2 CDCM6208,4 Samtec
Plug-in unit, 3 DDR3+SDRAM, a piece of FPGA and 4 422 serial ports transceiver are constituted, wherein the debugging, reset of 1601ARH and prison
Control signal is connected with FPGA, and PC machine is connected to after integrating DSU mouthfuls in FPGA, forms single particle test plate, as shown in Figure 2.
The 4 road 1X/4X RapidIO of 1601ARH provide reference difference clock by two panels CDCM6208 by 1X operating mode, send and connect
It collects mail after number progress high-frequency resistance matching and filtering processing, the edge of plate is connected to by Samtec connector, cable can be carried out
Communication test, ring are surveyed and the work of the verification experimental verifications such as self-test, as shown in Figure 3.In order to verify 1601ARH in single particle experiment
Ddr interface, 3 DDR3+SDRAM are integrated at the DDR control interface of PPC, and are laid out cloth by the topological structure of DDR2
Line；The ddr interface of network-on-chip is then drawn chief signal and is monitored, and is not connected to memory particle, as shown in Figure 4.
After the debugging interface of 1601ARH is connected with FPGA, integration logic is converted in FPGA, and the JTAG debugging interface of 1601ARH is turned
It is changed to DSU interface, is converted into being connected to PC machine after 422 agreements by transceiver after being picked out, as shown in Figure 5.1601ARH's
Reset signal is issued by outside and is provided after TPS70302 to FPGA, under the logic control of FPGA, can be provided by outside,
It can also be controlled by debugging interface DSU；Its INT signal can be used as the condition monitoring signal of 1601ARH, enter
By DSU oral instructions to PC machine after FPGA, the monitoring of test process is realized, as shown in Figure 6.By the 4 road low-speed communications of 1601ARH
It after interface UART is picked out, reserves ring and surveys interface, after carrying out level conversion and transmitting-receiving protocol conversion, be connected to by connector
The edge of breadboard, can carry out communication test and cable rings are surveyed, as shown in Figure 7.
(2) application conditions
The application conditions of the invention are the single particle experiments for carrying out 1601ARH.It is surveyed when 1601ARH completes all parameters
Examination and functional test after, can single particle experiment implementation method through the invention complete its single particle experiment verifying and examination,
The work of identification etc. can also provide application and exploitation example under space radiation environment for user, be at massive information
The user for managing device, which promotes, provides technical support.Wherein, 1X/4X is provided for the single particle experiment design of 4 road 4X RapidIO
High speed Networking Design, may be directly applied to the system integration between application verification and typical plate；Two DDR high-speed memory controls
The single particle experiment realization of interface demonstrates the design function of interface compatibility DDR2/3, provides reference for subsequent application；Needle
To the design of the single particle experiment of debugging, reset, monitoring and low-speed communication interface testing, to setting under the premise of not influencing to apply
Meter function has carried out comprehensive verifying and single particle experiment examination, provides design model for the system integration of 1601ARH.More than
Design can be applied to the related device with same-interface single particle experiment verifying and application and development in.
The present invention is described in more detail in conjunction with specific embodiments, and the present invention includes but is not limited to following embodiment:
Embodiment 1
The design function of positive sample chip 1601ARH based on the high ground term mesh of core " magnanimity information processing device " carries out single-particle
Verification experimental verification design.1601ARH is integrated with 4 road 4X RapidIO high-speed interfaces, can use simultaneously, can also separate single channel
Use, can also work under 1X/4X different working modes, and can 1X/4X it is mixed, unicast communication data transfer rate reaches
2.5Gbps.1601ARH is integrated with two-way DDR controller interface, and compatible DDR2/3, two interface functions are identical, but mutually
It is independent, working frequency 400MHz；Its JTAG debugging interface designed has more two EMU signals than general debugging interface, is used for
The debugging of PPC and DSP core is selected, INT signal can be configured to status signal monitoring operational process；4 integrated road low-speed communications
Interface UART can meet the needs of different agreement and different communication rate；Flouride-resistani acid phesphatase design has been carried out, has had single-particle inversion
(SEU error rate) (geostationary orbit) :≤10-5Mistake/device day, single event latch-up threshold value: >=75MeVcm2/mg
Anti-radiation performance.According to the design function and performance of 1601ARH, carried out using single particle experiment implementation method of the invention
Verification experimental verification design, can all standing its design function, assess its design performance parameter, the single particle experiment for being 1601ARH is examined
Hardware environment is provided with identification, provides design reference and debugging exploitation environment for user's promotion and application exploitation of monolithic integrated circuit.
By the debugging and use to the single particle test plate based on 1601ARH, the single-particle of magnanimity information processing device is tried
Test the design function of implementation method comprehensive verification 1601ARH, and complete Flouride-resistani acid phesphatase design performance index parameter test and
Verifying, by the user that single particle test plate extends to the single particle experiment design of other similar processors and national system integrates
In, the exploitation and verifying of application software can be carried out in single particle test plate, can be based on according to the demand of user
The application and development of 1601ARH provides excellent platform for the application verification of 1601ARH and application and development, also subsequent for project
Make smooth advances and established solid foundation.
The above content is merely illustrative of the invention's technical idea, and this does not limit the scope of protection of the present invention, all to press
According to technical idea proposed by the present invention, any changes made on the basis of the technical scheme each falls within claims of the present invention
Protection scope within.
Claims (8)
1. a kind of magnanimity information processing device single particle experiment implementation method, which comprises the following steps:
The 4 road RapidIO of 1601ARH are connected to the edge of pcb board by 4 connectors, carry out the communication of 4 road RapidIO
The step of verification experimental verification of function, interconnection test and self-looped testing；
It will be integrated in the ddr interface on PPC core in 1601ARH and carry out DDR2 and DDR3 function by integrated 3 DDR3+SDRAM
Compatible verification experimental verification, the test point that the ddr interface being integrated on network-on-chip reserves key signal carry out itself function monitor
The step of；
It is connected to FPGA while the debugging interface of 1601ARH is normally drawn, by converting integrated DSU interface in FPGA, into
The step of row debugging 1601ARH over long distances；
Reset signal and interrupt signal are accessed into FPGA, the step of resetted by debugging interface and test the monitoring of process；
The 4 road low-speed communication interfaces of 1601ARH are connected to transceiver, the edge of pcb board are connected to by connector, and even
Reserved ring surveys interface before being connected to transceiver, carries out the communication function verification experimental verification of low-speed communication module and the step of self-looped testing
Suddenly；
Above-mentioned steps since any or appoint it is several start simultaneously at progresss, up to above-mentioned steps complete when terminate.
2. a kind of magnanimity information processing device single particle experiment implementation method according to claim 1, which is characterized in that described
Carry out the communication function of RapidIO, the verification experimental verification of interconnection test and self-looped testing method particularly includes:
The minimum system that 1601ARH is designed in 1601ARH single particle test plate generates 16 pairs of difference using 2 CDCM6208
Clock, when individually providing differential reference by the operating mode of 4 road 1X RapidIO for every road 4X RapidIO of 1601ARH
Clock makes 1601ARH work under 1X or 4X mode；It sends and receives signal after carrying out high-frequency resistance matching and filtering processing, leads to
It crosses the edge that 4 Samtec connectors are connected to pcb board, carries out communication function, interconnection test and the self-looped testing of RapidIO
Verification experimental verification.
3. a kind of magnanimity information processing device single particle experiment implementation method according to claim 1, which is characterized in that described
Two panels forms 32 data bit widths in 3 DDR3+SDRAM, and third piece only carries out the verifying of EDAC verifying function with least-significant byte.
4. a kind of magnanimity information processing device single particle experiment implementation method according to claim 1, which is characterized in that described
Carry out debugging 1601ARH's over long distances method particularly includes:
FPGA is connected to while the debugging interface of 1601ARH is normally drawn, integration logic is converted in FPGA, by 1601ARH's
JTAG debugging interface is converted to DSU interface, is converted into being connected to PC machine after 422 agreements by 422 transceivers after being picked out, and carries out
Debugging 1601ARH over long distances.
5. a kind of magnanimity information processing device single particle experiment implementation method according to claim 4, which is characterized in that described
Resetted and tested the monitoring of process method particularly includes:
The reset signal of 1601ARH provides after TPS70302 to FPGA after being generated by external reset switch, or is sent by DSU
Reset command generates reset signal to 1601ARH to FPGA, by FPGA, under the logic control of FPGA, is resetted and is tested
The monitoring of process.
6. a kind of magnanimity information processing device single particle experiment implementation method according to claim 1, which is characterized in that described
Carry out communication function verification experimental verification and the self-looped testing of low-speed communication module method particularly includes:
It after the 4 road low-speed communication interfaces of 1601ARH are picked out, reserves ring and surveys interface, turn carrying out level by level translator
After changing, it is connected to after 422 transceivers carry out transmitting-receiving protocol conversion, the edge of pcb board is connected to by DB35 connector, carries out low speed
The communication function verification experimental verification of communication module and self-looped testing.
7. a kind of magnanimity information processing device single particle test plate for implementing single particle experiment implementation method described in claim 1,
It is characterised in that it includes 1601ARH, 4 Samtec connectors being connect with the 4 road RapidIO interfaces of 1601ARH, with
2 CDCM6208 of the RECLK interface connection of 1601ARH, 3 connect with the ddr interface being integrated on 1601ARH on PPC core
It piece DDR3+SDRAM, the FPGA being connect with the debugging interface of 1601ARH and is connect with the 4 road low-speed communication interfaces of 1601ARH
422 serial ports transceivers；Wherein:
4 Samtec connectors are used to for the 4 road RapidIO of 1601ARH being connected to the edge of single particle test plate；
2 CDCM6208 press 4 road 1X for generating 16 pairs of differential clocks, and for every road 4X RapidIO of 1601ARH
The operating mode of RapidIO individually provides differential reference clock；
3 DDR3+SDRAM are laid out wiring by the topological structure of DDR2, and the test compatible for DDR2 and DDR3 function is tested
Card；
FPGA is used to be converted to the debugging interface of 1601ARH DSU interface, and provides reset signal for 1601ARH and interrupt letter
Number；
The 4 road low-speed communication interfaces of 1601ARH reserve ring before being connected to serial ports transceiver and survey interface, are used for low-speed communication mould
The self-looped testing of block and the verification experimental verification of communication function.
8. a kind of magnanimity information processing device single particle test plate according to claim 7, which is characterized in that further include to
FPGA provides the reset switch and TPS70302 power management chip of reset signal, and reset signal passes through after being generated by reset switch
TPS70302 is provided to FPGA.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111459739A (en) * | 2020-03-31 | 2020-07-28 | 西安微电子技术研究所 | QDR SRAM application verification board and verification method |
| CN112398877A (en) * | 2021-01-20 | 2021-02-23 | 北京燧原智能科技有限公司 | Control signal conversion circuit, intellectual property core and system-level chip |
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